xref: /rk3399_ARM-atf/bl2/aarch64/bl2_entrypoint.S (revision 6397bf6a99d785caa9b50016cd6c8eb76083c117)
1/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <asm_macros.S>
33#include <bl_common.h>
34
35
36	.globl	bl2_entrypoint
37
38
39
40func bl2_entrypoint
41	/*---------------------------------------------
42	 * Store the extents of the tzram available to
43	 * BL2 for future use. Use the opcode param to
44	 * allow implement other functions if needed.
45	 * ---------------------------------------------
46	 */
47	mov	x20, x0
48	mov	x21, x1
49
50	/* ---------------------------------------------
51	 * This is BL2 which is expected to be executed
52	 * only by the primary cpu (at least for now).
53	 * So, make sure no secondary has lost its way.
54	 * ---------------------------------------------
55	 */
56	mrs	x0, mpidr_el1
57	bl	platform_is_primary_cpu
58	cbz	x0, _panic
59
60	/* ---------------------------------------------
61	 * Set the exception vector to something sane.
62	 * ---------------------------------------------
63	 */
64	adr	x0, early_exceptions
65	msr	vbar_el1, x0
66
67	/* ---------------------------------------------
68	 * Enable the instruction cache, stack pointer
69	 * and data access alignment checks
70	 * ---------------------------------------------
71	 */
72	mov	x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
73	mrs	x0, sctlr_el1
74	orr	x0, x0, x1
75	msr	sctlr_el1, x0
76	isb
77
78	/* ---------------------------------------------
79	 * Check the opcodes out of paranoia.
80	 * ---------------------------------------------
81	 */
82	mov	x0, #RUN_IMAGE
83	cmp	x0, x20
84	b.ne	_panic
85
86	/* ---------------------------------------------
87	 * Zero out NOBITS sections. There are 2 of them:
88	 *   - the .bss section;
89	 *   - the coherent memory section.
90	 * ---------------------------------------------
91	 */
92	ldr	x0, =__BSS_START__
93	ldr	x1, =__BSS_SIZE__
94	bl	zeromem16
95
96	ldr	x0, =__COHERENT_RAM_START__
97	ldr	x1, =__COHERENT_RAM_UNALIGNED_SIZE__
98	bl	zeromem16
99
100	/* --------------------------------------------
101	 * Allocate a stack whose memory will be marked
102	 * as Normal-IS-WBWA when the MMU is enabled.
103	 * There is no risk of reading stale stack
104	 * memory after enabling the MMU as only the
105	 * primary cpu is running at the moment.
106	 * --------------------------------------------
107	 */
108	mrs	x0, mpidr_el1
109	bl	platform_set_stack
110
111	/* ---------------------------------------------
112	 * Perform early platform setup & platform
113	 * specific early arch. setup e.g. mmu setup
114	 * ---------------------------------------------
115	 */
116	mov	x0, x21
117	bl	bl2_early_platform_setup
118	bl	bl2_plat_arch_setup
119
120	/* ---------------------------------------------
121	 * Jump to main function.
122	 * ---------------------------------------------
123	 */
124	bl	bl2_main
125_panic:
126	b	_panic
127