1/* 2 * Copyright (c) 2013, ARM Limited. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <bl_common.h> 32#include <arch.h> 33 34 35 .globl bl2_entrypoint 36 37 38 .section entry_code, "ax"; .align 3 39 40 41bl2_entrypoint:; .type bl2_entrypoint, %function 42 /*--------------------------------------------- 43 * Store the extents of the tzram available to 44 * BL2 for future use. Use the opcode param to 45 * allow implement other functions if needed. 46 * --------------------------------------------- 47 */ 48 mov x20, x0 49 mov x21, x1 50 mov x22, x2 51 52 /* --------------------------------------------- 53 * This is BL2 which is expected to be executed 54 * only by the primary cpu (at least for now). 55 * So, make sure no secondary has lost its way. 56 * --------------------------------------------- 57 */ 58 bl read_mpidr 59 mov x19, x0 60 bl platform_is_primary_cpu 61 cbz x0, _panic 62 63 /* --------------------------------------------- 64 * Set the exception vector to something sane. 65 * --------------------------------------------- 66 */ 67 adr x0, early_exceptions 68 msr vbar_el1, x0 69 70 /* --------------------------------------------- 71 * Enable the instruction cache. 72 * --------------------------------------------- 73 */ 74 mrs x0, sctlr_el1 75 orr x0, x0, #SCTLR_I_BIT 76 msr sctlr_el1, x0 77 78 isb 79 80 /* -------------------------------------------- 81 * Give ourselves a small coherent stack to 82 * ease the pain of initializing the MMU 83 * -------------------------------------------- 84 */ 85 mov x0, x19 86 bl platform_set_coherent_stack 87 88 /* --------------------------------------------- 89 * Perform early platform setup & platform 90 * specific early arch. setup e.g. mmu setup 91 * --------------------------------------------- 92 */ 93 mov x0, x21 94 mov x1, x22 95 bl bl2_early_platform_setup 96 bl bl2_plat_arch_setup 97 98 /* --------------------------------------------- 99 * Give ourselves a stack allocated in Normal 100 * -IS-WBWA memory 101 * --------------------------------------------- 102 */ 103 mov x0, x19 104 bl platform_set_stack 105 106 /* --------------------------------------------- 107 * Jump to main function. 108 * --------------------------------------------- 109 */ 110 bl bl2_main 111_panic: 112 b _panic 113