14f6ad66aSAchin Gupta/* 2*a6f340feSSoby Mathew * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 34f6ad66aSAchin Gupta * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 54f6ad66aSAchin Gupta */ 64f6ad66aSAchin Gupta 7c10bd2ceSSandrine Bailleux#include <arch.h> 80a30cf54SAndrew Thoelke#include <asm_macros.S> 997043ac9SDan Handley#include <bl_common.h> 104f6ad66aSAchin Gupta 114f6ad66aSAchin Gupta 124f6ad66aSAchin Gupta .globl bl2_entrypoint 134f6ad66aSAchin Gupta 144f6ad66aSAchin Gupta 154f6ad66aSAchin Gupta 160a30cf54SAndrew Thoelkefunc bl2_entrypoint 174f6ad66aSAchin Gupta /*--------------------------------------------- 18*a6f340feSSoby Mathew * Save arguments x0 - x3 from BL1 for future 19*a6f340feSSoby Mathew * use. 204f6ad66aSAchin Gupta * --------------------------------------------- 214f6ad66aSAchin Gupta */ 22*a6f340feSSoby Mathew mov x20, x0 23*a6f340feSSoby Mathew mov x21, x1 24*a6f340feSSoby Mathew mov x22, x2 25*a6f340feSSoby Mathew mov x23, x3 264f6ad66aSAchin Gupta 274f6ad66aSAchin Gupta /* --------------------------------------------- 28c10bd2ceSSandrine Bailleux * Set the exception vector to something sane. 29c10bd2ceSSandrine Bailleux * --------------------------------------------- 30c10bd2ceSSandrine Bailleux */ 31c10bd2ceSSandrine Bailleux adr x0, early_exceptions 32c10bd2ceSSandrine Bailleux msr vbar_el1, x0 330c8d4fefSAchin Gupta isb 340c8d4fefSAchin Gupta 350c8d4fefSAchin Gupta /* --------------------------------------------- 360c8d4fefSAchin Gupta * Enable the SError interrupt now that the 370c8d4fefSAchin Gupta * exception vectors have been setup. 380c8d4fefSAchin Gupta * --------------------------------------------- 390c8d4fefSAchin Gupta */ 400c8d4fefSAchin Gupta msr daifclr, #DAIF_ABT_BIT 41c10bd2ceSSandrine Bailleux 42c10bd2ceSSandrine Bailleux /* --------------------------------------------- 43ec3c1003SAchin Gupta * Enable the instruction cache, stack pointer 44ec3c1003SAchin Gupta * and data access alignment checks 45c10bd2ceSSandrine Bailleux * --------------------------------------------- 46c10bd2ceSSandrine Bailleux */ 47ec3c1003SAchin Gupta mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 48c10bd2ceSSandrine Bailleux mrs x0, sctlr_el1 49ec3c1003SAchin Gupta orr x0, x0, x1 50c10bd2ceSSandrine Bailleux msr sctlr_el1, x0 51c10bd2ceSSandrine Bailleux isb 52c10bd2ceSSandrine Bailleux 5365f546a1SSandrine Bailleux /* --------------------------------------------- 5454dc71e7SAchin Gupta * Invalidate the RW memory used by the BL2 5554dc71e7SAchin Gupta * image. This includes the data and NOBITS 5654dc71e7SAchin Gupta * sections. This is done to safeguard against 5754dc71e7SAchin Gupta * possible corruption of this memory by dirty 5854dc71e7SAchin Gupta * cache lines in a system cache as a result of 5954dc71e7SAchin Gupta * use by an earlier boot loader stage. 6054dc71e7SAchin Gupta * --------------------------------------------- 6154dc71e7SAchin Gupta */ 6254dc71e7SAchin Gupta adr x0, __RW_START__ 6354dc71e7SAchin Gupta adr x1, __RW_END__ 6454dc71e7SAchin Gupta sub x1, x1, x0 6554dc71e7SAchin Gupta bl inv_dcache_range 6654dc71e7SAchin Gupta 6754dc71e7SAchin Gupta /* --------------------------------------------- 6865f546a1SSandrine Bailleux * Zero out NOBITS sections. There are 2 of them: 6965f546a1SSandrine Bailleux * - the .bss section; 7065f546a1SSandrine Bailleux * - the coherent memory section. 7165f546a1SSandrine Bailleux * --------------------------------------------- 7265f546a1SSandrine Bailleux */ 7365f546a1SSandrine Bailleux ldr x0, =__BSS_START__ 7465f546a1SSandrine Bailleux ldr x1, =__BSS_SIZE__ 75308d359bSDouglas Raillard bl zeromem 7665f546a1SSandrine Bailleux 77ab8707e6SSoby Mathew#if USE_COHERENT_MEM 7865f546a1SSandrine Bailleux ldr x0, =__COHERENT_RAM_START__ 7965f546a1SSandrine Bailleux ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 80308d359bSDouglas Raillard bl zeromem 81ab8707e6SSoby Mathew#endif 8265f546a1SSandrine Bailleux 834f6ad66aSAchin Gupta /* -------------------------------------------- 84754a2b7aSAchin Gupta * Allocate a stack whose memory will be marked 85754a2b7aSAchin Gupta * as Normal-IS-WBWA when the MMU is enabled. 86754a2b7aSAchin Gupta * There is no risk of reading stale stack 87754a2b7aSAchin Gupta * memory after enabling the MMU as only the 88754a2b7aSAchin Gupta * primary cpu is running at the moment. 894f6ad66aSAchin Gupta * -------------------------------------------- 904f6ad66aSAchin Gupta */ 9185a181ceSSoby Mathew bl plat_set_my_stack 924f6ad66aSAchin Gupta 934f6ad66aSAchin Gupta /* --------------------------------------------- 9451faada7SDouglas Raillard * Initialize the stack protector canary before 9551faada7SDouglas Raillard * any C code is called. 9651faada7SDouglas Raillard * --------------------------------------------- 9751faada7SDouglas Raillard */ 9851faada7SDouglas Raillard#if STACK_PROTECTOR_ENABLED 9951faada7SDouglas Raillard bl update_stack_protector_canary 10051faada7SDouglas Raillard#endif 10151faada7SDouglas Raillard 10251faada7SDouglas Raillard /* --------------------------------------------- 1034f6ad66aSAchin Gupta * Perform early platform setup & platform 1044f6ad66aSAchin Gupta * specific early arch. setup e.g. mmu setup 1054f6ad66aSAchin Gupta * --------------------------------------------- 1064f6ad66aSAchin Gupta */ 1075698c5b3SYatharth Kochar mov x0, x20 108*a6f340feSSoby Mathew mov x1, x21 109*a6f340feSSoby Mathew mov x2, x22 110*a6f340feSSoby Mathew mov x3, x23 111*a6f340feSSoby Mathew bl bl2_early_platform_setup2 112*a6f340feSSoby Mathew 1134f6ad66aSAchin Gupta bl bl2_plat_arch_setup 1144f6ad66aSAchin Gupta 1154f6ad66aSAchin Gupta /* --------------------------------------------- 1164f6ad66aSAchin Gupta * Jump to main function. 1174f6ad66aSAchin Gupta * --------------------------------------------- 1184f6ad66aSAchin Gupta */ 1194f6ad66aSAchin Gupta bl bl2_main 1201c3ea103SAntonio Nino Diaz 1211c3ea103SAntonio Nino Diaz /* --------------------------------------------- 1221c3ea103SAntonio Nino Diaz * Should never reach this point. 1231c3ea103SAntonio Nino Diaz * --------------------------------------------- 1241c3ea103SAntonio Nino Diaz */ 125a806dad5SJeenu Viswambharan no_ret plat_panic_handler 1261c3ea103SAntonio Nino Diaz 1278b779620SKévin Petitendfunc bl2_entrypoint 128