14f6ad66aSAchin Gupta/* 2308d359bSDouglas Raillard * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 34f6ad66aSAchin Gupta * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 54f6ad66aSAchin Gupta */ 64f6ad66aSAchin Gupta 7c10bd2ceSSandrine Bailleux#include <arch.h> 80a30cf54SAndrew Thoelke#include <asm_macros.S> 997043ac9SDan Handley#include <bl_common.h> 104f6ad66aSAchin Gupta 114f6ad66aSAchin Gupta 124f6ad66aSAchin Gupta .globl bl2_entrypoint 134f6ad66aSAchin Gupta 144f6ad66aSAchin Gupta 154f6ad66aSAchin Gupta 160a30cf54SAndrew Thoelkefunc bl2_entrypoint 174f6ad66aSAchin Gupta /*--------------------------------------------- 185698c5b3SYatharth Kochar * Save from x1 the extents of the tzram 195698c5b3SYatharth Kochar * available to BL2 for future use. 205698c5b3SYatharth Kochar * x0 is not currently used. 214f6ad66aSAchin Gupta * --------------------------------------------- 224f6ad66aSAchin Gupta */ 235698c5b3SYatharth Kochar mov x20, x1 244f6ad66aSAchin Gupta 254f6ad66aSAchin Gupta /* --------------------------------------------- 26c10bd2ceSSandrine Bailleux * Set the exception vector to something sane. 27c10bd2ceSSandrine Bailleux * --------------------------------------------- 28c10bd2ceSSandrine Bailleux */ 29c10bd2ceSSandrine Bailleux adr x0, early_exceptions 30c10bd2ceSSandrine Bailleux msr vbar_el1, x0 310c8d4fefSAchin Gupta isb 320c8d4fefSAchin Gupta 330c8d4fefSAchin Gupta /* --------------------------------------------- 340c8d4fefSAchin Gupta * Enable the SError interrupt now that the 350c8d4fefSAchin Gupta * exception vectors have been setup. 360c8d4fefSAchin Gupta * --------------------------------------------- 370c8d4fefSAchin Gupta */ 380c8d4fefSAchin Gupta msr daifclr, #DAIF_ABT_BIT 39c10bd2ceSSandrine Bailleux 40c10bd2ceSSandrine Bailleux /* --------------------------------------------- 41ec3c1003SAchin Gupta * Enable the instruction cache, stack pointer 42ec3c1003SAchin Gupta * and data access alignment checks 43c10bd2ceSSandrine Bailleux * --------------------------------------------- 44c10bd2ceSSandrine Bailleux */ 45ec3c1003SAchin Gupta mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 46c10bd2ceSSandrine Bailleux mrs x0, sctlr_el1 47ec3c1003SAchin Gupta orr x0, x0, x1 48c10bd2ceSSandrine Bailleux msr sctlr_el1, x0 49c10bd2ceSSandrine Bailleux isb 50c10bd2ceSSandrine Bailleux 5165f546a1SSandrine Bailleux /* --------------------------------------------- 5254dc71e7SAchin Gupta * Invalidate the RW memory used by the BL2 5354dc71e7SAchin Gupta * image. This includes the data and NOBITS 5454dc71e7SAchin Gupta * sections. This is done to safeguard against 5554dc71e7SAchin Gupta * possible corruption of this memory by dirty 5654dc71e7SAchin Gupta * cache lines in a system cache as a result of 5754dc71e7SAchin Gupta * use by an earlier boot loader stage. 5854dc71e7SAchin Gupta * --------------------------------------------- 5954dc71e7SAchin Gupta */ 6054dc71e7SAchin Gupta adr x0, __RW_START__ 6154dc71e7SAchin Gupta adr x1, __RW_END__ 6254dc71e7SAchin Gupta sub x1, x1, x0 6354dc71e7SAchin Gupta bl inv_dcache_range 6454dc71e7SAchin Gupta 6554dc71e7SAchin Gupta /* --------------------------------------------- 6665f546a1SSandrine Bailleux * Zero out NOBITS sections. There are 2 of them: 6765f546a1SSandrine Bailleux * - the .bss section; 6865f546a1SSandrine Bailleux * - the coherent memory section. 6965f546a1SSandrine Bailleux * --------------------------------------------- 7065f546a1SSandrine Bailleux */ 7165f546a1SSandrine Bailleux ldr x0, =__BSS_START__ 7265f546a1SSandrine Bailleux ldr x1, =__BSS_SIZE__ 73308d359bSDouglas Raillard bl zeromem 7465f546a1SSandrine Bailleux 75ab8707e6SSoby Mathew#if USE_COHERENT_MEM 7665f546a1SSandrine Bailleux ldr x0, =__COHERENT_RAM_START__ 7765f546a1SSandrine Bailleux ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 78308d359bSDouglas Raillard bl zeromem 79ab8707e6SSoby Mathew#endif 8065f546a1SSandrine Bailleux 814f6ad66aSAchin Gupta /* -------------------------------------------- 82754a2b7aSAchin Gupta * Allocate a stack whose memory will be marked 83754a2b7aSAchin Gupta * as Normal-IS-WBWA when the MMU is enabled. 84754a2b7aSAchin Gupta * There is no risk of reading stale stack 85754a2b7aSAchin Gupta * memory after enabling the MMU as only the 86754a2b7aSAchin Gupta * primary cpu is running at the moment. 874f6ad66aSAchin Gupta * -------------------------------------------- 884f6ad66aSAchin Gupta */ 8985a181ceSSoby Mathew bl plat_set_my_stack 904f6ad66aSAchin Gupta 914f6ad66aSAchin Gupta /* --------------------------------------------- 9251faada7SDouglas Raillard * Initialize the stack protector canary before 9351faada7SDouglas Raillard * any C code is called. 9451faada7SDouglas Raillard * --------------------------------------------- 9551faada7SDouglas Raillard */ 9651faada7SDouglas Raillard#if STACK_PROTECTOR_ENABLED 9751faada7SDouglas Raillard bl update_stack_protector_canary 9851faada7SDouglas Raillard#endif 9951faada7SDouglas Raillard 10051faada7SDouglas Raillard /* --------------------------------------------- 1014f6ad66aSAchin Gupta * Perform early platform setup & platform 1024f6ad66aSAchin Gupta * specific early arch. setup e.g. mmu setup 1034f6ad66aSAchin Gupta * --------------------------------------------- 1044f6ad66aSAchin Gupta */ 1055698c5b3SYatharth Kochar mov x0, x20 1064f6ad66aSAchin Gupta bl bl2_early_platform_setup 1074f6ad66aSAchin Gupta bl bl2_plat_arch_setup 1084f6ad66aSAchin Gupta 1094f6ad66aSAchin Gupta /* --------------------------------------------- 1104f6ad66aSAchin Gupta * Jump to main function. 1114f6ad66aSAchin Gupta * --------------------------------------------- 1124f6ad66aSAchin Gupta */ 1134f6ad66aSAchin Gupta bl bl2_main 1141c3ea103SAntonio Nino Diaz 1151c3ea103SAntonio Nino Diaz /* --------------------------------------------- 1161c3ea103SAntonio Nino Diaz * Should never reach this point. 1171c3ea103SAntonio Nino Diaz * --------------------------------------------- 1181c3ea103SAntonio Nino Diaz */ 119a806dad5SJeenu Viswambharan no_ret plat_panic_handler 1201c3ea103SAntonio Nino Diaz 1218b779620SKévin Petitendfunc bl2_entrypoint 122