14f6ad66aSAchin Gupta/* 2e83b0cadSDan Handley * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 34f6ad66aSAchin Gupta * 44f6ad66aSAchin Gupta * Redistribution and use in source and binary forms, with or without 54f6ad66aSAchin Gupta * modification, are permitted provided that the following conditions are met: 64f6ad66aSAchin Gupta * 74f6ad66aSAchin Gupta * Redistributions of source code must retain the above copyright notice, this 84f6ad66aSAchin Gupta * list of conditions and the following disclaimer. 94f6ad66aSAchin Gupta * 104f6ad66aSAchin Gupta * Redistributions in binary form must reproduce the above copyright notice, 114f6ad66aSAchin Gupta * this list of conditions and the following disclaimer in the documentation 124f6ad66aSAchin Gupta * and/or other materials provided with the distribution. 134f6ad66aSAchin Gupta * 144f6ad66aSAchin Gupta * Neither the name of ARM nor the names of its contributors may be used 154f6ad66aSAchin Gupta * to endorse or promote products derived from this software without specific 164f6ad66aSAchin Gupta * prior written permission. 174f6ad66aSAchin Gupta * 184f6ad66aSAchin Gupta * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 194f6ad66aSAchin Gupta * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 204f6ad66aSAchin Gupta * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 214f6ad66aSAchin Gupta * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 224f6ad66aSAchin Gupta * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 234f6ad66aSAchin Gupta * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 244f6ad66aSAchin Gupta * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 254f6ad66aSAchin Gupta * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 264f6ad66aSAchin Gupta * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 274f6ad66aSAchin Gupta * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 284f6ad66aSAchin Gupta * POSSIBILITY OF SUCH DAMAGE. 294f6ad66aSAchin Gupta */ 304f6ad66aSAchin Gupta 31c10bd2ceSSandrine Bailleux#include <arch.h> 320a30cf54SAndrew Thoelke#include <asm_macros.S> 3397043ac9SDan Handley#include <bl_common.h> 344f6ad66aSAchin Gupta 354f6ad66aSAchin Gupta 364f6ad66aSAchin Gupta .globl bl2_entrypoint 374f6ad66aSAchin Gupta 384f6ad66aSAchin Gupta 394f6ad66aSAchin Gupta 400a30cf54SAndrew Thoelkefunc bl2_entrypoint 414f6ad66aSAchin Gupta /*--------------------------------------------- 424f6ad66aSAchin Gupta * Store the extents of the tzram available to 434f6ad66aSAchin Gupta * BL2 for future use. Use the opcode param to 444f6ad66aSAchin Gupta * allow implement other functions if needed. 454f6ad66aSAchin Gupta * --------------------------------------------- 464f6ad66aSAchin Gupta */ 474f6ad66aSAchin Gupta mov x20, x0 484f6ad66aSAchin Gupta mov x21, x1 494f6ad66aSAchin Gupta mov x22, x2 504f6ad66aSAchin Gupta 514f6ad66aSAchin Gupta /* --------------------------------------------- 524f6ad66aSAchin Gupta * This is BL2 which is expected to be executed 534f6ad66aSAchin Gupta * only by the primary cpu (at least for now). 544f6ad66aSAchin Gupta * So, make sure no secondary has lost its way. 554f6ad66aSAchin Gupta * --------------------------------------------- 564f6ad66aSAchin Gupta */ 57*7935d0a5SAndrew Thoelke mrs x0, mpidr_el1 584f6ad66aSAchin Gupta bl platform_is_primary_cpu 594f6ad66aSAchin Gupta cbz x0, _panic 604f6ad66aSAchin Gupta 61c10bd2ceSSandrine Bailleux /* --------------------------------------------- 62c10bd2ceSSandrine Bailleux * Set the exception vector to something sane. 63c10bd2ceSSandrine Bailleux * --------------------------------------------- 64c10bd2ceSSandrine Bailleux */ 65c10bd2ceSSandrine Bailleux adr x0, early_exceptions 66c10bd2ceSSandrine Bailleux msr vbar_el1, x0 67c10bd2ceSSandrine Bailleux 68c10bd2ceSSandrine Bailleux /* --------------------------------------------- 69c10bd2ceSSandrine Bailleux * Enable the instruction cache. 70c10bd2ceSSandrine Bailleux * --------------------------------------------- 71c10bd2ceSSandrine Bailleux */ 72c10bd2ceSSandrine Bailleux mrs x0, sctlr_el1 73c10bd2ceSSandrine Bailleux orr x0, x0, #SCTLR_I_BIT 74c10bd2ceSSandrine Bailleux msr sctlr_el1, x0 75c10bd2ceSSandrine Bailleux isb 76c10bd2ceSSandrine Bailleux 7765f546a1SSandrine Bailleux /* --------------------------------------------- 7834edaed5SSandrine Bailleux * Check the opcodes out of paranoia. 7934edaed5SSandrine Bailleux * --------------------------------------------- 8034edaed5SSandrine Bailleux */ 8134edaed5SSandrine Bailleux mov x0, #RUN_IMAGE 8234edaed5SSandrine Bailleux cmp x0, x20 8334edaed5SSandrine Bailleux b.ne _panic 8434edaed5SSandrine Bailleux 8534edaed5SSandrine Bailleux /* --------------------------------------------- 8665f546a1SSandrine Bailleux * Zero out NOBITS sections. There are 2 of them: 8765f546a1SSandrine Bailleux * - the .bss section; 8865f546a1SSandrine Bailleux * - the coherent memory section. 8965f546a1SSandrine Bailleux * --------------------------------------------- 9065f546a1SSandrine Bailleux */ 9165f546a1SSandrine Bailleux ldr x0, =__BSS_START__ 9265f546a1SSandrine Bailleux ldr x1, =__BSS_SIZE__ 9365f546a1SSandrine Bailleux bl zeromem16 9465f546a1SSandrine Bailleux 9565f546a1SSandrine Bailleux ldr x0, =__COHERENT_RAM_START__ 9665f546a1SSandrine Bailleux ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 9765f546a1SSandrine Bailleux bl zeromem16 9865f546a1SSandrine Bailleux 994f6ad66aSAchin Gupta /* -------------------------------------------- 1004f6ad66aSAchin Gupta * Give ourselves a small coherent stack to 1014f6ad66aSAchin Gupta * ease the pain of initializing the MMU 1024f6ad66aSAchin Gupta * -------------------------------------------- 1034f6ad66aSAchin Gupta */ 104*7935d0a5SAndrew Thoelke mrs x0, mpidr_el1 1054f6ad66aSAchin Gupta bl platform_set_coherent_stack 1064f6ad66aSAchin Gupta 1074f6ad66aSAchin Gupta /* --------------------------------------------- 1084f6ad66aSAchin Gupta * Perform early platform setup & platform 1094f6ad66aSAchin Gupta * specific early arch. setup e.g. mmu setup 1104f6ad66aSAchin Gupta * --------------------------------------------- 1114f6ad66aSAchin Gupta */ 1124f6ad66aSAchin Gupta mov x0, x21 1134f6ad66aSAchin Gupta mov x1, x22 1144f6ad66aSAchin Gupta bl bl2_early_platform_setup 1154f6ad66aSAchin Gupta bl bl2_plat_arch_setup 1164f6ad66aSAchin Gupta 1174f6ad66aSAchin Gupta /* --------------------------------------------- 1184f6ad66aSAchin Gupta * Give ourselves a stack allocated in Normal 1194f6ad66aSAchin Gupta * -IS-WBWA memory 1204f6ad66aSAchin Gupta * --------------------------------------------- 1214f6ad66aSAchin Gupta */ 122*7935d0a5SAndrew Thoelke mrs x0, mpidr_el1 1234f6ad66aSAchin Gupta bl platform_set_stack 1244f6ad66aSAchin Gupta 1254f6ad66aSAchin Gupta /* --------------------------------------------- 1264f6ad66aSAchin Gupta * Jump to main function. 1274f6ad66aSAchin Gupta * --------------------------------------------- 1284f6ad66aSAchin Gupta */ 1294f6ad66aSAchin Gupta bl bl2_main 1304f6ad66aSAchin Gupta_panic: 1314f6ad66aSAchin Gupta b _panic 132