1*4f6ad66aSAchin Gupta/* 2*4f6ad66aSAchin Gupta * Copyright (c) 2013, ARM Limited. All rights reserved. 3*4f6ad66aSAchin Gupta * 4*4f6ad66aSAchin Gupta * Redistribution and use in source and binary forms, with or without 5*4f6ad66aSAchin Gupta * modification, are permitted provided that the following conditions are met: 6*4f6ad66aSAchin Gupta * 7*4f6ad66aSAchin Gupta * Redistributions of source code must retain the above copyright notice, this 8*4f6ad66aSAchin Gupta * list of conditions and the following disclaimer. 9*4f6ad66aSAchin Gupta * 10*4f6ad66aSAchin Gupta * Redistributions in binary form must reproduce the above copyright notice, 11*4f6ad66aSAchin Gupta * this list of conditions and the following disclaimer in the documentation 12*4f6ad66aSAchin Gupta * and/or other materials provided with the distribution. 13*4f6ad66aSAchin Gupta * 14*4f6ad66aSAchin Gupta * Neither the name of ARM nor the names of its contributors may be used 15*4f6ad66aSAchin Gupta * to endorse or promote products derived from this software without specific 16*4f6ad66aSAchin Gupta * prior written permission. 17*4f6ad66aSAchin Gupta * 18*4f6ad66aSAchin Gupta * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*4f6ad66aSAchin Gupta * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*4f6ad66aSAchin Gupta * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*4f6ad66aSAchin Gupta * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*4f6ad66aSAchin Gupta * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*4f6ad66aSAchin Gupta * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*4f6ad66aSAchin Gupta * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*4f6ad66aSAchin Gupta * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*4f6ad66aSAchin Gupta * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*4f6ad66aSAchin Gupta * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*4f6ad66aSAchin Gupta * POSSIBILITY OF SUCH DAMAGE. 29*4f6ad66aSAchin Gupta */ 30*4f6ad66aSAchin Gupta 31*4f6ad66aSAchin Gupta#include <bl_common.h> 32*4f6ad66aSAchin Gupta 33*4f6ad66aSAchin Gupta 34*4f6ad66aSAchin Gupta .globl bl2_entrypoint 35*4f6ad66aSAchin Gupta 36*4f6ad66aSAchin Gupta 37*4f6ad66aSAchin Gupta .section entry_code, "ax"; .align 3 38*4f6ad66aSAchin Gupta 39*4f6ad66aSAchin Gupta 40*4f6ad66aSAchin Guptabl2_entrypoint:; .type bl2_entrypoint, %function 41*4f6ad66aSAchin Gupta /*--------------------------------------------- 42*4f6ad66aSAchin Gupta * Store the extents of the tzram available to 43*4f6ad66aSAchin Gupta * BL2 for future use. Use the opcode param to 44*4f6ad66aSAchin Gupta * allow implement other functions if needed. 45*4f6ad66aSAchin Gupta * --------------------------------------------- 46*4f6ad66aSAchin Gupta */ 47*4f6ad66aSAchin Gupta mov x20, x0 48*4f6ad66aSAchin Gupta mov x21, x1 49*4f6ad66aSAchin Gupta mov x22, x2 50*4f6ad66aSAchin Gupta 51*4f6ad66aSAchin Gupta /* --------------------------------------------- 52*4f6ad66aSAchin Gupta * This is BL2 which is expected to be executed 53*4f6ad66aSAchin Gupta * only by the primary cpu (at least for now). 54*4f6ad66aSAchin Gupta * So, make sure no secondary has lost its way. 55*4f6ad66aSAchin Gupta * --------------------------------------------- 56*4f6ad66aSAchin Gupta */ 57*4f6ad66aSAchin Gupta bl read_mpidr 58*4f6ad66aSAchin Gupta mov x19, x0 59*4f6ad66aSAchin Gupta bl platform_is_primary_cpu 60*4f6ad66aSAchin Gupta cbz x0, _panic 61*4f6ad66aSAchin Gupta 62*4f6ad66aSAchin Gupta /* -------------------------------------------- 63*4f6ad66aSAchin Gupta * Give ourselves a small coherent stack to 64*4f6ad66aSAchin Gupta * ease the pain of initializing the MMU 65*4f6ad66aSAchin Gupta * -------------------------------------------- 66*4f6ad66aSAchin Gupta */ 67*4f6ad66aSAchin Gupta mov x0, x19 68*4f6ad66aSAchin Gupta bl platform_set_coherent_stack 69*4f6ad66aSAchin Gupta 70*4f6ad66aSAchin Gupta /* --------------------------------------------- 71*4f6ad66aSAchin Gupta * Perform early platform setup & platform 72*4f6ad66aSAchin Gupta * specific early arch. setup e.g. mmu setup 73*4f6ad66aSAchin Gupta * --------------------------------------------- 74*4f6ad66aSAchin Gupta */ 75*4f6ad66aSAchin Gupta mov x0, x21 76*4f6ad66aSAchin Gupta mov x1, x22 77*4f6ad66aSAchin Gupta bl bl2_early_platform_setup 78*4f6ad66aSAchin Gupta bl bl2_plat_arch_setup 79*4f6ad66aSAchin Gupta 80*4f6ad66aSAchin Gupta /* --------------------------------------------- 81*4f6ad66aSAchin Gupta * Give ourselves a stack allocated in Normal 82*4f6ad66aSAchin Gupta * -IS-WBWA memory 83*4f6ad66aSAchin Gupta * --------------------------------------------- 84*4f6ad66aSAchin Gupta */ 85*4f6ad66aSAchin Gupta mov x0, x19 86*4f6ad66aSAchin Gupta bl platform_set_stack 87*4f6ad66aSAchin Gupta 88*4f6ad66aSAchin Gupta /* --------------------------------------------- 89*4f6ad66aSAchin Gupta * Jump to main function. 90*4f6ad66aSAchin Gupta * --------------------------------------------- 91*4f6ad66aSAchin Gupta */ 92*4f6ad66aSAchin Gupta bl bl2_main 93*4f6ad66aSAchin Gupta_panic: 94*4f6ad66aSAchin Gupta b _panic 95