14f6ad66aSAchin Gupta/* 2a6f340feSSoby Mathew * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 34f6ad66aSAchin Gupta * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 54f6ad66aSAchin Gupta */ 64f6ad66aSAchin Gupta 7c10bd2ceSSandrine Bailleux#include <arch.h> 80a30cf54SAndrew Thoelke#include <asm_macros.S> 9*09d40e0eSAntonio Nino Diaz#include <common/bl_common.h> 104f6ad66aSAchin Gupta 114f6ad66aSAchin Gupta 124f6ad66aSAchin Gupta .globl bl2_entrypoint 134f6ad66aSAchin Gupta 144f6ad66aSAchin Gupta 154f6ad66aSAchin Gupta 160a30cf54SAndrew Thoelkefunc bl2_entrypoint 174f6ad66aSAchin Gupta /*--------------------------------------------- 18a6f340feSSoby Mathew * Save arguments x0 - x3 from BL1 for future 19a6f340feSSoby Mathew * use. 204f6ad66aSAchin Gupta * --------------------------------------------- 214f6ad66aSAchin Gupta */ 22a6f340feSSoby Mathew mov x20, x0 23a6f340feSSoby Mathew mov x21, x1 24a6f340feSSoby Mathew mov x22, x2 25a6f340feSSoby Mathew mov x23, x3 264f6ad66aSAchin Gupta 274f6ad66aSAchin Gupta /* --------------------------------------------- 28c10bd2ceSSandrine Bailleux * Set the exception vector to something sane. 29c10bd2ceSSandrine Bailleux * --------------------------------------------- 30c10bd2ceSSandrine Bailleux */ 31c10bd2ceSSandrine Bailleux adr x0, early_exceptions 32c10bd2ceSSandrine Bailleux msr vbar_el1, x0 330c8d4fefSAchin Gupta isb 340c8d4fefSAchin Gupta 350c8d4fefSAchin Gupta /* --------------------------------------------- 360c8d4fefSAchin Gupta * Enable the SError interrupt now that the 370c8d4fefSAchin Gupta * exception vectors have been setup. 380c8d4fefSAchin Gupta * --------------------------------------------- 390c8d4fefSAchin Gupta */ 400c8d4fefSAchin Gupta msr daifclr, #DAIF_ABT_BIT 41c10bd2ceSSandrine Bailleux 42c10bd2ceSSandrine Bailleux /* --------------------------------------------- 43ec3c1003SAchin Gupta * Enable the instruction cache, stack pointer 44ec3c1003SAchin Gupta * and data access alignment checks 45c10bd2ceSSandrine Bailleux * --------------------------------------------- 46c10bd2ceSSandrine Bailleux */ 47ec3c1003SAchin Gupta mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 48c10bd2ceSSandrine Bailleux mrs x0, sctlr_el1 49ec3c1003SAchin Gupta orr x0, x0, x1 50c10bd2ceSSandrine Bailleux msr sctlr_el1, x0 51c10bd2ceSSandrine Bailleux isb 52c10bd2ceSSandrine Bailleux 5365f546a1SSandrine Bailleux /* --------------------------------------------- 5454dc71e7SAchin Gupta * Invalidate the RW memory used by the BL2 5554dc71e7SAchin Gupta * image. This includes the data and NOBITS 5654dc71e7SAchin Gupta * sections. This is done to safeguard against 5754dc71e7SAchin Gupta * possible corruption of this memory by dirty 5854dc71e7SAchin Gupta * cache lines in a system cache as a result of 5954dc71e7SAchin Gupta * use by an earlier boot loader stage. 6054dc71e7SAchin Gupta * --------------------------------------------- 6154dc71e7SAchin Gupta */ 6254dc71e7SAchin Gupta adr x0, __RW_START__ 6354dc71e7SAchin Gupta adr x1, __RW_END__ 6454dc71e7SAchin Gupta sub x1, x1, x0 6554dc71e7SAchin Gupta bl inv_dcache_range 6654dc71e7SAchin Gupta 6754dc71e7SAchin Gupta /* --------------------------------------------- 6865f546a1SSandrine Bailleux * Zero out NOBITS sections. There are 2 of them: 6965f546a1SSandrine Bailleux * - the .bss section; 7065f546a1SSandrine Bailleux * - the coherent memory section. 7165f546a1SSandrine Bailleux * --------------------------------------------- 7265f546a1SSandrine Bailleux */ 73f1722b69SSoby Mathew adrp x0, __BSS_START__ 74f1722b69SSoby Mathew add x0, x0, :lo12:__BSS_START__ 75f1722b69SSoby Mathew adrp x1, __BSS_END__ 76f1722b69SSoby Mathew add x1, x1, :lo12:__BSS_END__ 77f1722b69SSoby Mathew sub x1, x1, x0 78308d359bSDouglas Raillard bl zeromem 7965f546a1SSandrine Bailleux 80ab8707e6SSoby Mathew#if USE_COHERENT_MEM 81f1722b69SSoby Mathew adrp x0, __COHERENT_RAM_START__ 82f1722b69SSoby Mathew add x0, x0, :lo12:__COHERENT_RAM_START__ 83f1722b69SSoby Mathew adrp x1, __COHERENT_RAM_END_UNALIGNED__ 84f1722b69SSoby Mathew add x1, x1, :lo12:__COHERENT_RAM_END_UNALIGNED__ 85f1722b69SSoby Mathew sub x1, x1, x0 86308d359bSDouglas Raillard bl zeromem 87ab8707e6SSoby Mathew#endif 8865f546a1SSandrine Bailleux 894f6ad66aSAchin Gupta /* -------------------------------------------- 90754a2b7aSAchin Gupta * Allocate a stack whose memory will be marked 91754a2b7aSAchin Gupta * as Normal-IS-WBWA when the MMU is enabled. 92754a2b7aSAchin Gupta * There is no risk of reading stale stack 93754a2b7aSAchin Gupta * memory after enabling the MMU as only the 94754a2b7aSAchin Gupta * primary cpu is running at the moment. 954f6ad66aSAchin Gupta * -------------------------------------------- 964f6ad66aSAchin Gupta */ 9785a181ceSSoby Mathew bl plat_set_my_stack 984f6ad66aSAchin Gupta 994f6ad66aSAchin Gupta /* --------------------------------------------- 10051faada7SDouglas Raillard * Initialize the stack protector canary before 10151faada7SDouglas Raillard * any C code is called. 10251faada7SDouglas Raillard * --------------------------------------------- 10351faada7SDouglas Raillard */ 10451faada7SDouglas Raillard#if STACK_PROTECTOR_ENABLED 10551faada7SDouglas Raillard bl update_stack_protector_canary 10651faada7SDouglas Raillard#endif 10751faada7SDouglas Raillard 10851faada7SDouglas Raillard /* --------------------------------------------- 1094f6ad66aSAchin Gupta * Perform early platform setup & platform 1104f6ad66aSAchin Gupta * specific early arch. setup e.g. mmu setup 1114f6ad66aSAchin Gupta * --------------------------------------------- 1124f6ad66aSAchin Gupta */ 1135698c5b3SYatharth Kochar mov x0, x20 114a6f340feSSoby Mathew mov x1, x21 115a6f340feSSoby Mathew mov x2, x22 116a6f340feSSoby Mathew mov x3, x23 117a6f340feSSoby Mathew bl bl2_early_platform_setup2 118a6f340feSSoby Mathew 1194f6ad66aSAchin Gupta bl bl2_plat_arch_setup 1204f6ad66aSAchin Gupta 1214f6ad66aSAchin Gupta /* --------------------------------------------- 1224f6ad66aSAchin Gupta * Jump to main function. 1234f6ad66aSAchin Gupta * --------------------------------------------- 1244f6ad66aSAchin Gupta */ 1254f6ad66aSAchin Gupta bl bl2_main 1261c3ea103SAntonio Nino Diaz 1271c3ea103SAntonio Nino Diaz /* --------------------------------------------- 1281c3ea103SAntonio Nino Diaz * Should never reach this point. 1291c3ea103SAntonio Nino Diaz * --------------------------------------------- 1301c3ea103SAntonio Nino Diaz */ 131a806dad5SJeenu Viswambharan no_ret plat_panic_handler 1321c3ea103SAntonio Nino Diaz 1338b779620SKévin Petitendfunc bl2_entrypoint 134