1*e339d8f5SGatien Chevallier /* SPDX-License-Identifier: BSD-2-Clause */ 2*e339d8f5SGatien Chevallier /* 3*e339d8f5SGatien Chevallier * Copyright (C) 2026, STMicroelectronics - All Rights Reserved 4*e339d8f5SGatien Chevallier */ 5*e339d8f5SGatien Chevallier 6*e339d8f5SGatien Chevallier #ifndef __PTA_STM32MP_DEBUG_ACCESS_H 7*e339d8f5SGatien Chevallier #define __PTA_STM32MP_DEBUG_ACCESS_H 8*e339d8f5SGatien Chevallier 9*e339d8f5SGatien Chevallier #define PTA_STM32_DBG_ACCESS_UUID \ 10*e339d8f5SGatien Chevallier { 0xdd05bc8b, 0x9f3b, 0x49f0, \ 11*e339d8f5SGatien Chevallier { 0xb6, 0x49, 0x01, 0xaa, 0x10, 0xc1, 0xc2, 0x10 } } 12*e339d8f5SGatien Chevallier 13*e339d8f5SGatien Chevallier enum stm32_pta_dbg_profile { 14*e339d8f5SGatien Chevallier /* Embedded debug peripherals support */ 15*e339d8f5SGatien Chevallier PTA_STM32_DEBUG_PERIPHERAL_DBG_PROFILE = 0, 16*e339d8f5SGatien Chevallier /* Hardware Debug Port (HDP) support (internal signals observation) */ 17*e339d8f5SGatien Chevallier PTA_STM32_DEBUG_HDP_DBG_PROFILE = 1, 18*e339d8f5SGatien Chevallier }; 19*e339d8f5SGatien Chevallier 20*e339d8f5SGatien Chevallier /** 21*e339d8f5SGatien Chevallier * PTA_STM32_DEBUG_CMD_GRANT_DBG_ACCESS 22*e339d8f5SGatien Chevallier * 23*e339d8f5SGatien Chevallier * [in] value[0].a Debug configuration to grant access to. 24*e339d8f5SGatien Chevallier * See enum stm32_pta_dbg_profile. 25*e339d8f5SGatien Chevallier * 26*e339d8f5SGatien Chevallier * Return codes: 27*e339d8f5SGatien Chevallier * TEE_SUCCESS - Invoke command success 28*e339d8f5SGatien Chevallier * TEE_ERROR_BAD_PARAMETERS - Incorrect input param 29*e339d8f5SGatien Chevallier * TEE_ERROR_ACCESS_DENIED - Debug services access not granted 30*e339d8f5SGatien Chevallier */ 31*e339d8f5SGatien Chevallier #define PTA_STM32_DEBUG_CMD_GRANT_DBG_ACCESS 0x0 32*e339d8f5SGatien Chevallier 33*e339d8f5SGatien Chevallier #endif /* __PTA_STM32MP_DEBUG_ACCESS_H */ 34