1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries.
4 */
5
6 #include <io.h>
7 #include <mm/core_mmu.h>
8 #include <stdint.h>
9 #include <string.h>
10
11 #include "dsp.h"
12 #include "pas.h"
13
14 #define CBCR_BRANCH_ENABLE_BIT BIT(0)
15 #define CBCR_HW_CTL_ENABLE_BIT BIT(1)
16
17 #define BOOT_CORE_START BIT(0)
18 #define BOOT_CMD_START BIT(0)
19 #define BOOT_FSM_TIMEOUT 10000
20
dsp_fw_start(struct qcom_pas_data * data,const struct dsp_fw_boot_regs * regs)21 TEE_Result dsp_fw_start(struct qcom_pas_data *data,
22 const struct dsp_fw_boot_regs *regs)
23 {
24 vaddr_t base = io_pa_or_va(&data->base, data->size);
25 uint64_t timeout;
26
27 if (!regs)
28 return TEE_ERROR_BAD_PARAMETERS;
29
30 io_write32(base + regs->xo_cbcr, CBCR_BRANCH_ENABLE_BIT);
31 io_write32(base + regs->sleep_cbcr, CBCR_BRANCH_ENABLE_BIT);
32
33 if (data->pas_id == PAS_ID_TURING)
34 io_write32(base + regs->core_cbcr,
35 CBCR_BRANCH_ENABLE_BIT | CBCR_HW_CTL_ENABLE_BIT);
36 else
37 io_write32(base + regs->core_cbcr, CBCR_BRANCH_ENABLE_BIT);
38
39 io_write32(base + regs->rst_evb, data->fw_base >> 4);
40 dsb();
41
42 io_write32(base + regs->core_start, BOOT_CORE_START);
43 io_write32(base + regs->boot_cmd, BOOT_CMD_START);
44
45 timeout = timeout_init_us(BOOT_FSM_TIMEOUT);
46
47 while (!timeout_elapsed(timeout)) {
48 if (io_read32(base + regs->boot_status) & BIT(0))
49 return TEE_SUCCESS;
50
51 udelay(10);
52 }
53
54 EMSG("Timed out waiting for DSP to boot");
55
56 return TEE_ERROR_TIMEOUT;
57 }
58
59