1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (C) STMicroelectronics 2024 - All Rights Reserved 4 */ 5 6 #ifndef _DT_BINDINGS_RESET_ST_STM32MP25_RCC_H_ 7 #define _DT_BINDINGS_RESET_ST_STM32MP25_RCC_H_ 8 9 #define TIM1_R 0 10 #define TIM2_R 1 11 #define TIM3_R 2 12 #define TIM4_R 3 13 #define TIM5_R 4 14 #define TIM6_R 5 15 #define TIM7_R 6 16 #define TIM8_R 7 17 #define TIM10_R 8 18 #define TIM11_R 9 19 #define TIM12_R 10 20 #define TIM13_R 11 21 #define TIM14_R 12 22 #define TIM15_R 13 23 #define TIM16_R 14 24 #define TIM17_R 15 25 #define TIM20_R 16 26 #define LPTIM1_R 17 27 #define LPTIM2_R 18 28 #define LPTIM3_R 19 29 #define LPTIM4_R 20 30 #define LPTIM5_R 21 31 #define SPI1_R 22 32 #define SPI2_R 23 33 #define SPI3_R 24 34 #define SPI4_R 25 35 #define SPI5_R 26 36 #define SPI6_R 27 37 #define SPI7_R 28 38 #define SPI8_R 29 39 #define SPDIFRX_R 30 40 #define USART1_R 31 41 #define USART2_R 32 42 #define USART3_R 33 43 #define UART4_R 34 44 #define UART5_R 35 45 #define USART6_R 36 46 #define UART7_R 37 47 #define UART8_R 38 48 #define UART9_R 39 49 #define LPUART1_R 40 50 #define IS2M_R 41 51 #define I2C1_R 42 52 #define I2C2_R 43 53 #define I2C3_R 44 54 #define I2C4_R 45 55 #define I2C5_R 46 56 #define I2C6_R 47 57 #define I2C7_R 48 58 #define I2C8_R 49 59 #define SAI1_R 50 60 #define SAI2_R 51 61 #define SAI3_R 52 62 #define SAI4_R 53 63 #define MDF1_R 54 64 #define MDF2_R 55 65 #define FDCAN_R 56 66 #define HDP_R 57 67 #define ADC12_R 58 68 #define ADC3_R 59 69 #define ETH1_R 60 70 #define ETH2_R 61 71 #define USB2_R 62 72 #define USB2PHY1_R 63 73 #define USB2PHY2_R 64 74 #define USB3DR_R 65 75 #define USB3PCIEPHY_R 66 76 #define USBTC_R 67 77 #define ETHSW_R 68 78 #define SDMMC1_R 69 79 #define SDMMC1DLL_R 70 80 #define SDMMC2_R 71 81 #define SDMMC2DLL_R 72 82 #define SDMMC3_R 73 83 #define SDMMC3DLL_R 74 84 #define GPU_R 75 85 #define LTDC_R 76 86 #define DSI_R 77 87 #define LVDS_R 78 88 #define CSI_R 79 89 #define DCMIPP_R 80 90 #define CCI_R 81 91 #define VDEC_R 82 92 #define VENC_R 83 93 #define WWDG1_R 84 94 #define WWDG2_R 85 95 #define VREF_R 86 96 #define DTS_R 87 97 #define CRC_R 88 98 #define SERC_R 89 99 #define OSPIIOM_R 90 100 #define I3C1_R 91 101 #define I3C2_R 92 102 #define I3C3_R 93 103 #define I3C4_R 94 104 #define IWDG2_KER_R 95 105 #define IWDG4_KER_R 96 106 #define RNG_R 97 107 #define PKA_R 98 108 #define SAES_R 99 109 #define HASH_R 100 110 #define CRYP1_R 101 111 #define CRYP2_R 102 112 #define PCIE_R 103 113 #define OSPI1_R 104 114 #define OSPI1DLL_R 105 115 #define OSPI2_R 106 116 #define OSPI2DLL_R 107 117 #define FMC_R 108 118 #define DBG_R 109 119 #define GPIOA_R 110 120 #define GPIOB_R 111 121 #define GPIOC_R 112 122 #define GPIOD_R 113 123 #define GPIOE_R 114 124 #define GPIOF_R 115 125 #define GPIOG_R 116 126 #define GPIOH_R 117 127 #define GPIOI_R 118 128 #define GPIOJ_R 119 129 #define GPIOK_R 120 130 #define GPIOZ_R 121 131 #define HPDMA1_R 122 132 #define HPDMA2_R 123 133 #define HPDMA3_R 124 134 #define LPDMA_R 125 135 #define HSEM_R 126 136 #define IPCC1_R 127 137 #define IPCC2_R 128 138 #define C2_HOLDBOOT_R 129 139 #define C1_HOLDBOOT_R 130 140 #define C1_R 131 141 #define C1P1POR_R 132 142 #define C1P1_R 133 143 #define C2_R 134 144 #define C3_R 135 145 #define SYS_R 136 146 #define VSW_R 137 147 #define C1MS_R 138 148 #define DDRCP_R 139 149 #define DDRCAPB_R 140 150 #define DDRPHYCAPB_R 141 151 #define DDRCFG_R 142 152 #define DDR_R 143 153 #define IWDG1_SYS_R 144 154 #define IWDG2_SYS_R 145 155 #define IWDG3_SYS_R 146 156 #define IWDG4_SYS_R 147 157 158 #define STM32MP25_LAST_RESET 148 159 160 #define RST_SCMI_C1_R 0 161 #define RST_SCMI_C2_R 1 162 #define RST_SCMI_C1_HOLDBOOT_R 2 163 #define RST_SCMI_C2_HOLDBOOT_R 3 164 #define RST_SCMI_FMC 4 165 #define RST_SCMI_OSPI1 5 166 #define RST_SCMI_OSPI1DLL 6 167 #define RST_SCMI_OSPI2 7 168 #define RST_SCMI_OSPI2DLL 8 169 170 #endif /* _DT_BINDINGS_RESET_ST_STM32MP25_RCC_H_ */ 171