1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2025, STMicroelectronics 4 */ 5 #ifndef _DT_BINDINGS_FIREWALL_STM32MP21_RIFSC_H 6 #define _DT_BINDINGS_FIREWALL_STM32MP21_RIFSC_H 7 8 /* RIFSC ID */ 9 #define STM32MP21_RIFSC_TIM1_ID 0 10 #define STM32MP21_RIFSC_TIM2_ID 1 11 #define STM32MP21_RIFSC_TIM3_ID 2 12 #define STM32MP21_RIFSC_TIM4_ID 3 13 #define STM32MP21_RIFSC_TIM5_ID 4 14 #define STM32MP21_RIFSC_TIM6_ID 5 15 #define STM32MP21_RIFSC_TIM7_ID 6 16 #define STM32MP21_RIFSC_TIM8_ID 7 17 #define STM32MP21_RIFSC_TIM10_ID 8 18 #define STM32MP21_RIFSC_TIM11_ID 9 19 #define STM32MP21_RIFSC_TIM12_ID 10 20 #define STM32MP21_RIFSC_TIM13_ID 11 21 #define STM32MP21_RIFSC_TIM14_ID 12 22 #define STM32MP21_RIFSC_TIM15_ID 13 23 #define STM32MP21_RIFSC_TIM16_ID 14 24 #define STM32MP21_RIFSC_TIM17_ID 15 25 #define STM32MP21_RIFSC_LPTIM1_ID 17 26 #define STM32MP21_RIFSC_LPTIM2_ID 18 27 #define STM32MP21_RIFSC_LPTIM3_ID 19 28 #define STM32MP21_RIFSC_LPTIM4_ID 20 29 #define STM32MP21_RIFSC_LPTIM5_ID 21 30 #define STM32MP21_RIFSC_SPI1_ID 22 31 #define STM32MP21_RIFSC_SPI2_ID 23 32 #define STM32MP21_RIFSC_SPI3_ID 24 33 #define STM32MP21_RIFSC_SPI4_ID 25 34 #define STM32MP21_RIFSC_SPI5_ID 26 35 #define STM32MP21_RIFSC_SPI6_ID 27 36 #define STM32MP21_RIFSC_SPDIFRX_ID 30 37 #define STM32MP21_RIFSC_USART1_ID 31 38 #define STM32MP21_RIFSC_USART2_ID 32 39 #define STM32MP21_RIFSC_USART3_ID 33 40 #define STM32MP21_RIFSC_UART4_ID 34 41 #define STM32MP21_RIFSC_UART5_ID 35 42 #define STM32MP21_RIFSC_USART6_ID 36 43 #define STM32MP21_RIFSC_UART7_ID 37 44 #define STM32MP21_RIFSC_LPUART1_ID 40 45 #define STM32MP21_RIFSC_I2C1_ID 41 46 #define STM32MP21_RIFSC_I2C2_ID 42 47 #define STM32MP21_RIFSC_I2C3_ID 43 48 #define STM32MP21_RIFSC_SAI1_ID 49 49 #define STM32MP21_RIFSC_SAI2_ID 50 50 #define STM32MP21_RIFSC_SAI3_ID 51 51 #define STM32MP21_RIFSC_SAI4_ID 52 52 #define STM32MP21_RIFSC_MDF1_ID 54 53 #define STM32MP21_RIFSC_FDCAN_ID 56 54 #define STM32MP21_RIFSC_HDP_ID 57 55 #define STM32MP21_RIFSC_ADC1_ID 58 56 #define STM32MP21_RIFSC_ADC2_ID 59 57 #define STM32MP21_RIFSC_ETH1_ID 60 58 #define STM32MP21_RIFSC_ETH2_ID 61 59 #define STM32MP21_RIFSC_USBH_ID 63 60 #define STM32MP21_RIFSC_OTG_HS_ID 66 61 #define STM32MP21_RIFSC_DDRPERFM_ID 67 62 #define STM32MP21_RIFSC_STGEN_ID 73 63 #define STM32MP21_RIFSC_OCTOSPI1_ID 74 64 #define STM32MP21_RIFSC_SDMMC1_ID 76 65 #define STM32MP21_RIFSC_SDMMC2_ID 77 66 #define STM32MP21_RIFSC_SDMMC3_ID 78 67 #define STM32MP21_RIFSC_LTDC_CMN_ID 80 68 #define STM32MP21_RIFSC_CSI_ID 86 69 #define STM32MP21_RIFSC_DCMIPP_ID 87 70 #define STM32MP21_RIFSC_DCMI_PSSI_ID 88 71 #define STM32MP21_RIFSC_RNG1_ID 92 72 #define STM32MP21_RIFSC_RNG2_ID 93 73 #define STM32MP21_RIFSC_PKA_ID 94 74 #define STM32MP21_RIFSC_SAES_ID 95 75 #define STM32MP21_RIFSC_HASH1_ID 96 76 #define STM32MP21_RIFSC_HASH2_ID 97 77 #define STM32MP21_RIFSC_CRYP1_ID 98 78 #define STM32MP21_RIFSC_CRYP2_ID 99 79 #define STM32MP21_RIFSC_IWDG1_ID 100 80 #define STM32MP21_RIFSC_IWDG2_ID 101 81 #define STM32MP21_RIFSC_IWDG3_ID 102 82 #define STM32MP21_RIFSC_IWDG4_ID 103 83 #define STM32MP21_RIFSC_WWDG1_ID 104 84 #define STM32MP21_RIFSC_VREFBUF_ID 106 85 #define STM32MP21_RIFSC_DTS_ID 107 86 #define STM32MP21_RIFSC_RAMCFG_ID 108 87 #define STM32MP21_RIFSC_CRC_ID 109 88 #define STM32MP21_RIFSC_SERC_ID 110 89 #define STM32MP21_RIFSC_I3C1_ID 114 90 #define STM32MP21_RIFSC_I3C2_ID 115 91 #define STM32MP21_RIFSC_I3C3_ID 116 92 #define STM32MP21_RIFSC_ICACHE_DCACHE_ID 118 93 #define STM32MP21_RIFSC_LTDC_L1L2_ID 119 94 #define STM32MP21_RIFSC_LTDC_L3_ID 120 95 #define STM32MP21_RIFSC_OTFDEC1_ID 125 96 #define STM32MP21_RIFSC_IAC_ID 127 97 98 /* RIF-aware IPs */ 99 #define STM32MP21_RIFSC_PWR_ID 155 100 #define STM32MP21_RIFSC_GPIOA_ID 160 101 #define STM32MP21_RIFSC_GPIOB_ID 161 102 #define STM32MP21_RIFSC_GPIOC_ID 162 103 #define STM32MP21_RIFSC_GPIOD_ID 163 104 #define STM32MP21_RIFSC_GPIOE_ID 164 105 #define STM32MP21_RIFSC_GPIOF_ID 165 106 #define STM32MP21_RIFSC_GPIOG_ID 166 107 #define STM32MP21_RIFSC_GPIOH_ID 167 108 #define STM32MP21_RIFSC_GPIOI_ID 168 109 #define STM32MP21_RIFSC_GPIOZ_ID 171 110 111 /* Global lock bindings */ 112 #define RIFSC_RIMU_GLOCK 1 113 #define RIFSC_RISUP_GLOCK 2 114 115 /* masters ID */ 116 #define RIMU_ID_OFFSET 200 117 #define RIMU_ID(idx) ((idx) + RIMU_ID_OFFSET) 118 119 /* 120 * CID selection mode 121 * RIF_CIDSEL_P configuration by hardware or inherited from RISUP 122 * RIF_CIDSEL_M configuration from provided RIMU data 123 */ 124 #define RIF_CIDSEL_P 0 125 #define RIF_CIDSEL_M 1 126 127 #define RIMUPROT_RIMC_M_ID_SHIFT 0 128 #define RIMUPROT_RIMC_MODE_SHIFT 10 129 #define RIMUPROT_RIMC_MCID_SHIFT 12 130 #define RIMUPROT_RIMC_MSEC_SHIFT 16 131 #define RIMUPROT_RIMC_MPRIV_SHIFT 17 132 #define RIMUPROT_RIMC_ATTRx_SHIFT 8 133 #define RIMUPROT_RIMC_M_ID_MASK GENMASK_32(7, 0) 134 #define RIMUPROT_RIMC_MCID_MASK GENMASK_32(15, 12) 135 #define RIMUPROT_RIMC_ATTRx_MASK (BIT(RIMUPROT_RIMC_MODE_SHIFT) | \ 136 RIMUPROT_RIMC_MCID_MASK | \ 137 BIT(RIMUPROT_RIMC_MSEC_SHIFT) | \ 138 BIT(RIMUPROT_RIMC_MPRIV_SHIFT)) 139 140 #define RIMUPROT(rimuid, mcid, msec, mpriv, mode) \ 141 (((rimuid) << RIMUPROT_RIMC_M_ID_SHIFT) | \ 142 ((mpriv) << RIMUPROT_RIMC_MPRIV_SHIFT) | \ 143 ((msec) << RIMUPROT_RIMC_MSEC_SHIFT) | \ 144 ((mcid) << RIMUPROT_RIMC_MCID_SHIFT) | \ 145 ((mode) << RIMUPROT_RIMC_MODE_SHIFT)) 146 147 #endif /* _DT_BINDINGS_STM32_RIFSC_H */ 148