1 /* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */ 2 /* 3 * Copyright (C) 2021 Microchip 4 * 5 * This header provides constants for AT91 pmc status. 6 * 7 * The constants defined in this header are being used in dts. 8 */ 9 10 #ifndef _DT_BINDINGS_CLK_AT91_H 11 #define _DT_BINDINGS_CLK_AT91_H 12 13 #define PMC_TYPE_CORE 0 14 #define PMC_TYPE_SYSTEM 1 15 #define PMC_TYPE_PERIPHERAL 2 16 #define PMC_TYPE_GCK 3 17 #define PMC_TYPE_PROGRAMMABLE 4 18 19 #define PMC_SLOW 0 20 #define PMC_MCK 1 21 #define PMC_UTMI 2 22 #define PMC_MAIN 3 23 #define PMC_MCK2 4 24 #define PMC_I2S0_MUX 5 25 #define PMC_I2S1_MUX 6 26 #define PMC_PLLACK 7 27 #define PMC_PLLBCK 8 28 #define PMC_AUDIOPLLCK 9 29 #define PMC_MCK_PRES 10 30 #define PMC_AUDIOPLL_FRACCK 11 31 #define PMC_USBCK 12 32 #define PMC_SAMA5D2_CORE_CLK_COUNT 13 33 34 /* SAMA7G5 */ 35 #define PMC_CPUPLL (PMC_MAIN + 1) 36 #define PMC_SYSPLL (PMC_MAIN + 2) 37 #define PMC_DDRPLL (PMC_MAIN + 3) 38 #define PMC_IMGPLL (PMC_MAIN + 4) 39 #define PMC_BAUDPLL (PMC_MAIN + 5) 40 #define PMC_AUDIOPMCPLL (PMC_MAIN + 6) 41 #define PMC_AUDIOIOPLL (PMC_MAIN + 7) 42 #define PMC_ETHPLL (PMC_MAIN + 8) 43 #define PMC_CPU (PMC_MAIN + 9) 44 45 #define AT91_SCMI_CLK_CORE_MCK 0 46 #define AT91_SCMI_CLK_CORE_UTMI 1 47 #define AT91_SCMI_CLK_CORE_MAIN 2 48 #define AT91_SCMI_CLK_CORE_MCK2 3 49 #define AT91_SCMI_CLK_CORE_I2S0_MUX 4 50 #define AT91_SCMI_CLK_CORE_I2S1_MUX 5 51 #define AT91_SCMI_CLK_CORE_PLLACK 6 52 #define AT91_SCMI_CLK_CORE_PLLBCK 7 53 #define AT91_SCMI_CLK_CORE_AUDIOPLLCK 8 54 #define AT91_SCMI_CLK_CORE_MCK_PRES 9 55 56 #define AT91_SCMI_CLK_SYSTEM_DDRCK 10 57 #define AT91_SCMI_CLK_SYSTEM_LCDCK 11 58 #define AT91_SCMI_CLK_SYSTEM_UHPCK 12 59 #define AT91_SCMI_CLK_SYSTEM_UDPCK 13 60 #define AT91_SCMI_CLK_SYSTEM_PCK0 14 61 #define AT91_SCMI_CLK_SYSTEM_PCK1 15 62 #define AT91_SCMI_CLK_SYSTEM_PCK2 16 63 #define AT91_SCMI_CLK_SYSTEM_ISCCK 17 64 65 #define AT91_SCMI_CLK_PERIPH_MACB0_CLK 18 66 #define AT91_SCMI_CLK_PERIPH_TDES_CLK 19 67 #define AT91_SCMI_CLK_PERIPH_MATRIX1_CLK 20 68 #define AT91_SCMI_CLK_PERIPH_HSMC_CLK 21 69 #define AT91_SCMI_CLK_PERIPH_PIOA_CLK 22 70 #define AT91_SCMI_CLK_PERIPH_FLX0_CLK 23 71 #define AT91_SCMI_CLK_PERIPH_FLX1_CLK 24 72 #define AT91_SCMI_CLK_PERIPH_FLX2_CLK 25 73 #define AT91_SCMI_CLK_PERIPH_FLX3_CLK 26 74 #define AT91_SCMI_CLK_PERIPH_FLX4_CLK 27 75 #define AT91_SCMI_CLK_PERIPH_UART0_CLK 28 76 #define AT91_SCMI_CLK_PERIPH_UART1_CLK 29 77 #define AT91_SCMI_CLK_PERIPH_UART2_CLK 30 78 #define AT91_SCMI_CLK_PERIPH_UART3_CLK 31 79 #define AT91_SCMI_CLK_PERIPH_UART4_CLK 32 80 #define AT91_SCMI_CLK_PERIPH_TWI0_CLK 33 81 #define AT91_SCMI_CLK_PERIPH_TWI1_CLK 34 82 #define AT91_SCMI_CLK_PERIPH_SPI0_CLK 35 83 #define AT91_SCMI_CLK_PERIPH_SPI1_CLK 36 84 #define AT91_SCMI_CLK_PERIPH_TCB0_CLK 37 85 #define AT91_SCMI_CLK_PERIPH_TCB1_CLK 38 86 #define AT91_SCMI_CLK_PERIPH_PWM_CLK 39 87 #define AT91_SCMI_CLK_PERIPH_ADC_CLK 40 88 #define AT91_SCMI_CLK_PERIPH_UHPHS_CLK 41 89 #define AT91_SCMI_CLK_PERIPH_UDPHS_CLK 42 90 #define AT91_SCMI_CLK_PERIPH_SSC0_CLK 43 91 #define AT91_SCMI_CLK_PERIPH_SSC1_CLK 44 92 #define AT91_SCMI_CLK_PERIPH_TRNG_CLK 45 93 #define AT91_SCMI_CLK_PERIPH_PDMIC_CLK 46 94 #define AT91_SCMI_CLK_PERIPH_SECURAM_CLK 47 95 #define AT91_SCMI_CLK_PERIPH_I2S0_CLK 48 96 #define AT91_SCMI_CLK_PERIPH_I2S1_CLK 49 97 #define AT91_SCMI_CLK_PERIPH_CAN0_CLK 50 98 #define AT91_SCMI_CLK_PERIPH_CAN1_CLK 51 99 #define AT91_SCMI_CLK_PERIPH_PTC_CLK 52 100 #define AT91_SCMI_CLK_PERIPH_CLASSD_CLK 53 101 #define AT91_SCMI_CLK_PERIPH_DMA0_CLK 54 102 #define AT91_SCMI_CLK_PERIPH_DMA1_CLK 55 103 #define AT91_SCMI_CLK_PERIPH_AES_CLK 56 104 #define AT91_SCMI_CLK_PERIPH_AESB_CLK 57 105 #define AT91_SCMI_CLK_PERIPH_SHA_CLK 58 106 #define AT91_SCMI_CLK_PERIPH_MPDDR_CLK 59 107 #define AT91_SCMI_CLK_PERIPH_MATRIX0_CLK 60 108 #define AT91_SCMI_CLK_PERIPH_SDMMC0_HCLK 61 109 #define AT91_SCMI_CLK_PERIPH_SDMMC1_HCLK 62 110 #define AT91_SCMI_CLK_PERIPH_LCDC_CLK 63 111 #define AT91_SCMI_CLK_PERIPH_ISC_CLK 64 112 #define AT91_SCMI_CLK_PERIPH_QSPI0_CLK 65 113 #define AT91_SCMI_CLK_PERIPH_QSPI1_CLK 66 114 115 #define AT91_SCMI_CLK_GCK_SDMMC0_GCLK 67 116 #define AT91_SCMI_CLK_GCK_SDMMC1_GCLK 68 117 #define AT91_SCMI_CLK_GCK_TCB0_GCLK 69 118 #define AT91_SCMI_CLK_GCK_TCB1_GCLK 70 119 #define AT91_SCMI_CLK_GCK_PWM_GCLK 71 120 #define AT91_SCMI_CLK_GCK_ISC_GCLK 72 121 #define AT91_SCMI_CLK_GCK_PDMIC_GCLK 73 122 #define AT91_SCMI_CLK_GCK_I2S0_GCLK 74 123 #define AT91_SCMI_CLK_GCK_I2S1_GCLK 75 124 #define AT91_SCMI_CLK_GCK_CAN0_GCLK 76 125 #define AT91_SCMI_CLK_GCK_CAN1_GCLK 77 126 #define AT91_SCMI_CLK_GCK_CLASSD_GCLK 78 127 128 #define AT91_SCMI_CLK_PROG_PROG0 79 129 #define AT91_SCMI_CLK_PROG_PROG1 80 130 #define AT91_SCMI_CLK_PROG_PROG2 81 131 132 #define AT91_SCMI_CLK_SCKC_SLOWCK_32K 82 133 134 #ifdef CFG_SAMA7G5 135 #define AT91_SCMI_CLK_CORE_CPUPLLCK 4 136 #define AT91_SCMI_CLK_CORE_SYSPLLCK 5 137 #define AT91_SCMI_CLK_CORE_DDRPLLCK 6 138 #define AT91_SCMI_CLK_CORE_IMGPLLCK 7 139 #define AT91_SCMI_CLK_CORE_ETHPLLCK 10 140 #define AT91_SCMI_CLK_SYSTEM_PCK3 11 141 #define AT91_SCMI_CLK_SYSTEM_PCK4 12 142 #define AT91_SCMI_CLK_SYSTEM_PCK5 13 143 #define AT91_SCMI_CLK_SYSTEM_PCK6 17 144 #define AT91_SCMI_CLK_SYSTEM_PCK7 20 145 #define AT91_SCMI_CLK_UTMI1 97 146 #define AT91_SCMI_CLK_UTMI2 98 147 #define AT91_SCMI_CLK_UTMI3 99 148 #define AT91_SCMI_CLK_PERIPH_DMA2_CLK 100 149 #define AT91_SCMI_CLK_PERIPH_FLX5_CLK 28 150 #define AT91_SCMI_CLK_PERIPH_FLX6_CLK 29 151 #define AT91_SCMI_CLK_PERIPH_FLX7_CLK 30 152 #define AT91_SCMI_CLK_PERIPH_FLX8_CLK 31 153 #define AT91_SCMI_CLK_PERIPH_FLX9_CLK 32 154 #define AT91_SCMI_CLK_PERIPH_FLX10_CLK 33 155 #define AT91_SCMI_CLK_PERIPH_FLX11_CLK 34 156 #define AT91_SCMI_CLK_PERIPH_UDPHSB_CLK 35 157 #define AT91_SCMI_CLK_PERIPH_PDMC1_CLK 36 158 #define AT91_SCMI_CLK_PERIPH_UDPHSA_CLK 42 159 #define AT91_SCMI_CLK_GCK_ADC_GCLK 40 160 #define AT91_SCMI_CLK_PERIPH_PDMC0_CLK 46 161 #define AT91_SCMI_CLK_PERIPH_CAN2_CLK 52 162 #define AT91_SCMI_CLK_PERIPH_CAN3_CLK 53 163 #define AT91_SCMI_CLK_PERIPH_CAN4_CLK 59 164 #define AT91_SCMI_CLK_PERIPH_CAN5_CLK 60 165 #define AT91_SCMI_CLK_PERIPH_SDMMC2_HCLK 63 166 #define AT91_SCMI_CLK_GCK_SDMMC2_GCLK 71 167 #define AT91_SCMI_CLK_GCK_MACB0_GCLK 72 168 #define AT91_SCMI_CLK_GCK_MACB0_TSU 73 169 #define AT91_SCMI_CLK_GCK_CAN2_GCLK 78 170 #define AT91_SCMI_CLK_GCK_CAN3_GCLK 79 171 #define AT91_SCMI_CLK_GCK_CAN4_GCLK 80 172 #define AT91_SCMI_CLK_GCK_CAN5_GCLK 81 173 #define AT91_SCMI_CLK_PERIPH_SPDIFRX_CLK 83 174 #define AT91_SCMI_CLK_PERIPH_SPDIFTX_CLK 84 175 #define AT91_SCMI_CLK_GCK_QSPI0_GCLK 85 176 #define AT91_SCMI_CLK_GCK_QSPI1_GCLK 86 177 #define AT91_SCMI_CLK_GCK_SPDIFRX_GCLK 87 178 #define AT91_SCMI_CLK_GCK_SPDIFTX_GCLK 88 179 #define AT91_SCMI_CLK_GCK_MACB1_GCLK 89 180 #define AT91_SCMI_CLK_PERIPH_MACB1_CLK 90 181 #define AT91_SCMI_CLK_GCK_MACB1_TSU 91 182 #define AT91_SCMI_CLK_PERIPH_CSI_CLK 92 183 #define AT91_SCMI_CLK_GCK_CSI_GCLK 93 184 #define AT91_SCMI_CLK_PERIPH_CSI2DC_CLK 94 185 #define AT91_SCMI_CLK_PERIPH_ASRC_CLK 95 186 #define AT91_SCMI_CLK_GCK_ASRC_GCLK 96 187 #endif 188 189 #endif 190