1 /* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */ 2 /* 3 * Copyright (C) 2021 Microchip 4 * 5 * This header provides constants for AT91 pmc status. 6 * 7 * The constants defined in this header are being used in dts. 8 */ 9 10 #ifndef _DT_BINDINGS_CLK_AT91_H 11 #define _DT_BINDINGS_CLK_AT91_H 12 13 #define PMC_TYPE_CORE 0 14 #define PMC_TYPE_SYSTEM 1 15 #define PMC_TYPE_PERIPHERAL 2 16 #define PMC_TYPE_GCK 3 17 #define PMC_TYPE_PROGRAMMABLE 4 18 19 #define PMC_SLOW 0 20 #define PMC_MCK 1 21 #define PMC_UTMI 2 22 #define PMC_MAIN 3 23 #define PMC_MCK2 4 24 #define PMC_I2S0_MUX 5 25 #define PMC_I2S1_MUX 6 26 #define PMC_PLLACK 7 27 #define PMC_PLLBCK 8 28 #define PMC_AUDIOPLLCK 9 29 #define PMC_MCK_PRES 10 30 #define PMC_AUDIOPLL_FRACCK 11 31 #define PMC_USBCK 12 32 #define PMC_SAMA5D2_CORE_CLK_COUNT 13 33 34 /* SAMA7G5 */ 35 #define PMC_CPUPLL (PMC_MAIN + 1) 36 #define PMC_SYSPLL (PMC_MAIN + 2) 37 #define PMC_DDRPLL (PMC_MAIN + 3) 38 #define PMC_IMGPLL (PMC_MAIN + 4) 39 #define PMC_BAUDPLL (PMC_MAIN + 5) 40 #define PMC_AUDIOPMCPLL (PMC_MAIN + 6) 41 /* Reserved for PMC_MCK_PRES */ 42 #define PMC_AUDIOIOPLL (PMC_MAIN + 8) 43 #define PMC_ETHPLL (PMC_MAIN + 9) 44 #define PMC_MCK1 (PMC_MAIN + 10) 45 /* Reserved for MCK2, MCK3, MCK4 */ 46 #define PMC_UTMI1 (PMC_MAIN + 14) 47 #define PMC_UTMI2 (PMC_MAIN + 15) 48 #define PMC_UTMI3 (PMC_MAIN + 16) 49 #define PMC_SAMA7G5_CORE_CLK_COUNT (PMC_MAIN + 17) 50 51 #define AT91_SCMI_CLK_CORE_MCK 0 52 #define AT91_SCMI_CLK_CORE_UTMI 1 53 #define AT91_SCMI_CLK_CORE_MAIN 2 54 #define AT91_SCMI_CLK_CORE_MCK2 3 55 #define AT91_SCMI_CLK_CORE_I2S0_MUX 4 56 #define AT91_SCMI_CLK_CORE_I2S1_MUX 5 57 #define AT91_SCMI_CLK_CORE_PLLACK 6 58 #define AT91_SCMI_CLK_CORE_PLLBCK 7 59 #define AT91_SCMI_CLK_CORE_AUDIOPLLCK 8 60 #define AT91_SCMI_CLK_CORE_MCK_PRES 9 61 62 #define AT91_SCMI_CLK_SYSTEM_DDRCK 10 63 #define AT91_SCMI_CLK_SYSTEM_LCDCK 11 64 #define AT91_SCMI_CLK_SYSTEM_UHPCK 12 65 #define AT91_SCMI_CLK_SYSTEM_UDPCK 13 66 #define AT91_SCMI_CLK_SYSTEM_PCK0 14 67 #define AT91_SCMI_CLK_SYSTEM_PCK1 15 68 #define AT91_SCMI_CLK_SYSTEM_PCK2 16 69 #define AT91_SCMI_CLK_SYSTEM_ISCCK 17 70 71 #define AT91_SCMI_CLK_PERIPH_MACB0_CLK 18 72 #define AT91_SCMI_CLK_PERIPH_TDES_CLK 19 73 #define AT91_SCMI_CLK_PERIPH_MATRIX1_CLK 20 74 #define AT91_SCMI_CLK_PERIPH_HSMC_CLK 21 75 #define AT91_SCMI_CLK_PERIPH_PIOA_CLK 22 76 #define AT91_SCMI_CLK_PERIPH_FLX0_CLK 23 77 #define AT91_SCMI_CLK_PERIPH_FLX1_CLK 24 78 #define AT91_SCMI_CLK_PERIPH_FLX2_CLK 25 79 #define AT91_SCMI_CLK_PERIPH_FLX3_CLK 26 80 #define AT91_SCMI_CLK_PERIPH_FLX4_CLK 27 81 #define AT91_SCMI_CLK_PERIPH_UART0_CLK 28 82 #define AT91_SCMI_CLK_PERIPH_UART1_CLK 29 83 #define AT91_SCMI_CLK_PERIPH_UART2_CLK 30 84 #define AT91_SCMI_CLK_PERIPH_UART3_CLK 31 85 #define AT91_SCMI_CLK_PERIPH_UART4_CLK 32 86 #define AT91_SCMI_CLK_PERIPH_TWI0_CLK 33 87 #define AT91_SCMI_CLK_PERIPH_TWI1_CLK 34 88 #define AT91_SCMI_CLK_PERIPH_SPI0_CLK 35 89 #define AT91_SCMI_CLK_PERIPH_SPI1_CLK 36 90 #define AT91_SCMI_CLK_PERIPH_TCB0_CLK 37 91 #define AT91_SCMI_CLK_PERIPH_TCB1_CLK 38 92 #define AT91_SCMI_CLK_PERIPH_PWM_CLK 39 93 #define AT91_SCMI_CLK_PERIPH_ADC_CLK 40 94 #define AT91_SCMI_CLK_PERIPH_UHPHS_CLK 41 95 #define AT91_SCMI_CLK_PERIPH_UDPHS_CLK 42 96 #define AT91_SCMI_CLK_PERIPH_SSC0_CLK 43 97 #define AT91_SCMI_CLK_PERIPH_SSC1_CLK 44 98 #define AT91_SCMI_CLK_PERIPH_TRNG_CLK 45 99 #define AT91_SCMI_CLK_PERIPH_PDMIC_CLK 46 100 #define AT91_SCMI_CLK_PERIPH_SECURAM_CLK 47 101 #define AT91_SCMI_CLK_PERIPH_I2S0_CLK 48 102 #define AT91_SCMI_CLK_PERIPH_I2S1_CLK 49 103 #define AT91_SCMI_CLK_PERIPH_CAN0_CLK 50 104 #define AT91_SCMI_CLK_PERIPH_CAN1_CLK 51 105 #define AT91_SCMI_CLK_PERIPH_PTC_CLK 52 106 #define AT91_SCMI_CLK_PERIPH_CLASSD_CLK 53 107 #define AT91_SCMI_CLK_PERIPH_DMA0_CLK 54 108 #define AT91_SCMI_CLK_PERIPH_DMA1_CLK 55 109 #define AT91_SCMI_CLK_PERIPH_AES_CLK 56 110 #define AT91_SCMI_CLK_PERIPH_AESB_CLK 57 111 #define AT91_SCMI_CLK_PERIPH_SHA_CLK 58 112 #define AT91_SCMI_CLK_PERIPH_MPDDR_CLK 59 113 #define AT91_SCMI_CLK_PERIPH_MATRIX0_CLK 60 114 #define AT91_SCMI_CLK_PERIPH_SDMMC0_HCLK 61 115 #define AT91_SCMI_CLK_PERIPH_SDMMC1_HCLK 62 116 #define AT91_SCMI_CLK_PERIPH_LCDC_CLK 63 117 #define AT91_SCMI_CLK_PERIPH_ISC_CLK 64 118 #define AT91_SCMI_CLK_PERIPH_QSPI0_CLK 65 119 #define AT91_SCMI_CLK_PERIPH_QSPI1_CLK 66 120 121 #define AT91_SCMI_CLK_GCK_SDMMC0_GCLK 67 122 #define AT91_SCMI_CLK_GCK_SDMMC1_GCLK 68 123 #define AT91_SCMI_CLK_GCK_TCB0_GCLK 69 124 #define AT91_SCMI_CLK_GCK_TCB1_GCLK 70 125 #define AT91_SCMI_CLK_GCK_PWM_GCLK 71 126 #define AT91_SCMI_CLK_GCK_ISC_GCLK 72 127 #define AT91_SCMI_CLK_GCK_PDMIC_GCLK 73 128 #define AT91_SCMI_CLK_GCK_I2S0_GCLK 74 129 #define AT91_SCMI_CLK_GCK_I2S1_GCLK 75 130 #define AT91_SCMI_CLK_GCK_CAN0_GCLK 76 131 #define AT91_SCMI_CLK_GCK_CAN1_GCLK 77 132 #define AT91_SCMI_CLK_GCK_CLASSD_GCLK 78 133 134 #define AT91_SCMI_CLK_PROG_PROG0 79 135 #define AT91_SCMI_CLK_PROG_PROG1 80 136 #define AT91_SCMI_CLK_PROG_PROG2 81 137 138 #define AT91_SCMI_CLK_SCKC_SLOWCK_32K 82 139 #define AT91_SCMI_CLK_CPU_OPP 101 140 141 #ifdef CFG_SAMA7G5 142 #define AT91_SCMI_CLK_CORE_CPUPLLCK 4 143 #define AT91_SCMI_CLK_CORE_SYSPLLCK 5 144 #define AT91_SCMI_CLK_CORE_DDRPLLCK 6 145 #define AT91_SCMI_CLK_CORE_IMGPLLCK 7 146 #define AT91_SCMI_CLK_CORE_ETHPLLCK 10 147 #define AT91_SCMI_CLK_SYSTEM_PCK3 11 148 #define AT91_SCMI_CLK_SYSTEM_PCK4 12 149 #define AT91_SCMI_CLK_SYSTEM_PCK5 13 150 #define AT91_SCMI_CLK_SYSTEM_PCK6 17 151 #define AT91_SCMI_CLK_SYSTEM_PCK7 20 152 #define AT91_SCMI_CLK_UTMI1 97 153 #define AT91_SCMI_CLK_UTMI2 98 154 #define AT91_SCMI_CLK_UTMI3 99 155 #define AT91_SCMI_CLK_PERIPH_DMA2_CLK 100 156 #define AT91_SCMI_CLK_PERIPH_FLX5_CLK 28 157 #define AT91_SCMI_CLK_PERIPH_FLX6_CLK 29 158 #define AT91_SCMI_CLK_PERIPH_FLX7_CLK 30 159 #define AT91_SCMI_CLK_PERIPH_FLX8_CLK 31 160 #define AT91_SCMI_CLK_PERIPH_FLX9_CLK 32 161 #define AT91_SCMI_CLK_PERIPH_FLX10_CLK 33 162 #define AT91_SCMI_CLK_PERIPH_FLX11_CLK 34 163 #define AT91_SCMI_CLK_PERIPH_UDPHSB_CLK 35 164 #define AT91_SCMI_CLK_PERIPH_PDMC1_CLK 36 165 #define AT91_SCMI_CLK_PERIPH_UDPHSA_CLK 42 166 #define AT91_SCMI_CLK_GCK_ADC_GCLK 40 167 #define AT91_SCMI_CLK_PERIPH_PDMC0_CLK 46 168 #define AT91_SCMI_CLK_PERIPH_CAN2_CLK 52 169 #define AT91_SCMI_CLK_PERIPH_CAN3_CLK 53 170 #define AT91_SCMI_CLK_PERIPH_CAN4_CLK 59 171 #define AT91_SCMI_CLK_PERIPH_CAN5_CLK 60 172 #define AT91_SCMI_CLK_PERIPH_SDMMC2_HCLK 63 173 #define AT91_SCMI_CLK_GCK_SDMMC2_GCLK 71 174 #define AT91_SCMI_CLK_GCK_MACB0_GCLK 72 175 #define AT91_SCMI_CLK_GCK_MACB0_TSU 73 176 #define AT91_SCMI_CLK_GCK_CAN2_GCLK 78 177 #define AT91_SCMI_CLK_GCK_CAN3_GCLK 79 178 #define AT91_SCMI_CLK_GCK_CAN4_GCLK 80 179 #define AT91_SCMI_CLK_GCK_CAN5_GCLK 81 180 #define AT91_SCMI_CLK_PERIPH_SPDIFRX_CLK 83 181 #define AT91_SCMI_CLK_PERIPH_SPDIFTX_CLK 84 182 #define AT91_SCMI_CLK_GCK_QSPI0_GCLK 85 183 #define AT91_SCMI_CLK_GCK_QSPI1_GCLK 86 184 #define AT91_SCMI_CLK_GCK_SPDIFRX_GCLK 87 185 #define AT91_SCMI_CLK_GCK_SPDIFTX_GCLK 88 186 #define AT91_SCMI_CLK_GCK_MACB1_GCLK 89 187 #define AT91_SCMI_CLK_PERIPH_MACB1_CLK 90 188 #define AT91_SCMI_CLK_GCK_MACB1_TSU 91 189 #define AT91_SCMI_CLK_PERIPH_CSI_CLK 92 190 #define AT91_SCMI_CLK_GCK_CSI_GCLK 93 191 #define AT91_SCMI_CLK_PERIPH_CSI2DC_CLK 94 192 #define AT91_SCMI_CLK_PERIPH_ASRC_CLK 95 193 #define AT91_SCMI_CLK_GCK_ASRC_GCLK 96 194 #define AT91_SCMI_CLK_GCK_PDMC0_GCLK 102 195 #define AT91_SCMI_CLK_GCK_PDMC1_GCLK 103 196 #endif 197 198 #endif 199