1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 */ 5 6 #include <compiler.h> 7 #include <console.h> 8 #include <drivers/serial.h> 9 #include <drivers/stm32_uart.h> 10 #include <io.h> 11 #include <keep.h> 12 #include <kernel/delay.h> 13 #include <kernel/dt.h> 14 #include <kernel/panic.h> 15 #include <stm32_util.h> 16 #include <util.h> 17 18 #define UART_REG_CR1 0x00 /* Control register 1 */ 19 #define UART_REG_CR2 0x04 /* Control register 2 */ 20 #define UART_REG_CR3 0x08 /* Control register 3 */ 21 #define UART_REG_BRR 0x0c /* Baud rate register */ 22 #define UART_REG_RQR 0x18 /* Request register */ 23 #define UART_REG_ISR 0x1c /* Interrupt & status reg. */ 24 #define UART_REG_ICR 0x20 /* Interrupt flag clear reg. */ 25 #define UART_REG_RDR 0x24 /* Receive data register */ 26 #define UART_REG_TDR 0x28 /* Transmit data register */ 27 #define UART_REG_PRESC 0x2c /* Prescaler register */ 28 29 #define PUTC_TIMEOUT_US 1000 30 #define FLUSH_TIMEOUT_US 16000 31 32 /* 33 * Uart Interrupt & status register bits 34 * 35 * Bit 5 RXNE: Read data register not empty/RXFIFO not empty 36 * Bit 6 TC: Transmission complete 37 * Bit 7 TXE/TXFNF: Transmit data register empty/TXFIFO not full 38 * Bit 27 TXFE: TXFIFO threshold reached 39 */ 40 #define USART_ISR_RXNE_RXFNE BIT(5) 41 #define USART_ISR_TC BIT(6) 42 #define USART_ISR_TXE_TXFNF BIT(7) 43 #define USART_ISR_TXFE BIT(27) 44 45 static vaddr_t loc_chip_to_base(struct serial_chip *chip) 46 { 47 struct stm32_uart_pdata *pd = NULL; 48 49 pd = container_of(chip, struct stm32_uart_pdata, chip); 50 51 return io_pa_or_va(&pd->base); 52 } 53 54 static void loc_flush(struct serial_chip *chip) 55 { 56 vaddr_t base = loc_chip_to_base(chip); 57 uint64_t timeout = timeout_init_us(FLUSH_TIMEOUT_US); 58 59 while (!(io_read32(base + UART_REG_ISR) & USART_ISR_TXFE)) 60 if (timeout_elapsed(timeout)) 61 return; 62 } 63 64 static void loc_putc(struct serial_chip *chip, int ch) 65 { 66 vaddr_t base = loc_chip_to_base(chip); 67 uint64_t timeout = timeout_init_us(PUTC_TIMEOUT_US); 68 69 while (!(io_read32(base + UART_REG_ISR) & USART_ISR_TXE_TXFNF)) 70 if (timeout_elapsed(timeout)) 71 return; 72 73 io_write32(base + UART_REG_TDR, ch); 74 } 75 76 static bool loc_have_rx_data(struct serial_chip *chip) 77 { 78 vaddr_t base = loc_chip_to_base(chip); 79 80 return io_read32(base + UART_REG_ISR) & USART_ISR_RXNE_RXFNE; 81 } 82 83 static int loc_getchar(struct serial_chip *chip) 84 { 85 vaddr_t base = loc_chip_to_base(chip); 86 87 while (!loc_have_rx_data(chip)) 88 ; 89 90 return io_read32(base + UART_REG_RDR) & 0xff; 91 } 92 93 static const struct serial_ops stm32_uart_serial_ops = { 94 .flush = loc_flush, 95 .putc = loc_putc, 96 .have_rx_data = loc_have_rx_data, 97 .getchar = loc_getchar, 98 99 }; 100 KEEP_PAGER(stm32_uart_serial_ops); 101 102 void stm32_uart_init(struct stm32_uart_pdata *pd, vaddr_t base) 103 { 104 pd->base.pa = base; 105 pd->chip.ops = &stm32_uart_serial_ops; 106 } 107 108 #ifdef CFG_DT 109 static void register_secure_uart(struct stm32_uart_pdata *pd) 110 { 111 size_t n = 0; 112 113 stm32mp_register_secure_periph_iomem(pd->base.pa); 114 for (n = 0; n < pd->pinctrl_count; n++) 115 stm32mp_register_secure_gpio(pd->pinctrl[n].bank, 116 pd->pinctrl[n].pin); 117 } 118 119 static void register_non_secure_uart(struct stm32_uart_pdata *pd) 120 { 121 size_t n = 0; 122 123 stm32mp_register_non_secure_periph_iomem(pd->base.pa); 124 for (n = 0; n < pd->pinctrl_count; n++) 125 stm32mp_register_non_secure_gpio(pd->pinctrl[n].bank, 126 pd->pinctrl[n].pin); 127 } 128 129 struct stm32_uart_pdata *stm32_uart_init_from_dt_node(void *fdt, int node) 130 { 131 struct stm32_uart_pdata *pd = NULL; 132 struct dt_node_info info = { }; 133 struct stm32_pinctrl *pinctrl_cfg = NULL; 134 int count = 0; 135 136 _fdt_fill_device_info(fdt, &info, node); 137 138 if (info.status == DT_STATUS_DISABLED) 139 return NULL; 140 141 assert(info.clock != DT_INFO_INVALID_CLOCK && 142 info.reg != DT_INFO_INVALID_REG); 143 144 pd = calloc(1, sizeof(*pd)); 145 if (!pd) 146 panic(); 147 148 pd->chip.ops = &stm32_uart_serial_ops; 149 pd->base.pa = info.reg; 150 pd->secure = (info.status == DT_STATUS_OK_SEC); 151 pd->clock = (unsigned int)info.clock; 152 153 assert(cpu_mmu_enabled()); 154 pd->base.va = (vaddr_t)phys_to_virt(pd->base.pa, 155 pd->secure ? MEM_AREA_IO_SEC : 156 MEM_AREA_IO_NSEC); 157 158 count = stm32_pinctrl_fdt_get_pinctrl(fdt, node, NULL, 0); 159 if (count < 0) 160 panic(); 161 162 if (count) { 163 pinctrl_cfg = calloc(count, sizeof(*pinctrl_cfg)); 164 if (!pinctrl_cfg) 165 panic(); 166 167 stm32_pinctrl_fdt_get_pinctrl(fdt, node, pinctrl_cfg, count); 168 stm32_pinctrl_load_active_cfg(pinctrl_cfg, count); 169 } 170 pd->pinctrl = pinctrl_cfg; 171 pd->pinctrl_count = count; 172 173 if (pd->secure) 174 register_secure_uart(pd); 175 else 176 register_non_secure_uart(pd); 177 178 return pd; 179 } 180 #endif /*CFG_DT*/ 181