1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2023, STMicroelectronics 4 * 5 * STM32 GPIO driver is used as pin controller for stm32mp SoCs. 6 * The driver API is defined in header file stm32_gpio.h. 7 */ 8 9 #include <assert.h> 10 #include <drivers/clk.h> 11 #include <drivers/clk_dt.h> 12 #include <drivers/stm32_gpio.h> 13 #include <io.h> 14 #include <kernel/dt.h> 15 #include <kernel/boot.h> 16 #include <kernel/panic.h> 17 #include <kernel/spinlock.h> 18 #include <libfdt.h> 19 #include <mm/core_memprot.h> 20 #include <stdbool.h> 21 #include <stm32_util.h> 22 #include <sys/queue.h> 23 #include <trace.h> 24 #include <util.h> 25 26 #define GPIO_PIN_MAX 15 27 28 #define GPIO_MODER_OFFSET 0x00 29 #define GPIO_OTYPER_OFFSET 0x04 30 #define GPIO_OSPEEDR_OFFSET 0x08 31 #define GPIO_PUPDR_OFFSET 0x0c 32 #define GPIO_IDR_OFFSET 0x10 33 #define GPIO_ODR_OFFSET 0x14 34 #define GPIO_BSRR_OFFSET 0x18 35 #define GPIO_AFRL_OFFSET 0x20 36 #define GPIO_AFRH_OFFSET 0x24 37 #define GPIO_SECR_OFFSET 0x30 38 39 #define GPIO_ALT_LOWER_LIMIT 0x8 40 41 #define GPIO_MODE_MASK GENMASK_32(1, 0) 42 #define GPIO_OSPEED_MASK GENMASK_32(1, 0) 43 #define GPIO_PUPD_PULL_MASK GENMASK_32(1, 0) 44 #define GPIO_ALTERNATE_MASK GENMASK_32(3, 0) 45 46 #define DT_GPIO_BANK_SHIFT 12 47 #define DT_GPIO_BANK_MASK GENMASK_32(16, 12) 48 #define DT_GPIO_PIN_SHIFT 8 49 #define DT_GPIO_PIN_MASK GENMASK_32(11, 8) 50 #define DT_GPIO_MODE_MASK GENMASK_32(7, 0) 51 52 #define DT_GPIO_BANK_NAME0 "GPIOA" 53 54 /** 55 * struct stm32_gpio_bank - GPIO bank instance 56 * 57 * @base: base address of the GPIO controller registers. 58 * @clock: clock identifier. 59 * @ngpios: number of GPIOs. 60 * @bank_id: Id of the bank. 61 * @lock: lock protecting the GPIO bank access. 62 * @sec_support: True if bank supports pin security protection, otherwise false 63 * @seccfgr: Secure configuration register value. 64 * @link: Link in bank list 65 */ 66 struct stm32_gpio_bank { 67 vaddr_t base; 68 struct clk *clock; 69 unsigned int ngpios; 70 unsigned int bank_id; 71 unsigned int lock; 72 STAILQ_ENTRY(stm32_gpio_bank) link; 73 }; 74 75 static unsigned int gpio_lock; 76 77 static STAILQ_HEAD(, stm32_gpio_bank) bank_list = 78 STAILQ_HEAD_INITIALIZER(bank_list); 79 80 /* Save to output @cfg the current GPIO (@bank/@pin) configuration */ 81 static void get_gpio_cfg(uint32_t bank, uint32_t pin, struct gpio_cfg *cfg) 82 { 83 vaddr_t base = stm32_get_gpio_bank_base(bank); 84 struct clk *clk = stm32_get_gpio_bank_clk(bank); 85 86 clk_enable(clk); 87 88 /* 89 * Save GPIO configuration bits spread over the few bank registers. 90 * 1bit fields are accessed at bit position being the pin index. 91 * 2bit fields are accessed at bit position being twice the pin index. 92 * 4bit fields are accessed at bit position being fourth the pin index 93 * but accessed from 2 32bit registers at incremental addresses. 94 */ 95 cfg->mode = (io_read32(base + GPIO_MODER_OFFSET) >> (pin << 1)) & 96 GPIO_MODE_MASK; 97 98 cfg->otype = (io_read32(base + GPIO_OTYPER_OFFSET) >> pin) & 1; 99 100 cfg->ospeed = (io_read32(base + GPIO_OSPEEDR_OFFSET) >> (pin << 1)) & 101 GPIO_OSPEED_MASK; 102 103 cfg->pupd = (io_read32(base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & 104 GPIO_PUPD_PULL_MASK; 105 106 cfg->od = (io_read32(base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; 107 108 if (pin < GPIO_ALT_LOWER_LIMIT) 109 cfg->af = (io_read32(base + GPIO_AFRL_OFFSET) >> (pin << 2)) & 110 GPIO_ALTERNATE_MASK; 111 else 112 cfg->af = (io_read32(base + GPIO_AFRH_OFFSET) >> 113 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) & 114 GPIO_ALTERNATE_MASK; 115 116 clk_disable(clk); 117 } 118 119 /* Apply GPIO (@bank/@pin) configuration described by @cfg */ 120 static void set_gpio_cfg(uint32_t bank, uint32_t pin, struct gpio_cfg *cfg) 121 { 122 vaddr_t base = stm32_get_gpio_bank_base(bank); 123 struct clk *clk = stm32_get_gpio_bank_clk(bank); 124 uint32_t exceptions = cpu_spin_lock_xsave(&gpio_lock); 125 126 clk_enable(clk); 127 128 /* Load GPIO MODE value, 2bit value shifted by twice the pin number */ 129 io_clrsetbits32(base + GPIO_MODER_OFFSET, 130 GPIO_MODE_MASK << (pin << 1), 131 cfg->mode << (pin << 1)); 132 133 /* Load GPIO Output TYPE value, 1bit shifted by pin number value */ 134 io_clrsetbits32(base + GPIO_OTYPER_OFFSET, BIT(pin), cfg->otype << pin); 135 136 /* Load GPIO Output Speed confguration, 2bit value */ 137 io_clrsetbits32(base + GPIO_OSPEEDR_OFFSET, 138 GPIO_OSPEED_MASK << (pin << 1), 139 cfg->ospeed << (pin << 1)); 140 141 /* Load GPIO pull configuration, 2bit value */ 142 io_clrsetbits32(base + GPIO_PUPDR_OFFSET, BIT(pin), 143 cfg->pupd << (pin << 1)); 144 145 /* Load pin mux Alternate Function configuration, 4bit value */ 146 if (pin < GPIO_ALT_LOWER_LIMIT) { 147 io_clrsetbits32(base + GPIO_AFRL_OFFSET, 148 GPIO_ALTERNATE_MASK << (pin << 2), 149 cfg->af << (pin << 2)); 150 } else { 151 size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2; 152 153 io_clrsetbits32(base + GPIO_AFRH_OFFSET, 154 GPIO_ALTERNATE_MASK << shift, 155 cfg->af << shift); 156 } 157 158 /* Load GPIO Output direction confuguration, 1bit */ 159 io_clrsetbits32(base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin); 160 161 clk_disable(clk); 162 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 163 } 164 165 void stm32_pinctrl_load_active_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 166 { 167 size_t n = 0; 168 169 for (n = 0; n < cnt; n++) 170 set_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 171 &pinctrl[n].active_cfg); 172 } 173 174 void stm32_pinctrl_load_standby_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 175 { 176 size_t n = 0; 177 178 for (n = 0; n < cnt; n++) 179 set_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 180 &pinctrl[n].standby_cfg); 181 } 182 183 void stm32_pinctrl_store_standby_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 184 { 185 size_t n = 0; 186 187 for (n = 0; n < cnt; n++) 188 get_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 189 &pinctrl[n].standby_cfg); 190 } 191 192 /* Panic if GPIO bank information from platform do not match DTB description */ 193 static void ckeck_gpio_bank(void *fdt, uint32_t bank, int pinctrl_node) 194 { 195 int pinctrl_subnode = 0; 196 197 fdt_for_each_subnode(pinctrl_subnode, fdt, pinctrl_node) { 198 TEE_Result res = TEE_ERROR_GENERIC; 199 const fdt32_t *cuint = NULL; 200 struct clk *clk = NULL; 201 202 if (fdt_getprop(fdt, pinctrl_subnode, 203 "gpio-controller", NULL) == NULL) 204 continue; 205 206 /* Check bank register offset matches platform assumptions */ 207 cuint = fdt_getprop(fdt, pinctrl_subnode, "reg", NULL); 208 if (fdt32_to_cpu(*cuint) != stm32_get_gpio_bank_offset(bank)) 209 continue; 210 211 /* Check bank clock matches platform assumptions */ 212 res = clk_dt_get_by_index(fdt, pinctrl_subnode, 0, &clk); 213 if (res || clk != stm32_get_gpio_bank_clk(bank)) 214 panic(); 215 216 /* Check controller is enabled */ 217 if (fdt_get_status(fdt, pinctrl_subnode) == DT_STATUS_DISABLED) 218 panic(); 219 220 return; 221 } 222 223 panic(); 224 } 225 226 /* Count pins described in the DT node and get related data if possible */ 227 static int get_pinctrl_from_fdt(void *fdt, int node, 228 struct stm32_pinctrl *pinctrl, size_t count) 229 { 230 const fdt32_t *cuint, *slewrate; 231 int len = 0; 232 int pinctrl_node = 0; 233 uint32_t i = 0; 234 uint32_t speed = GPIO_OSPEED_LOW; 235 uint32_t pull = GPIO_PUPD_NO_PULL; 236 size_t found = 0; 237 238 cuint = fdt_getprop(fdt, node, "pinmux", &len); 239 if (!cuint) 240 return -FDT_ERR_NOTFOUND; 241 242 pinctrl_node = fdt_parent_offset(fdt, fdt_parent_offset(fdt, node)); 243 if (pinctrl_node < 0) 244 return -FDT_ERR_NOTFOUND; 245 246 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); 247 if (slewrate) 248 speed = fdt32_to_cpu(*slewrate); 249 250 if (fdt_getprop(fdt, node, "bias-pull-up", NULL)) 251 pull = GPIO_PUPD_PULL_UP; 252 if (fdt_getprop(fdt, node, "bias-pull-down", NULL)) 253 pull = GPIO_PUPD_PULL_DOWN; 254 255 for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 256 uint32_t pincfg = 0; 257 uint32_t bank = 0; 258 uint32_t pin = 0; 259 uint32_t mode = 0; 260 uint32_t alternate = 0; 261 uint32_t odata = 0; 262 bool opendrain = false; 263 264 pincfg = fdt32_to_cpu(*cuint); 265 cuint++; 266 267 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; 268 269 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT; 270 271 mode = pincfg & DT_GPIO_MODE_MASK; 272 273 switch (mode) { 274 case 0: 275 mode = GPIO_MODE_INPUT; 276 break; 277 case 1: 278 case 2: 279 case 3: 280 case 4: 281 case 5: 282 case 6: 283 case 7: 284 case 8: 285 case 9: 286 case 10: 287 case 11: 288 case 12: 289 case 13: 290 case 14: 291 case 15: 292 case 16: 293 alternate = mode - 1U; 294 mode = GPIO_MODE_ALTERNATE; 295 break; 296 case 17: 297 mode = GPIO_MODE_ANALOG; 298 break; 299 default: 300 mode = GPIO_MODE_OUTPUT; 301 break; 302 } 303 304 if (fdt_getprop(fdt, node, "drive-open-drain", NULL)) 305 opendrain = true; 306 307 if (fdt_getprop(fdt, node, "output-high", NULL) && 308 mode == GPIO_MODE_INPUT) { 309 mode = GPIO_MODE_OUTPUT; 310 odata = 1; 311 } 312 313 if (fdt_getprop(fdt, node, "output-low", NULL) && 314 mode == GPIO_MODE_INPUT) { 315 mode = GPIO_MODE_OUTPUT; 316 odata = 0; 317 } 318 319 /* Check GPIO bank clock/base address against platform */ 320 ckeck_gpio_bank(fdt, bank, pinctrl_node); 321 322 if (found < count) { 323 struct stm32_pinctrl *ref = &pinctrl[found]; 324 325 ref->bank = (uint8_t)bank; 326 ref->pin = (uint8_t)pin; 327 ref->active_cfg.mode = mode; 328 ref->active_cfg.otype = opendrain ? 1 : 0; 329 ref->active_cfg.ospeed = speed; 330 ref->active_cfg.pupd = pull; 331 ref->active_cfg.od = odata; 332 ref->active_cfg.af = alternate; 333 /* Default to analog mode for standby state */ 334 ref->standby_cfg.mode = GPIO_MODE_ANALOG; 335 ref->standby_cfg.pupd = GPIO_PUPD_NO_PULL; 336 } 337 338 found++; 339 } 340 341 return (int)found; 342 } 343 344 /* Get bank ID from bank node property st,bank-name or panic on failure */ 345 static unsigned int dt_get_bank_id(const void *fdt, int node) 346 { 347 const int dt_name_len = strlen(DT_GPIO_BANK_NAME0); 348 const fdt32_t *cuint = NULL; 349 int len = 0; 350 351 /* Parse "st,bank-name" to get its id (eg: GPIOA -> 0) */ 352 cuint = fdt_getprop(fdt, node, "st,bank-name", &len); 353 if (!cuint || (len != dt_name_len + 1)) 354 panic("Missing/wrong st,bank-name property"); 355 356 if (strncmp((const char *)cuint, DT_GPIO_BANK_NAME0, dt_name_len - 1) || 357 strcmp((const char *)cuint, DT_GPIO_BANK_NAME0) < 0) 358 panic("Wrong st,bank-name property"); 359 360 return (unsigned int)strcmp((const char *)cuint, DT_GPIO_BANK_NAME0); 361 } 362 363 /* 364 * Return whether or not the GPIO bank related to a DT node is already 365 * registered in the GPIO bank link. 366 */ 367 static bool bank_is_registered(const void *fdt, int node) 368 { 369 unsigned int bank_id = dt_get_bank_id(fdt, node); 370 struct stm32_gpio_bank *bank = NULL; 371 372 STAILQ_FOREACH(bank, &bank_list, link) 373 if (bank->bank_id == bank_id) 374 return true; 375 376 return false; 377 } 378 379 /* Get GPIO bank information from the DT */ 380 static TEE_Result dt_stm32_gpio_bank(const void *fdt, int node, 381 const void *compat_data __unused, 382 int range_offset, 383 struct stm32_gpio_bank **out_bank) 384 { 385 TEE_Result res = TEE_ERROR_GENERIC; 386 struct stm32_gpio_bank *bank = NULL; 387 const fdt32_t *cuint = NULL; 388 struct io_pa_va pa_va = { }; 389 struct clk *clk = NULL; 390 size_t blen = 0; 391 paddr_t pa = 0; 392 int len = 0; 393 int i = 0; 394 395 assert(out_bank); 396 397 /* Probe deferrable devices first */ 398 res = clk_dt_get_by_index(fdt, node, 0, &clk); 399 if (res) 400 return res; 401 402 bank = calloc(1, sizeof(*bank)); 403 if (!bank) 404 return TEE_ERROR_OUT_OF_MEMORY; 405 406 /* 407 * Do not rely *only* on the "reg" property to get the address, 408 * but consider also the "ranges" translation property 409 */ 410 pa = fdt_reg_base_address(fdt, node); 411 if (pa == DT_INFO_INVALID_REG) 412 panic("missing reg property"); 413 414 pa_va.pa = pa + range_offset; 415 416 blen = fdt_reg_size(fdt, node); 417 if (blen == DT_INFO_INVALID_REG_SIZE) 418 panic("missing reg size property"); 419 420 DMSG("Bank name %s", fdt_get_name(fdt, node, NULL)); 421 bank->base = io_pa_or_va_secure(&pa_va, blen); 422 bank->bank_id = dt_get_bank_id(fdt, node); 423 bank->clock = clk; 424 425 /* Parse gpio-ranges with its 4 parameters */ 426 cuint = fdt_getprop(fdt, node, "gpio-ranges", &len); 427 len /= sizeof(*cuint); 428 if (len % 4) 429 panic("wrong gpio-ranges syntax"); 430 431 /* Get the last defined gpio line (offset + nb of pins) */ 432 for (i = 0; i < len / 4; i++) { 433 bank->ngpios = MAX(bank->ngpios, 434 (unsigned int)(fdt32_to_cpu(*(cuint + 1)) + 435 fdt32_to_cpu(*(cuint + 3)))); 436 cuint += 4; 437 } 438 439 *out_bank = bank; 440 return TEE_SUCCESS; 441 } 442 443 /* Parse a pinctrl node to register the GPIO banks it describes */ 444 static TEE_Result dt_stm32_gpio_pinctrl(const void *fdt, int node, 445 const void *compat_data) 446 { 447 TEE_Result res = TEE_SUCCESS; 448 const fdt32_t *cuint = NULL; 449 int range_offs = 0; 450 int b_node = 0; 451 int len = 0; 452 453 /* Read the ranges property (for regs memory translation) */ 454 cuint = fdt_getprop(fdt, node, "ranges", &len); 455 if (!cuint) 456 panic("missing ranges property"); 457 458 len /= sizeof(*cuint); 459 if (len == 3) 460 range_offs = fdt32_to_cpu(*(cuint + 1)) - fdt32_to_cpu(*cuint); 461 462 fdt_for_each_subnode(b_node, fdt, node) { 463 cuint = fdt_getprop(fdt, b_node, "gpio-controller", &len); 464 if (cuint) { 465 /* 466 * We found a property "gpio-controller" in the node: 467 * the node is a GPIO bank description, add it to the 468 * bank list. 469 */ 470 struct stm32_gpio_bank *bank = NULL; 471 472 if (fdt_get_status(fdt, b_node) == DT_STATUS_DISABLED || 473 bank_is_registered(fdt, b_node)) 474 continue; 475 476 res = dt_stm32_gpio_bank(fdt, b_node, compat_data, 477 range_offs, &bank); 478 if (res) 479 return res; 480 481 STAILQ_INSERT_TAIL(&bank_list, bank, link); 482 } else { 483 if (len != -FDT_ERR_NOTFOUND) 484 panic(); 485 } 486 } 487 488 return TEE_SUCCESS; 489 } 490 491 int stm32_pinctrl_fdt_get_pinctrl(void *fdt, int device_node, 492 struct stm32_pinctrl *pinctrl, size_t count) 493 { 494 const fdt32_t *cuint = NULL; 495 int lenp = 0; 496 int i = 0; 497 size_t found = 0; 498 499 cuint = fdt_getprop(fdt, device_node, "pinctrl-0", &lenp); 500 if (!cuint) 501 return -FDT_ERR_NOTFOUND; 502 503 for (i = 0; i < (lenp / 4); i++) { 504 int node = 0; 505 int subnode = 0; 506 507 node = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 508 if (node < 0) 509 return -FDT_ERR_NOTFOUND; 510 511 fdt_for_each_subnode(subnode, fdt, node) { 512 size_t n = 0; 513 int rc = 0; 514 515 if (count > found) 516 n = count - found; 517 else 518 n = 0; 519 520 rc = get_pinctrl_from_fdt(fdt, subnode, 521 &pinctrl[found], n); 522 if (rc < 0) 523 return rc; 524 525 found += (size_t)rc; 526 } 527 528 cuint++; 529 } 530 531 return (int)found; 532 } 533 534 int stm32_get_gpio_count(void *fdt, int pinctrl_node, unsigned int bank) 535 { 536 int node = 0; 537 const fdt32_t *cuint = NULL; 538 539 fdt_for_each_subnode(node, fdt, pinctrl_node) { 540 if (!fdt_getprop(fdt, node, "gpio-controller", NULL)) 541 continue; 542 543 cuint = fdt_getprop(fdt, node, "reg", NULL); 544 if (!cuint) 545 continue; 546 547 if (fdt32_to_cpu(*cuint) != stm32_get_gpio_bank_offset(bank)) 548 continue; 549 550 cuint = fdt_getprop(fdt, node, "ngpios", NULL); 551 if (!cuint) 552 panic(); 553 554 return (int)fdt32_to_cpu(*cuint); 555 } 556 557 return -1; 558 } 559 560 static __maybe_unused bool valid_gpio_config(unsigned int bank, 561 unsigned int pin, bool input) 562 { 563 vaddr_t base = stm32_get_gpio_bank_base(bank); 564 uint32_t mode = (io_read32(base + GPIO_MODER_OFFSET) >> (pin << 1)) & 565 GPIO_MODE_MASK; 566 567 if (pin > GPIO_PIN_MAX) 568 return false; 569 570 if (input) 571 return mode == GPIO_MODE_INPUT; 572 else 573 return mode == GPIO_MODE_OUTPUT; 574 } 575 576 int stm32_gpio_get_input_level(unsigned int bank, unsigned int pin) 577 { 578 vaddr_t base = stm32_get_gpio_bank_base(bank); 579 struct clk *clk = stm32_get_gpio_bank_clk(bank); 580 int rc = 0; 581 582 clk_enable(clk); 583 584 assert(valid_gpio_config(bank, pin, true)); 585 586 if (io_read32(base + GPIO_IDR_OFFSET) == BIT(pin)) 587 rc = 1; 588 589 clk_disable(clk); 590 591 return rc; 592 } 593 594 void stm32_gpio_set_output_level(unsigned int bank, unsigned int pin, int level) 595 { 596 vaddr_t base = stm32_get_gpio_bank_base(bank); 597 struct clk *clk = stm32_get_gpio_bank_clk(bank); 598 599 clk_enable(clk); 600 601 assert(valid_gpio_config(bank, pin, false)); 602 603 if (level) 604 io_write32(base + GPIO_BSRR_OFFSET, BIT(pin)); 605 else 606 io_write32(base + GPIO_BSRR_OFFSET, BIT(pin + 16)); 607 608 clk_disable(clk); 609 } 610 611 void stm32_gpio_set_secure_cfg(unsigned int bank, unsigned int pin, bool secure) 612 { 613 vaddr_t base = stm32_get_gpio_bank_base(bank); 614 struct clk *clk = stm32_get_gpio_bank_clk(bank); 615 uint32_t exceptions = cpu_spin_lock_xsave(&gpio_lock); 616 617 clk_enable(clk); 618 619 if (secure) 620 io_setbits32(base + GPIO_SECR_OFFSET, BIT(pin)); 621 else 622 io_clrbits32(base + GPIO_SECR_OFFSET, BIT(pin)); 623 624 clk_disable(clk); 625 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 626 } 627 628 static TEE_Result stm32_pinctrl_probe(const void *fdt, int node, 629 const void *compat_data) 630 { 631 /* Register GPIO banks described in this pin control node */ 632 return dt_stm32_gpio_pinctrl(fdt, node, compat_data); 633 } 634 635 static const struct dt_device_match stm32_pinctrl_match_table[] = { 636 { .compatible = "st,stm32mp135-pinctrl" }, 637 { .compatible = "st,stm32mp157-pinctrl" }, 638 { .compatible = "st,stm32mp157-z-pinctrl" }, 639 { } 640 }; 641 642 DEFINE_DT_DRIVER(stm32_pinctrl_dt_driver) = { 643 .name = "stm32_gpio-pinctrl", 644 .type = DT_DRIVER_PINCTRL, 645 .match_table = stm32_pinctrl_match_table, 646 .probe = stm32_pinctrl_probe, 647 }; 648