1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2023, STMicroelectronics 4 * 5 * STM32 GPIO driver is used as pin controller for stm32mp SoCs. 6 * The driver API is defined in header file stm32_gpio.h. 7 */ 8 9 #include <assert.h> 10 #include <drivers/clk.h> 11 #include <drivers/clk_dt.h> 12 #include <drivers/stm32_gpio.h> 13 #include <io.h> 14 #include <kernel/dt.h> 15 #include <kernel/boot.h> 16 #include <kernel/panic.h> 17 #include <kernel/spinlock.h> 18 #include <libfdt.h> 19 #include <mm/core_memprot.h> 20 #include <stdbool.h> 21 #include <stm32_util.h> 22 #include <sys/queue.h> 23 #include <trace.h> 24 #include <util.h> 25 26 #define GPIO_PIN_MAX 15 27 28 #define GPIO_MODER_OFFSET 0x00 29 #define GPIO_OTYPER_OFFSET 0x04 30 #define GPIO_OSPEEDR_OFFSET 0x08 31 #define GPIO_PUPDR_OFFSET 0x0c 32 #define GPIO_IDR_OFFSET 0x10 33 #define GPIO_ODR_OFFSET 0x14 34 #define GPIO_BSRR_OFFSET 0x18 35 #define GPIO_AFRL_OFFSET 0x20 36 #define GPIO_AFRH_OFFSET 0x24 37 #define GPIO_SECR_OFFSET 0x30 38 39 #define GPIO_ALT_LOWER_LIMIT 0x8 40 41 #define GPIO_MODE_MASK GENMASK_32(1, 0) 42 #define GPIO_OSPEED_MASK GENMASK_32(1, 0) 43 #define GPIO_PUPD_PULL_MASK GENMASK_32(1, 0) 44 #define GPIO_ALTERNATE_MASK GENMASK_32(3, 0) 45 46 #define DT_GPIO_BANK_SHIFT 12 47 #define DT_GPIO_BANK_MASK GENMASK_32(16, 12) 48 #define DT_GPIO_PIN_SHIFT 8 49 #define DT_GPIO_PIN_MASK GENMASK_32(11, 8) 50 #define DT_GPIO_MODE_MASK GENMASK_32(7, 0) 51 52 #define DT_GPIO_BANK_NAME0 "GPIOA" 53 54 /** 55 * struct stm32_gpio_bank - GPIO bank instance 56 * 57 * @base: base address of the GPIO controller registers. 58 * @clock: clock identifier. 59 * @ngpios: number of GPIOs. 60 * @bank_id: Id of the bank. 61 * @lock: lock protecting the GPIO bank access. 62 * @sec_support: True if bank supports pin security protection, otherwise false 63 * @seccfgr: Secure configuration register value. 64 * @link: Link in bank list 65 */ 66 struct stm32_gpio_bank { 67 vaddr_t base; 68 struct clk *clock; 69 unsigned int ngpios; 70 unsigned int bank_id; 71 unsigned int lock; 72 STAILQ_ENTRY(stm32_gpio_bank) link; 73 }; 74 75 static unsigned int gpio_lock; 76 77 static STAILQ_HEAD(, stm32_gpio_bank) bank_list = 78 STAILQ_HEAD_INITIALIZER(bank_list); 79 80 static struct stm32_gpio_bank *stm32_gpio_get_bank(unsigned int bank_id) 81 { 82 struct stm32_gpio_bank *bank = NULL; 83 84 STAILQ_FOREACH(bank, &bank_list, link) 85 if (bank_id == bank->bank_id) 86 return bank; 87 88 panic(); 89 } 90 91 /* Save to output @cfg the current GPIO (@bank_id/@pin) configuration */ 92 static void get_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 93 { 94 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 95 96 if (clk_enable(bank->clock)) 97 panic(); 98 99 /* 100 * Save GPIO configuration bits spread over the few bank registers. 101 * 1bit fields are accessed at bit position being the pin index. 102 * 2bit fields are accessed at bit position being twice the pin index. 103 * 4bit fields are accessed at bit position being fourth the pin index 104 * but accessed from 2 32bit registers at incremental addresses. 105 */ 106 cfg->mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (pin << 1)) & 107 GPIO_MODE_MASK; 108 109 cfg->otype = (io_read32(bank->base + GPIO_OTYPER_OFFSET) >> pin) & 1; 110 111 cfg->ospeed = (io_read32(bank->base + GPIO_OSPEEDR_OFFSET) >> 112 (pin << 1)) & GPIO_OSPEED_MASK; 113 114 cfg->pupd = (io_read32(bank->base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & 115 GPIO_PUPD_PULL_MASK; 116 117 cfg->od = (io_read32(bank->base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; 118 119 if (pin < GPIO_ALT_LOWER_LIMIT) 120 cfg->af = (io_read32(bank->base + GPIO_AFRL_OFFSET) >> 121 (pin << 2)) & GPIO_ALTERNATE_MASK; 122 else 123 cfg->af = (io_read32(bank->base + GPIO_AFRH_OFFSET) >> 124 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) & 125 GPIO_ALTERNATE_MASK; 126 127 clk_disable(bank->clock); 128 } 129 130 /* Apply GPIO (@bank/@pin) configuration described by @cfg */ 131 static void set_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 132 { 133 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 134 uint32_t exceptions = 0; 135 136 if (clk_enable(bank->clock)) 137 panic(); 138 exceptions = cpu_spin_lock_xsave(&gpio_lock); 139 140 /* Load GPIO MODE value, 2bit value shifted by twice the pin number */ 141 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 142 SHIFT_U32(GPIO_MODE_MASK, pin << 1), 143 SHIFT_U32(cfg->mode, pin << 1)); 144 145 /* Load GPIO Output TYPE value, 1bit shifted by pin number value */ 146 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, BIT(pin), 147 SHIFT_U32(cfg->otype, pin)); 148 149 /* Load GPIO Output Speed confguration, 2bit value */ 150 io_clrsetbits32(bank->base + GPIO_OSPEEDR_OFFSET, 151 SHIFT_U32(GPIO_OSPEED_MASK, pin << 1), 152 SHIFT_U32(cfg->ospeed, pin << 1)); 153 154 /* Load GPIO pull configuration, 2bit value */ 155 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, BIT(pin), 156 SHIFT_U32(cfg->pupd, pin << 1)); 157 158 /* Load pin mux Alternate Function configuration, 4bit value */ 159 if (pin < GPIO_ALT_LOWER_LIMIT) { 160 io_clrsetbits32(bank->base + GPIO_AFRL_OFFSET, 161 SHIFT_U32(GPIO_ALTERNATE_MASK, pin << 2), 162 SHIFT_U32(cfg->af, pin << 2)); 163 } else { 164 size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2; 165 166 io_clrsetbits32(bank->base + GPIO_AFRH_OFFSET, 167 SHIFT_U32(GPIO_ALTERNATE_MASK, shift), 168 SHIFT_U32(cfg->af, shift)); 169 } 170 171 /* Load GPIO Output direction confuguration, 1bit */ 172 io_clrsetbits32(bank->base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin); 173 174 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 175 clk_disable(bank->clock); 176 } 177 178 void stm32_pinctrl_load_active_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 179 { 180 size_t n = 0; 181 182 for (n = 0; n < cnt; n++) 183 set_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 184 &pinctrl[n].active_cfg); 185 } 186 187 void stm32_pinctrl_load_standby_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 188 { 189 size_t n = 0; 190 191 for (n = 0; n < cnt; n++) 192 set_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 193 &pinctrl[n].standby_cfg); 194 } 195 196 void stm32_pinctrl_store_standby_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 197 { 198 size_t n = 0; 199 200 for (n = 0; n < cnt; n++) 201 get_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 202 &pinctrl[n].standby_cfg); 203 } 204 205 /* Panic if GPIO bank information from platform do not match DTB description */ 206 static void ckeck_gpio_bank(void *fdt, uint32_t bank, int pinctrl_node) 207 { 208 int pinctrl_subnode = 0; 209 210 fdt_for_each_subnode(pinctrl_subnode, fdt, pinctrl_node) { 211 const fdt32_t *cuint = NULL; 212 213 if (fdt_getprop(fdt, pinctrl_subnode, 214 "gpio-controller", NULL) == NULL) 215 continue; 216 217 /* Check bank register offset matches platform assumptions */ 218 cuint = fdt_getprop(fdt, pinctrl_subnode, "reg", NULL); 219 if (fdt32_to_cpu(*cuint) != stm32_get_gpio_bank_offset(bank)) 220 continue; 221 222 /* Check controller is enabled */ 223 if (fdt_get_status(fdt, pinctrl_subnode) == DT_STATUS_DISABLED) 224 panic(); 225 226 return; 227 } 228 229 panic(); 230 } 231 232 /* Count pins described in the DT node and get related data if possible */ 233 static int get_pinctrl_from_fdt(void *fdt, int node, 234 struct stm32_pinctrl *pinctrl, size_t count) 235 { 236 const fdt32_t *cuint, *slewrate; 237 int len = 0; 238 int pinctrl_node = 0; 239 uint32_t i = 0; 240 uint32_t speed = GPIO_OSPEED_LOW; 241 uint32_t pull = GPIO_PUPD_NO_PULL; 242 size_t found = 0; 243 244 cuint = fdt_getprop(fdt, node, "pinmux", &len); 245 if (!cuint) 246 return -FDT_ERR_NOTFOUND; 247 248 pinctrl_node = fdt_parent_offset(fdt, fdt_parent_offset(fdt, node)); 249 if (pinctrl_node < 0) 250 return -FDT_ERR_NOTFOUND; 251 252 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); 253 if (slewrate) 254 speed = fdt32_to_cpu(*slewrate); 255 256 if (fdt_getprop(fdt, node, "bias-pull-up", NULL)) 257 pull = GPIO_PUPD_PULL_UP; 258 if (fdt_getprop(fdt, node, "bias-pull-down", NULL)) 259 pull = GPIO_PUPD_PULL_DOWN; 260 261 for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 262 uint32_t pincfg = 0; 263 uint32_t bank = 0; 264 uint32_t pin = 0; 265 uint32_t mode = 0; 266 uint32_t alternate = 0; 267 uint32_t odata = 0; 268 bool opendrain = false; 269 270 pincfg = fdt32_to_cpu(*cuint); 271 cuint++; 272 273 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; 274 275 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT; 276 277 mode = pincfg & DT_GPIO_MODE_MASK; 278 279 switch (mode) { 280 case 0: 281 mode = GPIO_MODE_INPUT; 282 break; 283 case 1: 284 case 2: 285 case 3: 286 case 4: 287 case 5: 288 case 6: 289 case 7: 290 case 8: 291 case 9: 292 case 10: 293 case 11: 294 case 12: 295 case 13: 296 case 14: 297 case 15: 298 case 16: 299 alternate = mode - 1U; 300 mode = GPIO_MODE_ALTERNATE; 301 break; 302 case 17: 303 mode = GPIO_MODE_ANALOG; 304 break; 305 default: 306 mode = GPIO_MODE_OUTPUT; 307 break; 308 } 309 310 if (fdt_getprop(fdt, node, "drive-open-drain", NULL)) 311 opendrain = true; 312 313 if (fdt_getprop(fdt, node, "output-high", NULL) && 314 mode == GPIO_MODE_INPUT) { 315 mode = GPIO_MODE_OUTPUT; 316 odata = 1; 317 } 318 319 if (fdt_getprop(fdt, node, "output-low", NULL) && 320 mode == GPIO_MODE_INPUT) { 321 mode = GPIO_MODE_OUTPUT; 322 odata = 0; 323 } 324 325 /* Check GPIO bank clock/base address against platform */ 326 ckeck_gpio_bank(fdt, bank, pinctrl_node); 327 328 if (found < count) { 329 struct stm32_pinctrl *ref = &pinctrl[found]; 330 331 ref->bank = (uint8_t)bank; 332 ref->pin = (uint8_t)pin; 333 ref->active_cfg.mode = mode; 334 ref->active_cfg.otype = opendrain ? 1 : 0; 335 ref->active_cfg.ospeed = speed; 336 ref->active_cfg.pupd = pull; 337 ref->active_cfg.od = odata; 338 ref->active_cfg.af = alternate; 339 /* Default to analog mode for standby state */ 340 ref->standby_cfg.mode = GPIO_MODE_ANALOG; 341 ref->standby_cfg.pupd = GPIO_PUPD_NO_PULL; 342 } 343 344 found++; 345 } 346 347 return (int)found; 348 } 349 350 /* Get bank ID from bank node property st,bank-name or panic on failure */ 351 static unsigned int dt_get_bank_id(const void *fdt, int node) 352 { 353 const int dt_name_len = strlen(DT_GPIO_BANK_NAME0); 354 const fdt32_t *cuint = NULL; 355 int len = 0; 356 357 /* Parse "st,bank-name" to get its id (eg: GPIOA -> 0) */ 358 cuint = fdt_getprop(fdt, node, "st,bank-name", &len); 359 if (!cuint || (len != dt_name_len + 1)) 360 panic("Missing/wrong st,bank-name property"); 361 362 if (strncmp((const char *)cuint, DT_GPIO_BANK_NAME0, dt_name_len - 1) || 363 strcmp((const char *)cuint, DT_GPIO_BANK_NAME0) < 0) 364 panic("Wrong st,bank-name property"); 365 366 return (unsigned int)strcmp((const char *)cuint, DT_GPIO_BANK_NAME0); 367 } 368 369 /* 370 * Return whether or not the GPIO bank related to a DT node is already 371 * registered in the GPIO bank link. 372 */ 373 static bool bank_is_registered(const void *fdt, int node) 374 { 375 unsigned int bank_id = dt_get_bank_id(fdt, node); 376 struct stm32_gpio_bank *bank = NULL; 377 378 STAILQ_FOREACH(bank, &bank_list, link) 379 if (bank->bank_id == bank_id) 380 return true; 381 382 return false; 383 } 384 385 /* Get GPIO bank information from the DT */ 386 static TEE_Result dt_stm32_gpio_bank(const void *fdt, int node, 387 const void *compat_data __unused, 388 int range_offset, 389 struct stm32_gpio_bank **out_bank) 390 { 391 TEE_Result res = TEE_ERROR_GENERIC; 392 struct stm32_gpio_bank *bank = NULL; 393 const fdt32_t *cuint = NULL; 394 struct io_pa_va pa_va = { }; 395 struct clk *clk = NULL; 396 size_t blen = 0; 397 paddr_t pa = 0; 398 int len = 0; 399 int i = 0; 400 401 assert(out_bank); 402 403 /* Probe deferrable devices first */ 404 res = clk_dt_get_by_index(fdt, node, 0, &clk); 405 if (res) 406 return res; 407 408 bank = calloc(1, sizeof(*bank)); 409 if (!bank) 410 return TEE_ERROR_OUT_OF_MEMORY; 411 412 /* 413 * Do not rely *only* on the "reg" property to get the address, 414 * but consider also the "ranges" translation property 415 */ 416 pa = fdt_reg_base_address(fdt, node); 417 if (pa == DT_INFO_INVALID_REG) 418 panic("missing reg property"); 419 420 pa_va.pa = pa + range_offset; 421 422 blen = fdt_reg_size(fdt, node); 423 if (blen == DT_INFO_INVALID_REG_SIZE) 424 panic("missing reg size property"); 425 426 DMSG("Bank name %s", fdt_get_name(fdt, node, NULL)); 427 bank->base = io_pa_or_va_secure(&pa_va, blen); 428 bank->bank_id = dt_get_bank_id(fdt, node); 429 bank->clock = clk; 430 431 /* Parse gpio-ranges with its 4 parameters */ 432 cuint = fdt_getprop(fdt, node, "gpio-ranges", &len); 433 len /= sizeof(*cuint); 434 if (len % 4) 435 panic("wrong gpio-ranges syntax"); 436 437 /* Get the last defined gpio line (offset + nb of pins) */ 438 for (i = 0; i < len / 4; i++) { 439 bank->ngpios = MAX(bank->ngpios, 440 (unsigned int)(fdt32_to_cpu(*(cuint + 1)) + 441 fdt32_to_cpu(*(cuint + 3)))); 442 cuint += 4; 443 } 444 445 *out_bank = bank; 446 return TEE_SUCCESS; 447 } 448 449 /* Parse a pinctrl node to register the GPIO banks it describes */ 450 static TEE_Result dt_stm32_gpio_pinctrl(const void *fdt, int node, 451 const void *compat_data) 452 { 453 TEE_Result res = TEE_SUCCESS; 454 const fdt32_t *cuint = NULL; 455 int range_offs = 0; 456 int b_node = 0; 457 int len = 0; 458 459 /* Read the ranges property (for regs memory translation) */ 460 cuint = fdt_getprop(fdt, node, "ranges", &len); 461 if (!cuint) 462 panic("missing ranges property"); 463 464 len /= sizeof(*cuint); 465 if (len == 3) 466 range_offs = fdt32_to_cpu(*(cuint + 1)) - fdt32_to_cpu(*cuint); 467 468 fdt_for_each_subnode(b_node, fdt, node) { 469 cuint = fdt_getprop(fdt, b_node, "gpio-controller", &len); 470 if (cuint) { 471 /* 472 * We found a property "gpio-controller" in the node: 473 * the node is a GPIO bank description, add it to the 474 * bank list. 475 */ 476 struct stm32_gpio_bank *bank = NULL; 477 478 if (fdt_get_status(fdt, b_node) == DT_STATUS_DISABLED || 479 bank_is_registered(fdt, b_node)) 480 continue; 481 482 res = dt_stm32_gpio_bank(fdt, b_node, compat_data, 483 range_offs, &bank); 484 if (res) 485 return res; 486 487 STAILQ_INSERT_TAIL(&bank_list, bank, link); 488 } else { 489 if (len != -FDT_ERR_NOTFOUND) 490 panic(); 491 } 492 } 493 494 return TEE_SUCCESS; 495 } 496 497 int stm32_pinctrl_fdt_get_pinctrl(void *fdt, int device_node, 498 struct stm32_pinctrl *pinctrl, size_t count) 499 { 500 const fdt32_t *cuint = NULL; 501 int lenp = 0; 502 int i = 0; 503 size_t found = 0; 504 505 cuint = fdt_getprop(fdt, device_node, "pinctrl-0", &lenp); 506 if (!cuint) 507 return -FDT_ERR_NOTFOUND; 508 509 for (i = 0; i < (lenp / 4); i++) { 510 int node = 0; 511 int subnode = 0; 512 513 node = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 514 if (node < 0) 515 return -FDT_ERR_NOTFOUND; 516 517 fdt_for_each_subnode(subnode, fdt, node) { 518 size_t n = 0; 519 int rc = 0; 520 521 if (count > found) 522 n = count - found; 523 else 524 n = 0; 525 526 rc = get_pinctrl_from_fdt(fdt, subnode, 527 &pinctrl[found], n); 528 if (rc < 0) 529 return rc; 530 531 found += (size_t)rc; 532 } 533 534 cuint++; 535 } 536 537 return (int)found; 538 } 539 540 int stm32_get_gpio_count(void *fdt, int pinctrl_node, unsigned int bank) 541 { 542 int node = 0; 543 const fdt32_t *cuint = NULL; 544 545 fdt_for_each_subnode(node, fdt, pinctrl_node) { 546 if (!fdt_getprop(fdt, node, "gpio-controller", NULL)) 547 continue; 548 549 cuint = fdt_getprop(fdt, node, "reg", NULL); 550 if (!cuint) 551 continue; 552 553 if (fdt32_to_cpu(*cuint) != stm32_get_gpio_bank_offset(bank)) 554 continue; 555 556 cuint = fdt_getprop(fdt, node, "ngpios", NULL); 557 if (!cuint) 558 panic(); 559 560 return (int)fdt32_to_cpu(*cuint); 561 } 562 563 return -1; 564 } 565 566 static __maybe_unused bool valid_gpio_config(unsigned int bank_id, 567 unsigned int pin, bool input) 568 { 569 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 570 uint32_t mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> 571 (pin << 1)) & GPIO_MODE_MASK; 572 573 if (pin > GPIO_PIN_MAX) 574 return false; 575 576 if (input) 577 return mode == GPIO_MODE_INPUT; 578 else 579 return mode == GPIO_MODE_OUTPUT; 580 } 581 582 int stm32_gpio_get_input_level(unsigned int bank_id, unsigned int pin) 583 { 584 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 585 int rc = 0; 586 587 if (clk_enable(bank->clock)) 588 panic(); 589 590 assert(valid_gpio_config(bank_id, pin, true)); 591 592 if (io_read32(bank->base + GPIO_IDR_OFFSET) == BIT(pin)) 593 rc = 1; 594 595 clk_disable(bank->clock); 596 597 return rc; 598 } 599 600 void stm32_gpio_set_output_level(unsigned int bank_id, unsigned int pin, 601 int level) 602 { 603 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 604 605 if (clk_enable(bank->clock)) 606 panic(); 607 608 assert(valid_gpio_config(bank_id, pin, false)); 609 610 if (level) 611 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(pin)); 612 else 613 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(pin + 16)); 614 615 clk_disable(bank->clock); 616 } 617 618 void stm32_gpio_set_secure_cfg(unsigned int bank_id, unsigned int pin, 619 bool secure) 620 { 621 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 622 uint32_t exceptions = 0; 623 624 if (clk_enable(bank->clock)) 625 panic(); 626 exceptions = cpu_spin_lock_xsave(&gpio_lock); 627 628 if (secure) 629 io_setbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 630 else 631 io_clrbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 632 633 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 634 clk_disable(bank->clock); 635 } 636 637 static TEE_Result stm32_pinctrl_probe(const void *fdt, int node, 638 const void *compat_data) 639 { 640 /* Register GPIO banks described in this pin control node */ 641 return dt_stm32_gpio_pinctrl(fdt, node, compat_data); 642 } 643 644 static const struct dt_device_match stm32_pinctrl_match_table[] = { 645 { .compatible = "st,stm32mp135-pinctrl" }, 646 { .compatible = "st,stm32mp157-pinctrl" }, 647 { .compatible = "st,stm32mp157-z-pinctrl" }, 648 { } 649 }; 650 651 DEFINE_DT_DRIVER(stm32_pinctrl_dt_driver) = { 652 .name = "stm32_gpio-pinctrl", 653 .type = DT_DRIVER_PINCTRL, 654 .match_table = stm32_pinctrl_match_table, 655 .probe = stm32_pinctrl_probe, 656 }; 657