1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2024, STMicroelectronics 4 * 5 * STM32 GPIO driver is used as pin controller for stm32mp SoCs. 6 */ 7 8 #include <assert.h> 9 #include <compiler.h> 10 #include <drivers/clk.h> 11 #include <drivers/clk_dt.h> 12 #include <drivers/gpio.h> 13 #include <drivers/pinctrl.h> 14 #include <drivers/stm32_gpio.h> 15 #include <drivers/stm32_rif.h> 16 #include <dt-bindings/gpio/gpio.h> 17 #include <io.h> 18 #include <kernel/dt.h> 19 #include <kernel/boot.h> 20 #include <kernel/panic.h> 21 #include <kernel/pm.h> 22 #include <kernel/spinlock.h> 23 #include <libfdt.h> 24 #include <mm/core_memprot.h> 25 #include <stdbool.h> 26 #include <stdint.h> 27 #include <stm32_util.h> 28 #include <sys/queue.h> 29 #include <trace.h> 30 #include <util.h> 31 32 #ifndef CFG_DRIVERS_GPIO 33 #error stm32_gpio driver expects CFG_DRIVERS_GPIO 34 #endif 35 36 #define GPIO_PIN_MAX 15 37 38 #define GPIO_MODER_OFFSET U(0x00) 39 #define GPIO_OTYPER_OFFSET U(0x04) 40 #define GPIO_OSPEEDR_OFFSET U(0x08) 41 #define GPIO_PUPDR_OFFSET U(0x0c) 42 #define GPIO_IDR_OFFSET U(0x10) 43 #define GPIO_ODR_OFFSET U(0x14) 44 #define GPIO_BSRR_OFFSET U(0x18) 45 #define GPIO_AFRL_OFFSET U(0x20) 46 #define GPIO_AFRH_OFFSET U(0x24) 47 #define GPIO_SECR_OFFSET U(0x30) 48 #define GPIO_PRIVCFGR_OFFSET U(0x34) 49 #define GPIO_RCFGLOCKR_OFFSET U(0x38) 50 #define GPIO_CIDCFGR(x) (U(0x50) + U(0x8) * (x)) 51 #define GPIO_SEMCR(x) (U(0x54) + U(0x8) * (x)) 52 53 #define GPIO_ALT_LOWER_LIMIT U(0x8) 54 55 /* 56 * CIDCFGR register bitfields 57 */ 58 #define GPIO_CIDCFGR_SEMWL_MASK GENMASK_32(23, 16) 59 #define GPIO_CIDCFGR_SCID_MASK GENMASK_32(6, 4) 60 #define GPIO_CIDCFGR_CONF_MASK (_CIDCFGR_CFEN | _CIDCFGR_SEMEN | \ 61 GPIO_CIDCFGR_SCID_MASK | \ 62 GPIO_CIDCFGR_SEMWL_MASK) 63 64 /* 65 * PRIVCFGR register bitfields 66 */ 67 #define GPIO_PRIVCFGR_MASK GENMASK_32(15, 0) 68 69 /* 70 * SECCFGR register bitfields 71 */ 72 #define GPIO_SECCFGR_MASK GENMASK_32(15, 0) 73 74 /* 75 * RCFGLOCKR register bitfields 76 */ 77 #define GPIO_RCFGLOCKR_MASK GENMASK_32(15, 0) 78 79 /* 80 * SEMCR register bitfields 81 */ 82 #define GPIO_SEMCR_SCID_M GENMASK_32(6, 4) 83 84 #define GPIO_MODE_MASK GENMASK_32(1, 0) 85 #define GPIO_OSPEED_MASK GENMASK_32(1, 0) 86 #define GPIO_PUPD_PULL_MASK GENMASK_32(1, 0) 87 #define GPIO_ALTERNATE_MASK GENMASK_32(3, 0) 88 89 #define DT_GPIO_BANK_SHIFT U(12) 90 #define DT_GPIO_BANK_MASK GENMASK_32(16, 12) 91 #define DT_GPIO_PIN_SHIFT U(8) 92 #define DT_GPIO_PIN_MASK GENMASK_32(11, 8) 93 #define DT_GPIO_MODE_MASK GENMASK_32(7, 0) 94 95 #define DT_GPIO_BANK_NAME0 "GPIOA" 96 97 #define GPIO_MODE_INPUT U(0x0) 98 #define GPIO_MODE_OUTPUT U(0x1) 99 #define GPIO_MODE_ALTERNATE U(0x2) 100 #define GPIO_MODE_ANALOG U(0x3) 101 102 #define GPIO_OTYPE_PUSH_PULL U(0x0) 103 #define GPIO_OTYPE_OPEN_DRAIN U(0x1) 104 105 #define GPIO_OSPEED_LOW U(0x0) 106 #define GPIO_OSPEED_MEDIUM U(0x1) 107 #define GPIO_OSPEED_HIGH U(0x2) 108 #define GPIO_OSPEED_VERY_HIGH U(0x3) 109 110 #define GPIO_PUPD_NO_PULL U(0x0) 111 #define GPIO_PUPD_PULL_UP U(0x1) 112 #define GPIO_PUPD_PULL_DOWN U(0x2) 113 114 #define GPIO_OD_LEVEL_LOW U(0x0) 115 #define GPIO_OD_LEVEL_HIGH U(0x1) 116 117 #define GPIO_MAX_CID_SUPPORTED U(3) 118 119 /* 120 * GPIO configuration description structured as single 16bit word 121 * for efficient save/restore when GPIO pin suspends or resumes. 122 * 123 * @mode: One of GPIO_MODE_* 124 * @otype: One of GPIO_OTYPE_* 125 * @ospeed: One of GPIO_OSPEED_* 126 * @pupd: One of GPIO_PUPD_* 127 * @od: One of GPIO_OD_* 128 * @af: Alternate function numerical ID between 0 and 15 129 */ 130 struct gpio_cfg { 131 uint16_t mode: 2; 132 uint16_t otype: 1; 133 uint16_t ospeed: 2; 134 uint16_t pupd: 2; 135 uint16_t od: 1; 136 uint16_t af: 4; 137 }; 138 139 /* 140 * Description of a pin and its muxing 141 * 142 * @bank: GPIO bank identifier as assigned by the platform 143 * @pin: Pin number in the GPIO bank 144 * @cfg: Pin configuration 145 */ 146 struct stm32_pinctrl { 147 uint8_t bank; 148 uint8_t pin; 149 struct gpio_cfg cfg; 150 }; 151 152 /* 153 * struct stm32_pinctrl_array - Array of pins in a pin control state 154 * @count: Number of cells in @pinctrl 155 * @pinctrl: Pin control configuration 156 */ 157 struct stm32_pinctrl_array { 158 size_t count; 159 struct stm32_pinctrl pinctrl[]; 160 }; 161 162 /** 163 * struct stm32_gpio_bank - GPIO bank instance 164 * 165 * @base: base address of the GPIO controller registers. 166 * @clock: clock identifier. 167 * @gpio_chip: GPIO chip reference for that GPIO bank 168 * @ngpios: number of GPIOs. 169 * @bank_id: Id of the bank. 170 * @lock: lock protecting the GPIO bank access. 171 * @rif_cfg: RIF configuration data 172 * @seccfgr: non-RIF bank secure configuration data 173 * @sec_support: True if bank supports pin security protection, else false 174 * @ready: True if configuration is applied, else false 175 * @is_tdcid: True if OP-TEE runs as Trusted Domain CID 176 * @link: Link in bank list 177 */ 178 struct stm32_gpio_bank { 179 vaddr_t base; 180 struct clk *clock; 181 struct gpio_chip gpio_chip; 182 unsigned int ngpios; 183 unsigned int bank_id; 184 unsigned int lock; 185 struct rif_conf_data *rif_cfg; 186 uint32_t seccfgr; 187 bool sec_support; 188 bool ready; 189 bool is_tdcid; 190 STAILQ_ENTRY(stm32_gpio_bank) link; 191 }; 192 193 /* 194 * struct stm32_gpio_pm_state - Consumed GPIO for PM purpose 195 * @gpio_pinctrl: Reference and configuration state for a consumed GPIO 196 * @level: GPIO level 197 * @link: Link in consumed GPIO list 198 */ 199 struct stm32_gpio_pm_state { 200 struct stm32_pinctrl gpio_pinctrl; 201 uint8_t level; 202 SLIST_ENTRY(stm32_gpio_pm_state) link; 203 }; 204 205 /** 206 * Compatibility information of supported banks 207 * 208 * @gpioz: True if bank is a GPIOZ bank 209 * @secure_control: Identify GPIO security bank capability. 210 * @secure_extended: Identify RIF presence. 211 */ 212 struct bank_compat { 213 bool gpioz; 214 bool secure_control; 215 bool secure_extended; 216 }; 217 218 static unsigned int gpio_lock; 219 220 static STAILQ_HEAD(, stm32_gpio_bank) bank_list = 221 STAILQ_HEAD_INITIALIZER(bank_list); 222 223 static SLIST_HEAD(, stm32_gpio_pm_state) consumed_gpios_head; 224 225 static bool is_stm32_gpio_chip(struct gpio_chip *chip); 226 227 static struct stm32_gpio_bank *gpio_chip_to_bank(struct gpio_chip *chip) 228 { 229 return container_of(chip, struct stm32_gpio_bank, gpio_chip); 230 } 231 232 static enum gpio_level stm32_gpio_get_level(struct gpio_chip *chip, 233 unsigned int gpio_pin) 234 { 235 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 236 enum gpio_level level = GPIO_LEVEL_HIGH; 237 unsigned int reg_offset = 0; 238 unsigned int mode = 0; 239 240 assert(gpio_pin < bank->ngpios); 241 242 if (clk_enable(bank->clock)) 243 panic(); 244 245 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 246 GPIO_MODE_MASK; 247 248 switch (mode) { 249 case GPIO_MODE_INPUT: 250 reg_offset = GPIO_IDR_OFFSET; 251 break; 252 case GPIO_MODE_OUTPUT: 253 reg_offset = GPIO_ODR_OFFSET; 254 break; 255 default: 256 panic(); 257 } 258 259 if (io_read32(bank->base + reg_offset) & BIT(gpio_pin)) 260 level = GPIO_LEVEL_HIGH; 261 else 262 level = GPIO_LEVEL_LOW; 263 264 clk_disable(bank->clock); 265 266 return level; 267 } 268 269 static void stm32_gpio_set_level(struct gpio_chip *chip, unsigned int gpio_pin, 270 enum gpio_level level) 271 { 272 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 273 274 assert(gpio_pin < bank->ngpios); 275 276 if (clk_enable(bank->clock)) 277 panic(); 278 279 assert(((io_read32(bank->base + GPIO_MODER_OFFSET) >> 280 (gpio_pin << 1)) & GPIO_MODE_MASK) == GPIO_MODE_OUTPUT); 281 282 if (level == GPIO_LEVEL_HIGH) 283 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin)); 284 else 285 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin + 16)); 286 287 clk_disable(bank->clock); 288 } 289 290 static enum gpio_dir stm32_gpio_get_direction(struct gpio_chip *chip, 291 unsigned int gpio_pin) 292 { 293 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 294 uint32_t mode = 0; 295 296 assert(gpio_pin < bank->ngpios); 297 298 if (clk_enable(bank->clock)) 299 panic(); 300 301 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 302 GPIO_MODE_MASK; 303 304 clk_disable(bank->clock); 305 306 switch (mode) { 307 case GPIO_MODE_INPUT: 308 return GPIO_DIR_IN; 309 case GPIO_MODE_OUTPUT: 310 return GPIO_DIR_OUT; 311 default: 312 panic(); 313 } 314 } 315 316 static void stm32_gpio_set_direction(struct gpio_chip *chip, 317 unsigned int gpio_pin, 318 enum gpio_dir direction) 319 { 320 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 321 uint32_t exceptions = 0; 322 uint32_t mode = 0; 323 324 assert(gpio_pin < bank->ngpios); 325 326 if (direction == GPIO_DIR_IN) 327 mode = GPIO_MODE_INPUT; 328 else 329 mode = GPIO_MODE_OUTPUT; 330 331 if (clk_enable(bank->clock)) 332 panic(); 333 exceptions = cpu_spin_lock_xsave(&gpio_lock); 334 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 335 SHIFT_U32(GPIO_MODE_MASK, gpio_pin << 1), 336 SHIFT_U32(mode, gpio_pin << 1)); 337 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 338 clk_disable(bank->clock); 339 } 340 341 /* Forward reference to the PM callback handler for consumed GPIOs */ 342 static TEE_Result consumed_gpios_pm(enum pm_op op, unsigned int pm_hint, 343 const struct pm_callback_handle *pm_hdl); 344 345 static void stm32_gpio_put_gpio(struct gpio_chip *chip, struct gpio *gpio) 346 { 347 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 348 struct stm32_gpio_pm_state *tstate = NULL; 349 struct stm32_gpio_pm_state *state = NULL; 350 uint32_t exceptions = 0; 351 352 assert(is_stm32_gpio_chip(chip)); 353 354 exceptions = cpu_spin_lock_xsave(&gpio_lock); 355 356 SLIST_FOREACH_SAFE(state, &consumed_gpios_head, link, tstate) { 357 if (state->gpio_pinctrl.bank == bank->bank_id && 358 state->gpio_pinctrl.pin == gpio->pin) { 359 SLIST_REMOVE(&consumed_gpios_head, state, 360 stm32_gpio_pm_state, link); 361 unregister_pm_driver_cb(consumed_gpios_pm, state); 362 free(state); 363 free(gpio); 364 break; 365 } 366 } 367 assert(state); 368 369 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 370 } 371 372 static const struct gpio_ops stm32_gpio_ops = { 373 .get_direction = stm32_gpio_get_direction, 374 .set_direction = stm32_gpio_set_direction, 375 .get_value = stm32_gpio_get_level, 376 .set_value = stm32_gpio_set_level, 377 .put = stm32_gpio_put_gpio, 378 }; 379 380 static bool __maybe_unused is_stm32_gpio_chip(struct gpio_chip *chip) 381 { 382 return chip && chip->ops == &stm32_gpio_ops; 383 } 384 385 static struct stm32_gpio_bank *stm32_gpio_get_bank(unsigned int bank_id) 386 { 387 struct stm32_gpio_bank *bank = NULL; 388 389 STAILQ_FOREACH(bank, &bank_list, link) 390 if (bank_id == bank->bank_id) 391 return bank; 392 393 panic(); 394 } 395 396 /* Save to output @cfg the current GPIO (@bank_id/@pin) configuration */ 397 static void get_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 398 { 399 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 400 401 if (clk_enable(bank->clock)) 402 panic(); 403 404 /* 405 * Save GPIO configuration bits spread over the few bank registers. 406 * 1bit fields are accessed at bit position being the pin index. 407 * 2bit fields are accessed at bit position being twice the pin index. 408 * 4bit fields are accessed at bit position being fourth the pin index 409 * but accessed from 2 32bit registers at incremental addresses. 410 */ 411 cfg->mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (pin << 1)) & 412 GPIO_MODE_MASK; 413 414 cfg->otype = (io_read32(bank->base + GPIO_OTYPER_OFFSET) >> pin) & 1; 415 416 cfg->ospeed = (io_read32(bank->base + GPIO_OSPEEDR_OFFSET) >> 417 (pin << 1)) & GPIO_OSPEED_MASK; 418 419 cfg->pupd = (io_read32(bank->base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & 420 GPIO_PUPD_PULL_MASK; 421 422 cfg->od = (io_read32(bank->base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; 423 424 if (pin < GPIO_ALT_LOWER_LIMIT) 425 cfg->af = (io_read32(bank->base + GPIO_AFRL_OFFSET) >> 426 (pin << 2)) & GPIO_ALTERNATE_MASK; 427 else 428 cfg->af = (io_read32(bank->base + GPIO_AFRH_OFFSET) >> 429 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) & 430 GPIO_ALTERNATE_MASK; 431 432 clk_disable(bank->clock); 433 } 434 435 /* Apply GPIO (@bank/@pin) configuration described by @cfg */ 436 static void set_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 437 { 438 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 439 uint32_t exceptions = 0; 440 441 if (clk_enable(bank->clock)) 442 panic(); 443 exceptions = cpu_spin_lock_xsave(&gpio_lock); 444 445 /* Load GPIO MODE value, 2bit value shifted by twice the pin number */ 446 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 447 SHIFT_U32(GPIO_MODE_MASK, pin << 1), 448 SHIFT_U32(cfg->mode, pin << 1)); 449 450 /* Load GPIO Output TYPE value, 1bit shifted by pin number value */ 451 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, BIT(pin), 452 SHIFT_U32(cfg->otype, pin)); 453 454 /* Load GPIO Output Speed confguration, 2bit value */ 455 io_clrsetbits32(bank->base + GPIO_OSPEEDR_OFFSET, 456 SHIFT_U32(GPIO_OSPEED_MASK, pin << 1), 457 SHIFT_U32(cfg->ospeed, pin << 1)); 458 459 /* Load GPIO pull configuration, 2bit value */ 460 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, BIT(pin), 461 SHIFT_U32(cfg->pupd, pin << 1)); 462 463 /* Load pin mux Alternate Function configuration, 4bit value */ 464 if (pin < GPIO_ALT_LOWER_LIMIT) { 465 io_clrsetbits32(bank->base + GPIO_AFRL_OFFSET, 466 SHIFT_U32(GPIO_ALTERNATE_MASK, pin << 2), 467 SHIFT_U32(cfg->af, pin << 2)); 468 } else { 469 size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2; 470 471 io_clrsetbits32(bank->base + GPIO_AFRH_OFFSET, 472 SHIFT_U32(GPIO_ALTERNATE_MASK, shift), 473 SHIFT_U32(cfg->af, shift)); 474 } 475 476 /* Load GPIO Output direction confuguration, 1bit */ 477 io_clrsetbits32(bank->base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin); 478 479 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 480 clk_disable(bank->clock); 481 } 482 483 /* Count pins described in the DT node and get related data if possible */ 484 static int get_pinctrl_from_fdt(const void *fdt, int node, 485 struct stm32_pinctrl *pinctrl, size_t count) 486 { 487 const fdt32_t *cuint = NULL; 488 const fdt32_t *slewrate = NULL; 489 int len = 0; 490 uint32_t i = 0; 491 uint32_t speed = GPIO_OSPEED_LOW; 492 uint32_t pull = GPIO_PUPD_NO_PULL; 493 size_t found = 0; 494 495 cuint = fdt_getprop(fdt, node, "pinmux", &len); 496 if (!cuint) 497 return -FDT_ERR_NOTFOUND; 498 499 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); 500 if (slewrate) 501 speed = fdt32_to_cpu(*slewrate); 502 503 if (fdt_getprop(fdt, node, "bias-pull-up", NULL)) 504 pull = GPIO_PUPD_PULL_UP; 505 if (fdt_getprop(fdt, node, "bias-pull-down", NULL)) 506 pull = GPIO_PUPD_PULL_DOWN; 507 508 for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 509 uint32_t pincfg = 0; 510 uint32_t bank = 0; 511 uint32_t pin = 0; 512 uint32_t mode = 0; 513 uint32_t alternate = 0; 514 uint32_t odata = 0; 515 bool opendrain = false; 516 517 pincfg = fdt32_to_cpu(*cuint); 518 cuint++; 519 520 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; 521 522 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT; 523 524 mode = pincfg & DT_GPIO_MODE_MASK; 525 526 switch (mode) { 527 case 0: 528 mode = GPIO_MODE_INPUT; 529 break; 530 case 1: 531 case 2: 532 case 3: 533 case 4: 534 case 5: 535 case 6: 536 case 7: 537 case 8: 538 case 9: 539 case 10: 540 case 11: 541 case 12: 542 case 13: 543 case 14: 544 case 15: 545 case 16: 546 alternate = mode - 1U; 547 mode = GPIO_MODE_ALTERNATE; 548 break; 549 case 17: 550 mode = GPIO_MODE_ANALOG; 551 break; 552 default: 553 mode = GPIO_MODE_OUTPUT; 554 break; 555 } 556 557 if (fdt_getprop(fdt, node, "drive-open-drain", NULL)) 558 opendrain = true; 559 560 if (fdt_getprop(fdt, node, "output-high", NULL) && 561 mode == GPIO_MODE_INPUT) { 562 mode = GPIO_MODE_OUTPUT; 563 odata = 1; 564 } 565 566 if (fdt_getprop(fdt, node, "output-low", NULL) && 567 mode == GPIO_MODE_INPUT) { 568 mode = GPIO_MODE_OUTPUT; 569 odata = 0; 570 } 571 572 if (found < count) { 573 struct stm32_pinctrl *ref = &pinctrl[found]; 574 575 ref->bank = (uint8_t)bank; 576 ref->pin = (uint8_t)pin; 577 ref->cfg.mode = mode; 578 if (opendrain) 579 ref->cfg.otype = GPIO_OTYPE_OPEN_DRAIN; 580 else 581 ref->cfg.otype = GPIO_OTYPE_PUSH_PULL; 582 ref->cfg.ospeed = speed; 583 ref->cfg.pupd = pull; 584 ref->cfg.od = odata; 585 ref->cfg.af = alternate; 586 } 587 588 found++; 589 } 590 591 return (int)found; 592 } 593 594 static TEE_Result consumed_gpios_pm(enum pm_op op, 595 unsigned int pm_hint __unused, 596 const struct pm_callback_handle *pm_hdl) 597 { 598 struct stm32_gpio_pm_state *handle = pm_hdl->handle; 599 unsigned int bank_id = handle->gpio_pinctrl.bank; 600 unsigned int pin = handle->gpio_pinctrl.pin; 601 struct gpio_chip *chip = &stm32_gpio_get_bank(bank_id)->gpio_chip; 602 603 if (op == PM_OP_RESUME) { 604 set_gpio_cfg(bank_id, pin, &handle->gpio_pinctrl.cfg); 605 if (handle->gpio_pinctrl.cfg.mode == GPIO_MODE_OUTPUT) 606 stm32_gpio_set_level(chip, pin, handle->level); 607 } else { 608 get_gpio_cfg(bank_id, pin, &handle->gpio_pinctrl.cfg); 609 if (handle->gpio_pinctrl.cfg.mode == GPIO_MODE_OUTPUT) 610 handle->level = stm32_gpio_get_level(chip, pin); 611 } 612 613 return TEE_SUCCESS; 614 } 615 DECLARE_KEEP_PAGER(consumed_gpios_pm); 616 617 static TEE_Result stm32_gpio_get_dt(struct dt_pargs *pargs, void *data, 618 struct gpio **out_gpio) 619 { 620 TEE_Result res = TEE_ERROR_GENERIC; 621 struct stm32_gpio_pm_state *state = NULL; 622 struct stm32_gpio_bank *bank = data; 623 struct gpio *gpio = NULL; 624 unsigned int shift_1b = 0; 625 unsigned int shift_2b = 0; 626 uint32_t exceptions = 0; 627 uint32_t otype = 0; 628 uint32_t pupd = 0; 629 uint32_t mode = 0; 630 631 res = gpio_dt_alloc_pin(pargs, &gpio); 632 if (res) 633 return res; 634 635 if (gpio->pin >= bank->ngpios) { 636 DMSG("Invalid GPIO reference"); 637 free(gpio); 638 return TEE_ERROR_GENERIC; 639 } 640 641 state = calloc(1, sizeof(*state)); 642 if (!state) { 643 free(gpio); 644 return TEE_ERROR_OUT_OF_MEMORY; 645 } 646 647 state->gpio_pinctrl.pin = gpio->pin; 648 state->gpio_pinctrl.bank = bank->bank_id; 649 SLIST_INSERT_HEAD(&consumed_gpios_head, state, link); 650 651 register_pm_driver_cb(consumed_gpios_pm, state, "stm32-gpio-state"); 652 653 shift_1b = gpio->pin; 654 shift_2b = SHIFT_U32(gpio->pin, 1); 655 656 if (gpio->dt_flags & GPIO_PULL_UP) 657 pupd = GPIO_PUPD_PULL_UP; 658 else if (gpio->dt_flags & GPIO_PULL_DOWN) 659 pupd = GPIO_PUPD_PULL_DOWN; 660 else 661 pupd = GPIO_PUPD_NO_PULL; 662 663 if (gpio->dt_flags & GPIO_LINE_OPEN_DRAIN) 664 otype = GPIO_OTYPE_OPEN_DRAIN; 665 else 666 otype = GPIO_OTYPE_PUSH_PULL; 667 668 if (clk_enable(bank->clock)) 669 panic(); 670 exceptions = cpu_spin_lock_xsave(&gpio_lock); 671 672 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 673 SHIFT_U32(GPIO_MODE_MASK, shift_2b), 674 SHIFT_U32(mode, shift_2b)); 675 676 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, 677 SHIFT_U32(GPIO_OTYPE_OPEN_DRAIN, shift_1b), 678 SHIFT_U32(otype, shift_1b)); 679 680 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, 681 SHIFT_U32(GPIO_PUPD_PULL_MASK, shift_2b), 682 SHIFT_U32(pupd, shift_2b)); 683 684 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 685 clk_disable(bank->clock); 686 687 gpio->chip = &bank->gpio_chip; 688 689 *out_gpio = gpio; 690 691 return TEE_SUCCESS; 692 } 693 694 /* Get bank ID from bank node property st,bank-name or panic on failure */ 695 static unsigned int dt_get_bank_id(const void *fdt, int node) 696 { 697 const int dt_name_len = strlen(DT_GPIO_BANK_NAME0); 698 const fdt32_t *cuint = NULL; 699 int len = 0; 700 701 /* Parse "st,bank-name" to get its id (eg: GPIOA -> 0) */ 702 cuint = fdt_getprop(fdt, node, "st,bank-name", &len); 703 if (!cuint || (len != dt_name_len + 1)) 704 panic("Missing/wrong st,bank-name property"); 705 706 if (strncmp((const char *)cuint, DT_GPIO_BANK_NAME0, dt_name_len - 1) || 707 strcmp((const char *)cuint, DT_GPIO_BANK_NAME0) < 0) 708 panic("Wrong st,bank-name property"); 709 710 return (unsigned int)strcmp((const char *)cuint, DT_GPIO_BANK_NAME0); 711 } 712 713 /* 714 * Return whether or not the GPIO bank related to a DT node is already 715 * registered in the GPIO bank link. 716 */ 717 static bool bank_is_registered(const void *fdt, int node) 718 { 719 unsigned int bank_id = dt_get_bank_id(fdt, node); 720 struct stm32_gpio_bank *bank = NULL; 721 722 STAILQ_FOREACH(bank, &bank_list, link) 723 if (bank->bank_id == bank_id) 724 return true; 725 726 return false; 727 } 728 729 #ifdef CFG_STM32_RIF 730 static TEE_Result handle_available_semaphores(struct stm32_gpio_bank *bank) 731 { 732 TEE_Result res = TEE_ERROR_GENERIC; 733 uint32_t cidcfgr = 0; 734 unsigned int i = 0; 735 736 for (i = 0 ; i < bank->ngpios; i++) { 737 if (!(BIT(i) & bank->rif_cfg->access_mask[0])) 738 continue; 739 740 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(i)); 741 742 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) 743 continue; 744 745 if (!(io_read32(bank->base + GPIO_SECR_OFFSET) & BIT(i))) { 746 res = stm32_rif_release_semaphore(bank->base + 747 GPIO_SEMCR(i), 748 MAX_CID_SUPPORTED); 749 if (res) { 750 EMSG("Cannot release semaphore for resource %u", 751 i); 752 return res; 753 } 754 } else { 755 res = stm32_rif_acquire_semaphore(bank->base + 756 GPIO_SEMCR(i), 757 MAX_CID_SUPPORTED); 758 if (res) { 759 EMSG("Cannot acquire semaphore for resource %u", 760 i); 761 return res; 762 } 763 } 764 } 765 766 return TEE_SUCCESS; 767 } 768 769 static TEE_Result apply_rif_config(struct stm32_gpio_bank *bank) 770 { 771 TEE_Result res = TEE_ERROR_GENERIC; 772 unsigned int i = 0; 773 774 if (!bank->rif_cfg) 775 return TEE_SUCCESS; 776 777 if (clk_enable(bank->clock)) 778 panic(); 779 780 if (bank->is_tdcid) { 781 for (i = 0; i < bank->ngpios; i++) { 782 if (!(BIT(i) & bank->rif_cfg->access_mask[0])) 783 continue; 784 785 /* 786 * When TDCID, OP-TEE should be the one to set the CID 787 * filtering configuration. Clearing previous 788 * configuration prevents undesired events during the 789 * only legitimate configuration. 790 */ 791 io_clrbits32(bank->base + GPIO_CIDCFGR(i), 792 GPIO_CIDCFGR_CONF_MASK); 793 } 794 } else { 795 res = handle_available_semaphores(bank); 796 if (res) 797 panic(); 798 } 799 800 /* Security and privilege RIF configuration */ 801 io_clrsetbits32(bank->base + GPIO_PRIVCFGR_OFFSET, 802 bank->rif_cfg->access_mask[0], 803 bank->rif_cfg->priv_conf[0]); 804 io_clrsetbits32(bank->base + GPIO_SECR_OFFSET, 805 bank->rif_cfg->access_mask[0], 806 bank->rif_cfg->sec_conf[0]); 807 808 if (!bank->is_tdcid) { 809 res = TEE_SUCCESS; 810 goto out; 811 } 812 813 for (i = 0; i < bank->ngpios; i++) { 814 if (!(BIT(i) & bank->rif_cfg->access_mask[0])) 815 continue; 816 817 io_clrsetbits32(bank->base + GPIO_CIDCFGR(i), 818 GPIO_CIDCFGR_CONF_MASK, 819 bank->rif_cfg->cid_confs[i]); 820 } 821 822 /* 823 * Lock RIF configuration if configured. This cannot be undone until 824 * next reset. 825 */ 826 io_setbits32(bank->base + GPIO_RCFGLOCKR_OFFSET, 827 bank->rif_cfg->lock_conf[0]); 828 829 res = handle_available_semaphores(bank); 830 if (res) 831 panic(); 832 833 out: 834 if (IS_ENABLED(CFG_TEE_CORE_DEBUG)) { 835 /* Check that RIF config are applied, panic otherwise */ 836 if ((io_read32(bank->base + GPIO_PRIVCFGR_OFFSET) & 837 bank->rif_cfg->access_mask[0]) != 838 bank->rif_cfg->priv_conf[0]) { 839 EMSG("GPIO bank%c priv conf is incorrect", 840 'A' + bank->bank_id); 841 panic(); 842 } 843 844 if ((io_read32(bank->base + GPIO_SECR_OFFSET) & 845 bank->rif_cfg->access_mask[0]) != 846 bank->rif_cfg->sec_conf[0]) { 847 EMSG("GPIO bank %c sec conf is incorrect", 848 'A' + bank->bank_id); 849 panic(); 850 } 851 } 852 853 clk_disable(bank->clock); 854 855 return res; 856 } 857 #else /* CFG_STM32_RIF */ 858 static TEE_Result apply_rif_config(struct stm32_gpio_bank *bank __unused) 859 { 860 return TEE_SUCCESS; 861 } 862 #endif /* CFG_STM32_RIF */ 863 864 static void stm32_gpio_save_rif_config(struct stm32_gpio_bank *bank) 865 { 866 size_t i = 0; 867 868 for (i = 0; i < bank->ngpios; i++) 869 bank->rif_cfg->cid_confs[i] = io_read32(bank->base + 870 GPIO_CIDCFGR(i)); 871 872 bank->rif_cfg->priv_conf[0] = io_read32(bank->base + 873 GPIO_PRIVCFGR_OFFSET); 874 bank->rif_cfg->sec_conf[0] = io_read32(bank->base + 875 GPIO_SECR_OFFSET); 876 bank->rif_cfg->lock_conf[0] = io_read32(bank->base + 877 GPIO_RCFGLOCKR_OFFSET); 878 } 879 880 static void stm32_parse_gpio_rif_conf(struct stm32_gpio_bank *bank, 881 const void *fdt, int node) 882 { 883 unsigned int i = 0; 884 unsigned int nb_rif_conf = 0; 885 int lenp = 0; 886 const fdt32_t *cuint = NULL; 887 888 cuint = fdt_getprop(fdt, node, "st,protreg", &lenp); 889 if (!cuint) { 890 DMSG("No RIF configuration available"); 891 return; 892 } 893 894 bank->rif_cfg = calloc(1, sizeof(*bank->rif_cfg)); 895 if (!bank->rif_cfg) 896 panic(); 897 898 bank->rif_cfg->sec_conf = calloc(1, sizeof(uint32_t)); 899 if (!bank->rif_cfg->sec_conf) 900 panic(); 901 902 nb_rif_conf = (unsigned int)(lenp / sizeof(uint32_t)); 903 assert(nb_rif_conf <= bank->ngpios); 904 905 bank->rif_cfg->cid_confs = calloc(bank->ngpios, sizeof(uint32_t)); 906 bank->rif_cfg->priv_conf = calloc(1, sizeof(uint32_t)); 907 bank->rif_cfg->lock_conf = calloc(1, sizeof(uint32_t)); 908 bank->rif_cfg->access_mask = calloc(1, sizeof(uint32_t)); 909 if (!bank->rif_cfg->cid_confs || !bank->rif_cfg->access_mask || 910 !bank->rif_cfg->priv_conf || !bank->rif_cfg->lock_conf) 911 panic("Missing memory capacity for GPIOS RIF configuration"); 912 913 for (i = 0; i < nb_rif_conf; i++) 914 stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), bank->rif_cfg, 915 bank->ngpios); 916 } 917 918 /* Get GPIO bank information from the DT */ 919 static TEE_Result dt_stm32_gpio_bank(const void *fdt, int node, 920 const void *compat_data, 921 int range_offset, 922 struct stm32_gpio_bank **out_bank) 923 { 924 const struct bank_compat *compat = compat_data; 925 TEE_Result res = TEE_ERROR_GENERIC; 926 struct stm32_gpio_bank *bank = NULL; 927 const fdt32_t *cuint = NULL; 928 struct io_pa_va pa_va = { }; 929 struct clk *clk = NULL; 930 size_t blen = 0; 931 paddr_t pa = 0; 932 int len = 0; 933 int i = 0; 934 935 assert(out_bank); 936 937 /* Probe deferrable devices first */ 938 res = clk_dt_get_by_index(fdt, node, 0, &clk); 939 if (res) 940 return res; 941 942 bank = calloc(1, sizeof(*bank)); 943 if (!bank) 944 return TEE_ERROR_OUT_OF_MEMORY; 945 946 if (compat->secure_extended) { 947 res = stm32_rifsc_check_tdcid(&bank->is_tdcid); 948 if (res) { 949 free(bank); 950 return res; 951 } 952 } 953 954 /* 955 * Do not rely *only* on the "reg" property to get the address, 956 * but consider also the "ranges" translation property 957 */ 958 if (fdt_reg_info(fdt, node, &pa, &blen)) 959 panic("missing reg or reg size property"); 960 961 pa_va.pa = pa + range_offset; 962 963 DMSG("Bank name %s", fdt_get_name(fdt, node, NULL)); 964 bank->bank_id = dt_get_bank_id(fdt, node); 965 bank->clock = clk; 966 bank->gpio_chip.ops = &stm32_gpio_ops; 967 bank->sec_support = compat->secure_control; 968 969 /* Parse gpio-ranges with its 4 parameters */ 970 cuint = fdt_getprop(fdt, node, "gpio-ranges", &len); 971 len /= sizeof(*cuint); 972 if (len % 4) 973 panic("wrong gpio-ranges syntax"); 974 975 /* Get the last defined gpio line (offset + nb of pins) */ 976 for (i = 0; i < len / 4; i++) { 977 bank->ngpios = MAX(bank->ngpios, 978 (unsigned int)(fdt32_to_cpu(*(cuint + 1)) + 979 fdt32_to_cpu(*(cuint + 3)))); 980 cuint += 4; 981 } 982 983 if (compat->secure_extended) { 984 /* RIF configuration */ 985 bank->base = io_pa_or_va_secure(&pa_va, blen); 986 987 stm32_parse_gpio_rif_conf(bank, fdt, node); 988 } else if (bank->sec_support) { 989 /* Secure configuration */ 990 bank->base = io_pa_or_va_secure(&pa_va, blen); 991 cuint = fdt_getprop(fdt, node, "st,protreg", NULL); 992 if (cuint) 993 bank->seccfgr = fdt32_to_cpu(*cuint); 994 else 995 DMSG("GPIO bank %c assigned to non-secure", 996 bank->bank_id + 'A'); 997 } else { 998 bank->base = io_pa_or_va_nsec(&pa_va, blen); 999 } 1000 1001 if (compat->gpioz) 1002 stm32mp_register_gpioz_pin_count(bank->ngpios); 1003 1004 *out_bank = bank; 1005 1006 return TEE_SUCCESS; 1007 } 1008 1009 /* Parse a pinctrl node to register the GPIO banks it describes */ 1010 static TEE_Result dt_stm32_gpio_pinctrl(const void *fdt, int node, 1011 const void *compat_data) 1012 { 1013 TEE_Result res = TEE_SUCCESS; 1014 const fdt32_t *cuint = NULL; 1015 int range_offs = 0; 1016 int b_node = 0; 1017 int len = 0; 1018 1019 /* Read the ranges property (for regs memory translation) */ 1020 cuint = fdt_getprop(fdt, node, "ranges", &len); 1021 if (!cuint) 1022 panic("missing ranges property"); 1023 1024 len /= sizeof(*cuint); 1025 if (len == 3) 1026 range_offs = fdt32_to_cpu(*(cuint + 1)) - fdt32_to_cpu(*cuint); 1027 1028 fdt_for_each_subnode(b_node, fdt, node) { 1029 cuint = fdt_getprop(fdt, b_node, "gpio-controller", &len); 1030 if (cuint) { 1031 /* 1032 * We found a property "gpio-controller" in the node: 1033 * the node is a GPIO bank description, add it to the 1034 * bank list. 1035 */ 1036 struct stm32_gpio_bank *bank = NULL; 1037 1038 if (fdt_get_status(fdt, b_node) == DT_STATUS_DISABLED || 1039 bank_is_registered(fdt, b_node)) 1040 continue; 1041 1042 res = dt_stm32_gpio_bank(fdt, b_node, compat_data, 1043 range_offs, &bank); 1044 if (res) 1045 return res; 1046 1047 /* Registering a provider should not defer probe */ 1048 res = gpio_register_provider(fdt, b_node, 1049 stm32_gpio_get_dt, bank); 1050 if (res) 1051 panic(); 1052 1053 STAILQ_INSERT_TAIL(&bank_list, bank, link); 1054 } else { 1055 if (len != -FDT_ERR_NOTFOUND) 1056 panic(); 1057 } 1058 } 1059 1060 return TEE_SUCCESS; 1061 } 1062 1063 void stm32_gpio_set_secure_cfg(unsigned int bank_id, unsigned int pin, 1064 bool secure) 1065 { 1066 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 1067 uint32_t exceptions = 0; 1068 1069 if (clk_enable(bank->clock)) 1070 panic(); 1071 exceptions = cpu_spin_lock_xsave(&gpio_lock); 1072 1073 if (secure) 1074 io_setbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 1075 else 1076 io_clrbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 1077 1078 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 1079 clk_disable(bank->clock); 1080 } 1081 1082 #ifdef CFG_DRIVERS_PINCTRL 1083 static TEE_Result stm32_pinctrl_conf_apply(struct pinconf *conf) 1084 { 1085 struct stm32_pinctrl_array *ref = conf->priv; 1086 struct stm32_pinctrl *p = ref->pinctrl; 1087 size_t pin_count = ref->count; 1088 size_t n = 0; 1089 1090 for (n = 0; n < pin_count; n++) 1091 set_gpio_cfg(p[n].bank, p[n].pin, &p[n].cfg); 1092 1093 return TEE_SUCCESS; 1094 } 1095 1096 static void stm32_pinctrl_conf_free(struct pinconf *conf) 1097 { 1098 free(conf); 1099 } 1100 1101 static const struct pinctrl_ops stm32_pinctrl_ops = { 1102 .conf_apply = stm32_pinctrl_conf_apply, 1103 .conf_free = stm32_pinctrl_conf_free, 1104 }; 1105 1106 DECLARE_KEEP_PAGER(stm32_pinctrl_ops); 1107 1108 void stm32_gpio_pinctrl_bank_pin(struct pinctrl_state *pinctrl, 1109 unsigned int *bank, unsigned int *pin, 1110 unsigned int *count) 1111 { 1112 size_t conf_index = 0; 1113 size_t pin_count = 0; 1114 size_t n = 0; 1115 1116 assert(count); 1117 if (!pinctrl) 1118 goto out; 1119 1120 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 1121 struct pinconf *pinconf = pinctrl->confs[conf_index]; 1122 struct stm32_pinctrl_array *ref = pinconf->priv; 1123 1124 /* Consider only the stm32_gpio pins */ 1125 if (pinconf->ops != &stm32_pinctrl_ops) 1126 continue; 1127 1128 if (bank || pin) { 1129 for (n = 0; n < ref->count; n++) { 1130 if (bank && pin_count < *count) 1131 bank[pin_count] = ref->pinctrl[n].bank; 1132 if (pin && pin_count < *count) 1133 pin[pin_count] = ref->pinctrl[n].pin; 1134 pin_count++; 1135 } 1136 } else { 1137 pin_count += ref->count; 1138 } 1139 } 1140 1141 out: 1142 *count = pin_count; 1143 } 1144 1145 void stm32_pinctrl_set_secure_cfg(struct pinctrl_state *pinctrl, bool secure) 1146 { 1147 size_t conf_index = 0; 1148 1149 if (!pinctrl) 1150 return; 1151 1152 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 1153 struct pinconf *pinconf = pinctrl->confs[conf_index]; 1154 struct stm32_pinctrl_array *ref = pinconf->priv; 1155 struct stm32_pinctrl *pc = NULL; 1156 size_t n = 0; 1157 1158 for (n = 0; n < ref->count; n++) { 1159 if (pinconf->ops != &stm32_pinctrl_ops) 1160 continue; 1161 1162 pc = ref->pinctrl + n; 1163 stm32_gpio_set_secure_cfg(pc->bank, pc->pin, secure); 1164 } 1165 } 1166 } 1167 1168 /* Allocate and return a pinctrl configuration from a DT reference */ 1169 static TEE_Result stm32_pinctrl_dt_get(struct dt_pargs *pargs, 1170 void *data __unused, 1171 struct pinconf **out_pinconf) 1172 { 1173 struct conf { 1174 struct pinconf pinconf; 1175 struct stm32_pinctrl_array array_ref; 1176 } *loc_conf = NULL; 1177 struct stm32_pinctrl *pinctrl = NULL; 1178 struct pinconf *pinconf = NULL; 1179 const void *fdt = NULL; 1180 size_t pin_count = 0; 1181 int pinctrl_node = 0; 1182 int pinmux_node = 0; 1183 int count = 0; 1184 1185 pinctrl_node = pargs->phandle_node; 1186 fdt = pargs->fdt; 1187 assert(fdt && pinctrl_node); 1188 1189 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 1190 if (fdt_getprop(fdt, pinmux_node, "pinmux", &count)) 1191 pin_count += (size_t)count / sizeof(uint32_t); 1192 else if (count != -FDT_ERR_NOTFOUND) 1193 panic(); 1194 } 1195 1196 loc_conf = calloc(1, sizeof(*loc_conf) + sizeof(*pinctrl) * pin_count); 1197 if (!loc_conf) 1198 return TEE_ERROR_OUT_OF_MEMORY; 1199 1200 pinconf = &loc_conf->pinconf; 1201 pinconf->ops = &stm32_pinctrl_ops; 1202 pinconf->priv = &loc_conf->array_ref; 1203 1204 loc_conf->array_ref.count = pin_count; 1205 pinctrl = loc_conf->array_ref.pinctrl; 1206 1207 count = 0; 1208 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 1209 int found = 0; 1210 1211 found = get_pinctrl_from_fdt(fdt, pinmux_node, pinctrl + count, 1212 pin_count - count); 1213 if (found <= 0 && found > ((int)pin_count - count)) { 1214 /* We can't recover from an error here so let's panic */ 1215 panic(); 1216 } 1217 1218 count += found; 1219 } 1220 1221 *out_pinconf = pinconf; 1222 1223 return TEE_SUCCESS; 1224 } 1225 #endif /*CFG_DRIVERS_PINCTRL*/ 1226 1227 static void stm32_gpio_get_conf_sec(struct stm32_gpio_bank *bank) 1228 { 1229 if (bank->sec_support) { 1230 clk_enable(bank->clock); 1231 bank->seccfgr = io_read32(bank->base + GPIO_SECR_OFFSET); 1232 clk_disable(bank->clock); 1233 } 1234 } 1235 1236 static void stm32_gpio_set_conf_sec(struct stm32_gpio_bank *bank) 1237 { 1238 if (bank->sec_support) { 1239 clk_enable(bank->clock); 1240 io_write32(bank->base + GPIO_SECR_OFFSET, bank->seccfgr); 1241 clk_disable(bank->clock); 1242 } 1243 } 1244 1245 static TEE_Result stm32_gpio_sec_config_resume(void) 1246 { 1247 TEE_Result res = TEE_ERROR_GENERIC; 1248 struct stm32_gpio_bank *bank = NULL; 1249 1250 STAILQ_FOREACH(bank, &bank_list, link) { 1251 if (bank->rif_cfg) { 1252 if (!bank->is_tdcid) 1253 continue; 1254 1255 bank->rif_cfg->access_mask[0] = GENMASK_32(bank->ngpios, 1256 0); 1257 1258 res = apply_rif_config(bank); 1259 if (res) { 1260 EMSG("Failed to set GPIO bank %c RIF config", 1261 'A' + bank->bank_id); 1262 return res; 1263 } 1264 } else { 1265 stm32_gpio_set_conf_sec(bank); 1266 } 1267 } 1268 1269 return TEE_SUCCESS; 1270 } 1271 1272 static TEE_Result stm32_gpio_sec_config_suspend(void) 1273 { 1274 struct stm32_gpio_bank *bank = NULL; 1275 1276 STAILQ_FOREACH(bank, &bank_list, link) { 1277 if (bank->rif_cfg) { 1278 if (bank->is_tdcid) 1279 stm32_gpio_save_rif_config(bank); 1280 } else { 1281 stm32_gpio_get_conf_sec(bank); 1282 } 1283 } 1284 1285 return TEE_SUCCESS; 1286 } 1287 1288 static TEE_Result 1289 stm32_gpio_sec_config_pm(enum pm_op op, unsigned int pm_hint, 1290 const struct pm_callback_handle *hdl __unused) 1291 { 1292 TEE_Result ret = TEE_ERROR_GENERIC; 1293 1294 if (!PM_HINT_IS_STATE(pm_hint, CONTEXT)) 1295 return TEE_SUCCESS; 1296 1297 if (op == PM_OP_RESUME) 1298 ret = stm32_gpio_sec_config_resume(); 1299 else 1300 ret = stm32_gpio_sec_config_suspend(); 1301 1302 return ret; 1303 } 1304 DECLARE_KEEP_PAGER(stm32_gpio_sec_config_pm); 1305 1306 /* 1307 * Several pinctrl nodes can be probed. Their bank will be put in the unique 1308 * bank_list. To avoid multiple configuration set for a bank when looping 1309 * over each bank in the bank list, ready is set to true when a bank is 1310 * configured. Therefore, during other bank probes, the configuration won't 1311 * be set again. 1312 */ 1313 static TEE_Result apply_sec_cfg(void) 1314 { 1315 TEE_Result res = TEE_ERROR_GENERIC; 1316 struct stm32_gpio_bank *bank = NULL; 1317 1318 STAILQ_FOREACH(bank, &bank_list, link) { 1319 if (bank->ready) 1320 continue; 1321 1322 if (bank->rif_cfg) { 1323 res = apply_rif_config(bank); 1324 if (res) { 1325 EMSG("Failed to set GPIO bank %c RIF config", 1326 'A' + bank->bank_id); 1327 STAILQ_REMOVE(&bank_list, bank, stm32_gpio_bank, 1328 link); 1329 free(bank); 1330 return res; 1331 } 1332 } else { 1333 stm32_gpio_set_conf_sec(bank); 1334 } 1335 1336 bank->ready = true; 1337 } 1338 1339 return TEE_SUCCESS; 1340 } 1341 1342 static TEE_Result stm32_pinctrl_probe(const void *fdt, int node, 1343 const void *compat_data) 1344 { 1345 static bool pm_register; 1346 TEE_Result res = TEE_ERROR_GENERIC; 1347 1348 /* Register GPIO banks described in this pin control node */ 1349 res = dt_stm32_gpio_pinctrl(fdt, node, compat_data); 1350 if (res) 1351 return res; 1352 1353 if (STAILQ_EMPTY(&bank_list)) 1354 DMSG("no gpio bank for that driver"); 1355 else if (apply_sec_cfg()) 1356 panic(); 1357 1358 if (!pm_register) { 1359 /* 1360 * Register to PM once for all probed banks to restore 1361 * their secure configuration. 1362 */ 1363 register_pm_driver_cb(stm32_gpio_sec_config_pm, NULL, 1364 "stm32-gpio-secure-config"); 1365 pm_register = true; 1366 } 1367 1368 #ifdef CFG_DRIVERS_PINCTRL 1369 res = pinctrl_register_provider(fdt, node, stm32_pinctrl_dt_get, 1370 (void *)compat_data); 1371 if (res) 1372 panic(); 1373 #endif 1374 1375 return TEE_SUCCESS; 1376 } 1377 1378 static const struct dt_device_match stm32_pinctrl_match_table[] = { 1379 { 1380 .compatible = "st,stm32mp135-pinctrl", 1381 .compat_data = &(struct bank_compat){ 1382 .secure_control = true, 1383 .secure_extended = false, 1384 }, 1385 }, 1386 { 1387 .compatible = "st,stm32mp157-pinctrl", 1388 .compat_data = &(struct bank_compat){ 1389 .secure_control = false, 1390 .secure_extended = false, 1391 }, 1392 }, 1393 { 1394 .compatible = "st,stm32mp157-z-pinctrl", 1395 .compat_data = &(struct bank_compat){ 1396 .gpioz = true, 1397 .secure_control = true, 1398 .secure_extended = false, 1399 }, 1400 }, 1401 { 1402 .compatible = "st,stm32mp257-pinctrl", 1403 .compat_data = &(struct bank_compat){ 1404 .secure_control = true, 1405 .secure_extended = true, 1406 }, 1407 }, 1408 { 1409 .compatible = "st,stm32mp257-z-pinctrl", 1410 .compat_data = &(struct bank_compat){ 1411 .gpioz = true, 1412 .secure_control = true, 1413 .secure_extended = true, 1414 }, 1415 }, 1416 { } 1417 }; 1418 1419 DEFINE_DT_DRIVER(stm32_pinctrl_dt_driver) = { 1420 .name = "stm32_gpio-pinctrl", 1421 .type = DT_DRIVER_PINCTRL, 1422 .match_table = stm32_pinctrl_match_table, 1423 .probe = stm32_pinctrl_probe, 1424 }; 1425