1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2023, STMicroelectronics 4 * 5 * STM32 GPIO driver is used as pin controller for stm32mp SoCs. 6 * The driver API is defined in header file stm32_gpio.h. 7 */ 8 9 #include <assert.h> 10 #include <drivers/clk.h> 11 #include <drivers/clk_dt.h> 12 #include <drivers/gpio.h> 13 #include <drivers/stm32_gpio.h> 14 #include <io.h> 15 #include <kernel/dt.h> 16 #include <kernel/boot.h> 17 #include <kernel/panic.h> 18 #include <kernel/spinlock.h> 19 #include <libfdt.h> 20 #include <mm/core_memprot.h> 21 #include <stdbool.h> 22 #include <stm32_util.h> 23 #include <sys/queue.h> 24 #include <trace.h> 25 #include <util.h> 26 27 #define GPIO_PIN_MAX 15 28 29 #define GPIO_MODER_OFFSET 0x00 30 #define GPIO_OTYPER_OFFSET 0x04 31 #define GPIO_OSPEEDR_OFFSET 0x08 32 #define GPIO_PUPDR_OFFSET 0x0c 33 #define GPIO_IDR_OFFSET 0x10 34 #define GPIO_ODR_OFFSET 0x14 35 #define GPIO_BSRR_OFFSET 0x18 36 #define GPIO_AFRL_OFFSET 0x20 37 #define GPIO_AFRH_OFFSET 0x24 38 #define GPIO_SECR_OFFSET 0x30 39 40 #define GPIO_ALT_LOWER_LIMIT 0x8 41 42 #define GPIO_MODE_MASK GENMASK_32(1, 0) 43 #define GPIO_OSPEED_MASK GENMASK_32(1, 0) 44 #define GPIO_PUPD_PULL_MASK GENMASK_32(1, 0) 45 #define GPIO_ALTERNATE_MASK GENMASK_32(3, 0) 46 47 #define DT_GPIO_BANK_SHIFT 12 48 #define DT_GPIO_BANK_MASK GENMASK_32(16, 12) 49 #define DT_GPIO_PIN_SHIFT 8 50 #define DT_GPIO_PIN_MASK GENMASK_32(11, 8) 51 #define DT_GPIO_MODE_MASK GENMASK_32(7, 0) 52 53 #define DT_GPIO_BANK_NAME0 "GPIOA" 54 55 /** 56 * struct stm32_gpio_bank - GPIO bank instance 57 * 58 * @base: base address of the GPIO controller registers. 59 * @clock: clock identifier. 60 * @gpio_chip: GPIO chip reference for that GPIO bank 61 * @ngpios: number of GPIOs. 62 * @bank_id: Id of the bank. 63 * @lock: lock protecting the GPIO bank access. 64 * @sec_support: True if bank supports pin security protection, otherwise false 65 * @seccfgr: Secure configuration register value. 66 * @link: Link in bank list 67 */ 68 struct stm32_gpio_bank { 69 vaddr_t base; 70 struct clk *clock; 71 struct gpio_chip gpio_chip; 72 unsigned int ngpios; 73 unsigned int bank_id; 74 unsigned int lock; 75 STAILQ_ENTRY(stm32_gpio_bank) link; 76 }; 77 78 static unsigned int gpio_lock; 79 80 static STAILQ_HEAD(, stm32_gpio_bank) bank_list = 81 STAILQ_HEAD_INITIALIZER(bank_list); 82 83 static bool is_stm32_gpio_chip(struct gpio_chip *chip); 84 85 static struct stm32_gpio_bank *gpio_chip_to_bank(struct gpio_chip *chip) 86 { 87 return container_of(chip, struct stm32_gpio_bank, gpio_chip); 88 } 89 90 static enum gpio_level stm32_gpio_get_level(struct gpio_chip *chip, 91 unsigned int gpio_pin) 92 { 93 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 94 enum gpio_level level = GPIO_LEVEL_HIGH; 95 unsigned int reg_offset = 0; 96 unsigned int mode = 0; 97 98 assert(gpio_pin < bank->ngpios); 99 clk_enable(bank->clock); 100 101 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 102 GPIO_MODE_MASK; 103 104 switch (mode) { 105 case GPIO_MODE_INPUT: 106 reg_offset = GPIO_IDR_OFFSET; 107 break; 108 case GPIO_MODE_OUTPUT: 109 reg_offset = GPIO_ODR_OFFSET; 110 break; 111 default: 112 panic(); 113 } 114 115 if (io_read32(bank->base + reg_offset) & BIT(gpio_pin)) 116 level = GPIO_LEVEL_HIGH; 117 else 118 level = GPIO_LEVEL_LOW; 119 120 clk_disable(bank->clock); 121 122 return level; 123 } 124 125 static void stm32_gpio_set_level(struct gpio_chip *chip, unsigned int gpio_pin, 126 enum gpio_level level) 127 { 128 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 129 130 assert(gpio_pin < bank->ngpios); 131 clk_enable(bank->clock); 132 133 assert(((io_read32(bank->base + GPIO_MODER_OFFSET) >> 134 (gpio_pin << 1)) & GPIO_MODE_MASK) == GPIO_MODE_OUTPUT); 135 136 if (level == GPIO_LEVEL_HIGH) 137 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin)); 138 else 139 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin + 16)); 140 141 clk_disable(bank->clock); 142 } 143 144 static enum gpio_dir stm32_gpio_get_direction(struct gpio_chip *chip, 145 unsigned int gpio_pin) 146 { 147 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 148 uint32_t mode = 0; 149 150 assert(gpio_pin < bank->ngpios); 151 clk_enable(bank->clock); 152 153 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 154 GPIO_MODE_MASK; 155 156 clk_disable(bank->clock); 157 158 switch (mode) { 159 case GPIO_MODE_INPUT: 160 return GPIO_DIR_IN; 161 case GPIO_MODE_OUTPUT: 162 return GPIO_DIR_OUT; 163 default: 164 panic(); 165 } 166 } 167 168 static void stm32_gpio_set_direction(struct gpio_chip *chip, 169 unsigned int gpio_pin, 170 enum gpio_dir direction) 171 { 172 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 173 uint32_t exceptions = 0; 174 uint32_t mode = 0; 175 176 assert(gpio_pin < bank->ngpios); 177 178 if (direction == GPIO_DIR_IN) 179 mode = GPIO_MODE_INPUT; 180 else 181 mode = GPIO_MODE_OUTPUT; 182 183 clk_enable(bank->clock); 184 exceptions = cpu_spin_lock_xsave(&gpio_lock); 185 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 186 SHIFT_U32(GPIO_MODE_MASK, gpio_pin << 1), 187 SHIFT_U32(mode, gpio_pin << 1)); 188 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 189 clk_disable(bank->clock); 190 } 191 192 static void stm32_gpio_put_gpio(struct gpio_chip *chip __maybe_unused, 193 struct gpio *gpio) 194 { 195 assert(is_stm32_gpio_chip(chip)); 196 free(gpio); 197 } 198 199 static const struct gpio_ops stm32_gpio_ops = { 200 .get_direction = stm32_gpio_get_direction, 201 .set_direction = stm32_gpio_set_direction, 202 .get_value = stm32_gpio_get_level, 203 .set_value = stm32_gpio_set_level, 204 .put = stm32_gpio_put_gpio, 205 }; 206 207 static bool __maybe_unused is_stm32_gpio_chip(struct gpio_chip *chip) 208 { 209 return chip && chip->ops == &stm32_gpio_ops; 210 } 211 212 static struct stm32_gpio_bank *stm32_gpio_get_bank(unsigned int bank_id) 213 { 214 struct stm32_gpio_bank *bank = NULL; 215 216 STAILQ_FOREACH(bank, &bank_list, link) 217 if (bank_id == bank->bank_id) 218 return bank; 219 220 panic(); 221 } 222 223 /* Save to output @cfg the current GPIO (@bank_id/@pin) configuration */ 224 static void get_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 225 { 226 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 227 228 if (clk_enable(bank->clock)) 229 panic(); 230 231 /* 232 * Save GPIO configuration bits spread over the few bank registers. 233 * 1bit fields are accessed at bit position being the pin index. 234 * 2bit fields are accessed at bit position being twice the pin index. 235 * 4bit fields are accessed at bit position being fourth the pin index 236 * but accessed from 2 32bit registers at incremental addresses. 237 */ 238 cfg->mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (pin << 1)) & 239 GPIO_MODE_MASK; 240 241 cfg->otype = (io_read32(bank->base + GPIO_OTYPER_OFFSET) >> pin) & 1; 242 243 cfg->ospeed = (io_read32(bank->base + GPIO_OSPEEDR_OFFSET) >> 244 (pin << 1)) & GPIO_OSPEED_MASK; 245 246 cfg->pupd = (io_read32(bank->base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & 247 GPIO_PUPD_PULL_MASK; 248 249 cfg->od = (io_read32(bank->base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; 250 251 if (pin < GPIO_ALT_LOWER_LIMIT) 252 cfg->af = (io_read32(bank->base + GPIO_AFRL_OFFSET) >> 253 (pin << 2)) & GPIO_ALTERNATE_MASK; 254 else 255 cfg->af = (io_read32(bank->base + GPIO_AFRH_OFFSET) >> 256 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) & 257 GPIO_ALTERNATE_MASK; 258 259 clk_disable(bank->clock); 260 } 261 262 /* Apply GPIO (@bank/@pin) configuration described by @cfg */ 263 static void set_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 264 { 265 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 266 uint32_t exceptions = 0; 267 268 if (clk_enable(bank->clock)) 269 panic(); 270 exceptions = cpu_spin_lock_xsave(&gpio_lock); 271 272 /* Load GPIO MODE value, 2bit value shifted by twice the pin number */ 273 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 274 SHIFT_U32(GPIO_MODE_MASK, pin << 1), 275 SHIFT_U32(cfg->mode, pin << 1)); 276 277 /* Load GPIO Output TYPE value, 1bit shifted by pin number value */ 278 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, BIT(pin), 279 SHIFT_U32(cfg->otype, pin)); 280 281 /* Load GPIO Output Speed confguration, 2bit value */ 282 io_clrsetbits32(bank->base + GPIO_OSPEEDR_OFFSET, 283 SHIFT_U32(GPIO_OSPEED_MASK, pin << 1), 284 SHIFT_U32(cfg->ospeed, pin << 1)); 285 286 /* Load GPIO pull configuration, 2bit value */ 287 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, BIT(pin), 288 SHIFT_U32(cfg->pupd, pin << 1)); 289 290 /* Load pin mux Alternate Function configuration, 4bit value */ 291 if (pin < GPIO_ALT_LOWER_LIMIT) { 292 io_clrsetbits32(bank->base + GPIO_AFRL_OFFSET, 293 SHIFT_U32(GPIO_ALTERNATE_MASK, pin << 2), 294 SHIFT_U32(cfg->af, pin << 2)); 295 } else { 296 size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2; 297 298 io_clrsetbits32(bank->base + GPIO_AFRH_OFFSET, 299 SHIFT_U32(GPIO_ALTERNATE_MASK, shift), 300 SHIFT_U32(cfg->af, shift)); 301 } 302 303 /* Load GPIO Output direction confuguration, 1bit */ 304 io_clrsetbits32(bank->base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin); 305 306 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 307 clk_disable(bank->clock); 308 } 309 310 void stm32_pinctrl_load_active_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 311 { 312 size_t n = 0; 313 314 for (n = 0; n < cnt; n++) 315 set_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 316 &pinctrl[n].active_cfg); 317 } 318 319 void stm32_pinctrl_load_standby_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 320 { 321 size_t n = 0; 322 323 for (n = 0; n < cnt; n++) 324 set_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 325 &pinctrl[n].standby_cfg); 326 } 327 328 void stm32_pinctrl_store_standby_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 329 { 330 size_t n = 0; 331 332 for (n = 0; n < cnt; n++) 333 get_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 334 &pinctrl[n].standby_cfg); 335 } 336 337 /* Panic if GPIO bank information from platform do not match DTB description */ 338 static void ckeck_gpio_bank(void *fdt, uint32_t bank, int pinctrl_node) 339 { 340 int pinctrl_subnode = 0; 341 342 fdt_for_each_subnode(pinctrl_subnode, fdt, pinctrl_node) { 343 const fdt32_t *cuint = NULL; 344 345 if (fdt_getprop(fdt, pinctrl_subnode, 346 "gpio-controller", NULL) == NULL) 347 continue; 348 349 /* Check bank register offset matches platform assumptions */ 350 cuint = fdt_getprop(fdt, pinctrl_subnode, "reg", NULL); 351 if (fdt32_to_cpu(*cuint) != stm32_get_gpio_bank_offset(bank)) 352 continue; 353 354 /* Check controller is enabled */ 355 if (fdt_get_status(fdt, pinctrl_subnode) == DT_STATUS_DISABLED) 356 panic(); 357 358 return; 359 } 360 361 panic(); 362 } 363 364 /* Count pins described in the DT node and get related data if possible */ 365 static int get_pinctrl_from_fdt(void *fdt, int node, 366 struct stm32_pinctrl *pinctrl, size_t count) 367 { 368 const fdt32_t *cuint, *slewrate; 369 int len = 0; 370 int pinctrl_node = 0; 371 uint32_t i = 0; 372 uint32_t speed = GPIO_OSPEED_LOW; 373 uint32_t pull = GPIO_PUPD_NO_PULL; 374 size_t found = 0; 375 376 cuint = fdt_getprop(fdt, node, "pinmux", &len); 377 if (!cuint) 378 return -FDT_ERR_NOTFOUND; 379 380 pinctrl_node = fdt_parent_offset(fdt, fdt_parent_offset(fdt, node)); 381 if (pinctrl_node < 0) 382 return -FDT_ERR_NOTFOUND; 383 384 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); 385 if (slewrate) 386 speed = fdt32_to_cpu(*slewrate); 387 388 if (fdt_getprop(fdt, node, "bias-pull-up", NULL)) 389 pull = GPIO_PUPD_PULL_UP; 390 if (fdt_getprop(fdt, node, "bias-pull-down", NULL)) 391 pull = GPIO_PUPD_PULL_DOWN; 392 393 for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 394 uint32_t pincfg = 0; 395 uint32_t bank = 0; 396 uint32_t pin = 0; 397 uint32_t mode = 0; 398 uint32_t alternate = 0; 399 uint32_t odata = 0; 400 bool opendrain = false; 401 402 pincfg = fdt32_to_cpu(*cuint); 403 cuint++; 404 405 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; 406 407 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT; 408 409 mode = pincfg & DT_GPIO_MODE_MASK; 410 411 switch (mode) { 412 case 0: 413 mode = GPIO_MODE_INPUT; 414 break; 415 case 1: 416 case 2: 417 case 3: 418 case 4: 419 case 5: 420 case 6: 421 case 7: 422 case 8: 423 case 9: 424 case 10: 425 case 11: 426 case 12: 427 case 13: 428 case 14: 429 case 15: 430 case 16: 431 alternate = mode - 1U; 432 mode = GPIO_MODE_ALTERNATE; 433 break; 434 case 17: 435 mode = GPIO_MODE_ANALOG; 436 break; 437 default: 438 mode = GPIO_MODE_OUTPUT; 439 break; 440 } 441 442 if (fdt_getprop(fdt, node, "drive-open-drain", NULL)) 443 opendrain = true; 444 445 if (fdt_getprop(fdt, node, "output-high", NULL) && 446 mode == GPIO_MODE_INPUT) { 447 mode = GPIO_MODE_OUTPUT; 448 odata = 1; 449 } 450 451 if (fdt_getprop(fdt, node, "output-low", NULL) && 452 mode == GPIO_MODE_INPUT) { 453 mode = GPIO_MODE_OUTPUT; 454 odata = 0; 455 } 456 457 /* Check GPIO bank clock/base address against platform */ 458 ckeck_gpio_bank(fdt, bank, pinctrl_node); 459 460 if (found < count) { 461 struct stm32_pinctrl *ref = &pinctrl[found]; 462 463 ref->bank = (uint8_t)bank; 464 ref->pin = (uint8_t)pin; 465 ref->active_cfg.mode = mode; 466 ref->active_cfg.otype = opendrain ? 1 : 0; 467 ref->active_cfg.ospeed = speed; 468 ref->active_cfg.pupd = pull; 469 ref->active_cfg.od = odata; 470 ref->active_cfg.af = alternate; 471 /* Default to analog mode for standby state */ 472 ref->standby_cfg.mode = GPIO_MODE_ANALOG; 473 ref->standby_cfg.pupd = GPIO_PUPD_NO_PULL; 474 } 475 476 found++; 477 } 478 479 return (int)found; 480 } 481 482 static struct gpio *stm32_gpio_get_dt(struct dt_pargs *pargs, 483 void *data, TEE_Result *res) 484 { 485 struct stm32_gpio_bank *bank = data; 486 struct gpio *gpio = NULL; 487 unsigned int shift_1b = 0; 488 unsigned int shift_2b = 0; 489 uint32_t exceptions = 0; 490 uint32_t otype = 0; 491 uint32_t pupd = 0; 492 uint32_t mode = 0; 493 494 gpio = gpio_dt_alloc_pin(pargs, res); 495 if (*res) 496 return NULL; 497 498 if (gpio->pin >= bank->ngpios) { 499 DMSG("Invalid GPIO reference"); 500 free(gpio); 501 return NULL; 502 } 503 504 shift_1b = gpio->pin; 505 shift_2b = SHIFT_U32(gpio->pin, 1); 506 507 if (gpio->dt_flags & GPIO_PULL_UP) 508 pupd = GPIO_PUPD_PULL_UP; 509 else if (gpio->dt_flags & GPIO_PULL_DOWN) 510 pupd = GPIO_PUPD_PULL_DOWN; 511 else 512 pupd = GPIO_PUPD_NO_PULL; 513 514 if (gpio->dt_flags & GPIO_LINE_OPEN_DRAIN) 515 otype = GPIO_OTYPE_OPEN_DRAIN; 516 else 517 otype = GPIO_OTYPE_PUSH_PULL; 518 519 if (clk_enable(bank->clock)) 520 panic(); 521 exceptions = cpu_spin_lock_xsave(&gpio_lock); 522 523 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 524 SHIFT_U32(GPIO_MODE_MASK, shift_2b), 525 SHIFT_U32(mode, shift_2b)); 526 527 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, 528 SHIFT_U32(GPIO_OTYPE_OPEN_DRAIN, shift_1b), 529 SHIFT_U32(otype, shift_1b)); 530 531 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, 532 SHIFT_U32(GPIO_PUPD_PULL_MASK, shift_2b), 533 SHIFT_U32(pupd, shift_2b)); 534 535 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 536 clk_disable(bank->clock); 537 538 gpio->chip = &bank->gpio_chip; 539 540 *res = TEE_SUCCESS; 541 542 return gpio; 543 } 544 545 /* Get bank ID from bank node property st,bank-name or panic on failure */ 546 static unsigned int dt_get_bank_id(const void *fdt, int node) 547 { 548 const int dt_name_len = strlen(DT_GPIO_BANK_NAME0); 549 const fdt32_t *cuint = NULL; 550 int len = 0; 551 552 /* Parse "st,bank-name" to get its id (eg: GPIOA -> 0) */ 553 cuint = fdt_getprop(fdt, node, "st,bank-name", &len); 554 if (!cuint || (len != dt_name_len + 1)) 555 panic("Missing/wrong st,bank-name property"); 556 557 if (strncmp((const char *)cuint, DT_GPIO_BANK_NAME0, dt_name_len - 1) || 558 strcmp((const char *)cuint, DT_GPIO_BANK_NAME0) < 0) 559 panic("Wrong st,bank-name property"); 560 561 return (unsigned int)strcmp((const char *)cuint, DT_GPIO_BANK_NAME0); 562 } 563 564 /* 565 * Return whether or not the GPIO bank related to a DT node is already 566 * registered in the GPIO bank link. 567 */ 568 static bool bank_is_registered(const void *fdt, int node) 569 { 570 unsigned int bank_id = dt_get_bank_id(fdt, node); 571 struct stm32_gpio_bank *bank = NULL; 572 573 STAILQ_FOREACH(bank, &bank_list, link) 574 if (bank->bank_id == bank_id) 575 return true; 576 577 return false; 578 } 579 580 /* Get GPIO bank information from the DT */ 581 static TEE_Result dt_stm32_gpio_bank(const void *fdt, int node, 582 const void *compat_data __unused, 583 int range_offset, 584 struct stm32_gpio_bank **out_bank) 585 { 586 TEE_Result res = TEE_ERROR_GENERIC; 587 struct stm32_gpio_bank *bank = NULL; 588 const fdt32_t *cuint = NULL; 589 struct io_pa_va pa_va = { }; 590 struct clk *clk = NULL; 591 size_t blen = 0; 592 paddr_t pa = 0; 593 int len = 0; 594 int i = 0; 595 596 assert(out_bank); 597 598 /* Probe deferrable devices first */ 599 res = clk_dt_get_by_index(fdt, node, 0, &clk); 600 if (res) 601 return res; 602 603 bank = calloc(1, sizeof(*bank)); 604 if (!bank) 605 return TEE_ERROR_OUT_OF_MEMORY; 606 607 /* 608 * Do not rely *only* on the "reg" property to get the address, 609 * but consider also the "ranges" translation property 610 */ 611 pa = fdt_reg_base_address(fdt, node); 612 if (pa == DT_INFO_INVALID_REG) 613 panic("missing reg property"); 614 615 pa_va.pa = pa + range_offset; 616 617 blen = fdt_reg_size(fdt, node); 618 if (blen == DT_INFO_INVALID_REG_SIZE) 619 panic("missing reg size property"); 620 621 DMSG("Bank name %s", fdt_get_name(fdt, node, NULL)); 622 bank->base = io_pa_or_va_secure(&pa_va, blen); 623 bank->bank_id = dt_get_bank_id(fdt, node); 624 bank->clock = clk; 625 bank->gpio_chip.ops = &stm32_gpio_ops; 626 627 /* Parse gpio-ranges with its 4 parameters */ 628 cuint = fdt_getprop(fdt, node, "gpio-ranges", &len); 629 len /= sizeof(*cuint); 630 if (len % 4) 631 panic("wrong gpio-ranges syntax"); 632 633 /* Get the last defined gpio line (offset + nb of pins) */ 634 for (i = 0; i < len / 4; i++) { 635 bank->ngpios = MAX(bank->ngpios, 636 (unsigned int)(fdt32_to_cpu(*(cuint + 1)) + 637 fdt32_to_cpu(*(cuint + 3)))); 638 cuint += 4; 639 } 640 641 *out_bank = bank; 642 return TEE_SUCCESS; 643 } 644 645 /* Parse a pinctrl node to register the GPIO banks it describes */ 646 static TEE_Result dt_stm32_gpio_pinctrl(const void *fdt, int node, 647 const void *compat_data) 648 { 649 TEE_Result res = TEE_SUCCESS; 650 const fdt32_t *cuint = NULL; 651 int range_offs = 0; 652 int b_node = 0; 653 int len = 0; 654 655 /* Read the ranges property (for regs memory translation) */ 656 cuint = fdt_getprop(fdt, node, "ranges", &len); 657 if (!cuint) 658 panic("missing ranges property"); 659 660 len /= sizeof(*cuint); 661 if (len == 3) 662 range_offs = fdt32_to_cpu(*(cuint + 1)) - fdt32_to_cpu(*cuint); 663 664 fdt_for_each_subnode(b_node, fdt, node) { 665 cuint = fdt_getprop(fdt, b_node, "gpio-controller", &len); 666 if (cuint) { 667 /* 668 * We found a property "gpio-controller" in the node: 669 * the node is a GPIO bank description, add it to the 670 * bank list. 671 */ 672 struct stm32_gpio_bank *bank = NULL; 673 674 if (fdt_get_status(fdt, b_node) == DT_STATUS_DISABLED || 675 bank_is_registered(fdt, b_node)) 676 continue; 677 678 res = dt_stm32_gpio_bank(fdt, b_node, compat_data, 679 range_offs, &bank); 680 if (res) 681 return res; 682 683 /* Registering a provider should not defer probe */ 684 res = gpio_register_provider(fdt, b_node, 685 stm32_gpio_get_dt, bank); 686 if (res) 687 panic(); 688 689 STAILQ_INSERT_TAIL(&bank_list, bank, link); 690 } else { 691 if (len != -FDT_ERR_NOTFOUND) 692 panic(); 693 } 694 } 695 696 return TEE_SUCCESS; 697 } 698 699 int stm32_pinctrl_fdt_get_pinctrl(void *fdt, int device_node, 700 struct stm32_pinctrl *pinctrl, size_t count) 701 { 702 const fdt32_t *cuint = NULL; 703 int lenp = 0; 704 int i = 0; 705 size_t found = 0; 706 707 cuint = fdt_getprop(fdt, device_node, "pinctrl-0", &lenp); 708 if (!cuint) 709 return -FDT_ERR_NOTFOUND; 710 711 for (i = 0; i < (lenp / 4); i++) { 712 int node = 0; 713 int subnode = 0; 714 715 node = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 716 if (node < 0) 717 return -FDT_ERR_NOTFOUND; 718 719 fdt_for_each_subnode(subnode, fdt, node) { 720 size_t n = 0; 721 int rc = 0; 722 723 if (count > found) 724 n = count - found; 725 else 726 n = 0; 727 728 rc = get_pinctrl_from_fdt(fdt, subnode, 729 &pinctrl[found], n); 730 if (rc < 0) 731 return rc; 732 733 found += (size_t)rc; 734 } 735 736 cuint++; 737 } 738 739 return (int)found; 740 } 741 742 int stm32_get_gpio_count(void *fdt, int pinctrl_node, unsigned int bank) 743 { 744 int node = 0; 745 const fdt32_t *cuint = NULL; 746 747 fdt_for_each_subnode(node, fdt, pinctrl_node) { 748 if (!fdt_getprop(fdt, node, "gpio-controller", NULL)) 749 continue; 750 751 cuint = fdt_getprop(fdt, node, "reg", NULL); 752 if (!cuint) 753 continue; 754 755 if (fdt32_to_cpu(*cuint) != stm32_get_gpio_bank_offset(bank)) 756 continue; 757 758 cuint = fdt_getprop(fdt, node, "ngpios", NULL); 759 if (!cuint) 760 panic(); 761 762 return (int)fdt32_to_cpu(*cuint); 763 } 764 765 return -1; 766 } 767 768 static __maybe_unused bool valid_gpio_config(unsigned int bank_id, 769 unsigned int pin, bool input) 770 { 771 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 772 uint32_t mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> 773 (pin << 1)) & GPIO_MODE_MASK; 774 775 if (pin > GPIO_PIN_MAX) 776 return false; 777 778 if (input) 779 return mode == GPIO_MODE_INPUT; 780 else 781 return mode == GPIO_MODE_OUTPUT; 782 } 783 784 int stm32_gpio_get_input_level(unsigned int bank_id, unsigned int pin) 785 { 786 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 787 int rc = 0; 788 789 if (clk_enable(bank->clock)) 790 panic(); 791 792 assert(valid_gpio_config(bank_id, pin, true)); 793 794 if (io_read32(bank->base + GPIO_IDR_OFFSET) == BIT(pin)) 795 rc = 1; 796 797 clk_disable(bank->clock); 798 799 return rc; 800 } 801 802 void stm32_gpio_set_output_level(unsigned int bank_id, unsigned int pin, 803 int level) 804 { 805 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 806 807 if (clk_enable(bank->clock)) 808 panic(); 809 810 assert(valid_gpio_config(bank_id, pin, false)); 811 812 if (level) 813 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(pin)); 814 else 815 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(pin + 16)); 816 817 clk_disable(bank->clock); 818 } 819 820 void stm32_gpio_set_secure_cfg(unsigned int bank_id, unsigned int pin, 821 bool secure) 822 { 823 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 824 uint32_t exceptions = 0; 825 826 if (clk_enable(bank->clock)) 827 panic(); 828 exceptions = cpu_spin_lock_xsave(&gpio_lock); 829 830 if (secure) 831 io_setbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 832 else 833 io_clrbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 834 835 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 836 clk_disable(bank->clock); 837 } 838 839 static TEE_Result stm32_pinctrl_probe(const void *fdt, int node, 840 const void *compat_data) 841 { 842 /* Register GPIO banks described in this pin control node */ 843 return dt_stm32_gpio_pinctrl(fdt, node, compat_data); 844 } 845 846 static const struct dt_device_match stm32_pinctrl_match_table[] = { 847 { .compatible = "st,stm32mp135-pinctrl" }, 848 { .compatible = "st,stm32mp157-pinctrl" }, 849 { .compatible = "st,stm32mp157-z-pinctrl" }, 850 { } 851 }; 852 853 DEFINE_DT_DRIVER(stm32_pinctrl_dt_driver) = { 854 .name = "stm32_gpio-pinctrl", 855 .type = DT_DRIVER_PINCTRL, 856 .match_table = stm32_pinctrl_match_table, 857 .probe = stm32_pinctrl_probe, 858 }; 859