1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2023, STMicroelectronics 4 * 5 * STM32 GPIO driver is used as pin controller for stm32mp SoCs. 6 * The driver API is defined in header file stm32_gpio.h. 7 */ 8 9 #include <assert.h> 10 #include <drivers/clk.h> 11 #include <drivers/clk_dt.h> 12 #include <drivers/stm32_gpio.h> 13 #include <io.h> 14 #include <kernel/dt.h> 15 #include <kernel/boot.h> 16 #include <kernel/panic.h> 17 #include <kernel/spinlock.h> 18 #include <libfdt.h> 19 #include <mm/core_memprot.h> 20 #include <stdbool.h> 21 #include <stm32_util.h> 22 #include <sys/queue.h> 23 #include <trace.h> 24 #include <util.h> 25 26 #define GPIO_PIN_MAX 15 27 28 #define GPIO_MODER_OFFSET 0x00 29 #define GPIO_OTYPER_OFFSET 0x04 30 #define GPIO_OSPEEDR_OFFSET 0x08 31 #define GPIO_PUPDR_OFFSET 0x0c 32 #define GPIO_IDR_OFFSET 0x10 33 #define GPIO_ODR_OFFSET 0x14 34 #define GPIO_BSRR_OFFSET 0x18 35 #define GPIO_AFRL_OFFSET 0x20 36 #define GPIO_AFRH_OFFSET 0x24 37 #define GPIO_SECR_OFFSET 0x30 38 39 #define GPIO_ALT_LOWER_LIMIT 0x8 40 41 #define GPIO_MODE_MASK GENMASK_32(1, 0) 42 #define GPIO_OSPEED_MASK GENMASK_32(1, 0) 43 #define GPIO_PUPD_PULL_MASK GENMASK_32(1, 0) 44 #define GPIO_ALTERNATE_MASK GENMASK_32(3, 0) 45 46 #define DT_GPIO_BANK_SHIFT 12 47 #define DT_GPIO_BANK_MASK GENMASK_32(16, 12) 48 #define DT_GPIO_PIN_SHIFT 8 49 #define DT_GPIO_PIN_MASK GENMASK_32(11, 8) 50 #define DT_GPIO_MODE_MASK GENMASK_32(7, 0) 51 52 #define DT_GPIO_BANK_NAME0 "GPIOA" 53 54 /** 55 * struct stm32_gpio_bank - GPIO bank instance 56 * 57 * @base: base address of the GPIO controller registers. 58 * @clock: clock identifier. 59 * @ngpios: number of GPIOs. 60 * @bank_id: Id of the bank. 61 * @lock: lock protecting the GPIO bank access. 62 * @sec_support: True if bank supports pin security protection, otherwise false 63 * @seccfgr: Secure configuration register value. 64 * @link: Link in bank list 65 */ 66 struct stm32_gpio_bank { 67 vaddr_t base; 68 struct clk *clock; 69 unsigned int ngpios; 70 unsigned int bank_id; 71 unsigned int lock; 72 STAILQ_ENTRY(stm32_gpio_bank) link; 73 }; 74 75 static unsigned int gpio_lock; 76 77 static STAILQ_HEAD(, stm32_gpio_bank) bank_list = 78 STAILQ_HEAD_INITIALIZER(bank_list); 79 80 static struct stm32_gpio_bank *stm32_gpio_get_bank(unsigned int bank_id) 81 { 82 struct stm32_gpio_bank *bank = NULL; 83 84 STAILQ_FOREACH(bank, &bank_list, link) 85 if (bank_id == bank->bank_id) 86 return bank; 87 88 panic(); 89 } 90 91 /* Save to output @cfg the current GPIO (@bank_id/@pin) configuration */ 92 static void get_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 93 { 94 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 95 96 if (clk_enable(bank->clock)) 97 panic(); 98 99 /* 100 * Save GPIO configuration bits spread over the few bank registers. 101 * 1bit fields are accessed at bit position being the pin index. 102 * 2bit fields are accessed at bit position being twice the pin index. 103 * 4bit fields are accessed at bit position being fourth the pin index 104 * but accessed from 2 32bit registers at incremental addresses. 105 */ 106 cfg->mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (pin << 1)) & 107 GPIO_MODE_MASK; 108 109 cfg->otype = (io_read32(bank->base + GPIO_OTYPER_OFFSET) >> pin) & 1; 110 111 cfg->ospeed = (io_read32(bank->base + GPIO_OSPEEDR_OFFSET) >> 112 (pin << 1)) & GPIO_OSPEED_MASK; 113 114 cfg->pupd = (io_read32(bank->base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & 115 GPIO_PUPD_PULL_MASK; 116 117 cfg->od = (io_read32(bank->base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; 118 119 if (pin < GPIO_ALT_LOWER_LIMIT) 120 cfg->af = (io_read32(bank->base + GPIO_AFRL_OFFSET) >> 121 (pin << 2)) & GPIO_ALTERNATE_MASK; 122 else 123 cfg->af = (io_read32(bank->base + GPIO_AFRH_OFFSET) >> 124 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) & 125 GPIO_ALTERNATE_MASK; 126 127 clk_disable(bank->clock); 128 } 129 130 /* Apply GPIO (@bank/@pin) configuration described by @cfg */ 131 static void set_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 132 { 133 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 134 uint32_t exceptions = cpu_spin_lock_xsave(&gpio_lock); 135 136 if (clk_enable(bank->clock)) 137 panic(); 138 139 /* Load GPIO MODE value, 2bit value shifted by twice the pin number */ 140 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 141 SHIFT_U32(GPIO_MODE_MASK, pin << 1), 142 SHIFT_U32(cfg->mode, pin << 1)); 143 144 /* Load GPIO Output TYPE value, 1bit shifted by pin number value */ 145 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, BIT(pin), 146 SHIFT_U32(cfg->otype, pin)); 147 148 /* Load GPIO Output Speed confguration, 2bit value */ 149 io_clrsetbits32(bank->base + GPIO_OSPEEDR_OFFSET, 150 SHIFT_U32(GPIO_OSPEED_MASK, pin << 1), 151 SHIFT_U32(cfg->ospeed, pin << 1)); 152 153 /* Load GPIO pull configuration, 2bit value */ 154 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, BIT(pin), 155 SHIFT_U32(cfg->pupd, pin << 1)); 156 157 /* Load pin mux Alternate Function configuration, 4bit value */ 158 if (pin < GPIO_ALT_LOWER_LIMIT) { 159 io_clrsetbits32(bank->base + GPIO_AFRL_OFFSET, 160 SHIFT_U32(GPIO_ALTERNATE_MASK, pin << 2), 161 SHIFT_U32(cfg->af, pin << 2)); 162 } else { 163 size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2; 164 165 io_clrsetbits32(bank->base + GPIO_AFRH_OFFSET, 166 SHIFT_U32(GPIO_ALTERNATE_MASK, shift), 167 SHIFT_U32(cfg->af, shift)); 168 } 169 170 /* Load GPIO Output direction confuguration, 1bit */ 171 io_clrsetbits32(bank->base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin); 172 173 clk_disable(bank->clock); 174 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 175 } 176 177 void stm32_pinctrl_load_active_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 178 { 179 size_t n = 0; 180 181 for (n = 0; n < cnt; n++) 182 set_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 183 &pinctrl[n].active_cfg); 184 } 185 186 void stm32_pinctrl_load_standby_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 187 { 188 size_t n = 0; 189 190 for (n = 0; n < cnt; n++) 191 set_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 192 &pinctrl[n].standby_cfg); 193 } 194 195 void stm32_pinctrl_store_standby_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 196 { 197 size_t n = 0; 198 199 for (n = 0; n < cnt; n++) 200 get_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 201 &pinctrl[n].standby_cfg); 202 } 203 204 /* Panic if GPIO bank information from platform do not match DTB description */ 205 static void ckeck_gpio_bank(void *fdt, uint32_t bank, int pinctrl_node) 206 { 207 int pinctrl_subnode = 0; 208 209 fdt_for_each_subnode(pinctrl_subnode, fdt, pinctrl_node) { 210 const fdt32_t *cuint = NULL; 211 212 if (fdt_getprop(fdt, pinctrl_subnode, 213 "gpio-controller", NULL) == NULL) 214 continue; 215 216 /* Check bank register offset matches platform assumptions */ 217 cuint = fdt_getprop(fdt, pinctrl_subnode, "reg", NULL); 218 if (fdt32_to_cpu(*cuint) != stm32_get_gpio_bank_offset(bank)) 219 continue; 220 221 /* Check controller is enabled */ 222 if (fdt_get_status(fdt, pinctrl_subnode) == DT_STATUS_DISABLED) 223 panic(); 224 225 return; 226 } 227 228 panic(); 229 } 230 231 /* Count pins described in the DT node and get related data if possible */ 232 static int get_pinctrl_from_fdt(void *fdt, int node, 233 struct stm32_pinctrl *pinctrl, size_t count) 234 { 235 const fdt32_t *cuint, *slewrate; 236 int len = 0; 237 int pinctrl_node = 0; 238 uint32_t i = 0; 239 uint32_t speed = GPIO_OSPEED_LOW; 240 uint32_t pull = GPIO_PUPD_NO_PULL; 241 size_t found = 0; 242 243 cuint = fdt_getprop(fdt, node, "pinmux", &len); 244 if (!cuint) 245 return -FDT_ERR_NOTFOUND; 246 247 pinctrl_node = fdt_parent_offset(fdt, fdt_parent_offset(fdt, node)); 248 if (pinctrl_node < 0) 249 return -FDT_ERR_NOTFOUND; 250 251 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); 252 if (slewrate) 253 speed = fdt32_to_cpu(*slewrate); 254 255 if (fdt_getprop(fdt, node, "bias-pull-up", NULL)) 256 pull = GPIO_PUPD_PULL_UP; 257 if (fdt_getprop(fdt, node, "bias-pull-down", NULL)) 258 pull = GPIO_PUPD_PULL_DOWN; 259 260 for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 261 uint32_t pincfg = 0; 262 uint32_t bank = 0; 263 uint32_t pin = 0; 264 uint32_t mode = 0; 265 uint32_t alternate = 0; 266 uint32_t odata = 0; 267 bool opendrain = false; 268 269 pincfg = fdt32_to_cpu(*cuint); 270 cuint++; 271 272 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; 273 274 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT; 275 276 mode = pincfg & DT_GPIO_MODE_MASK; 277 278 switch (mode) { 279 case 0: 280 mode = GPIO_MODE_INPUT; 281 break; 282 case 1: 283 case 2: 284 case 3: 285 case 4: 286 case 5: 287 case 6: 288 case 7: 289 case 8: 290 case 9: 291 case 10: 292 case 11: 293 case 12: 294 case 13: 295 case 14: 296 case 15: 297 case 16: 298 alternate = mode - 1U; 299 mode = GPIO_MODE_ALTERNATE; 300 break; 301 case 17: 302 mode = GPIO_MODE_ANALOG; 303 break; 304 default: 305 mode = GPIO_MODE_OUTPUT; 306 break; 307 } 308 309 if (fdt_getprop(fdt, node, "drive-open-drain", NULL)) 310 opendrain = true; 311 312 if (fdt_getprop(fdt, node, "output-high", NULL) && 313 mode == GPIO_MODE_INPUT) { 314 mode = GPIO_MODE_OUTPUT; 315 odata = 1; 316 } 317 318 if (fdt_getprop(fdt, node, "output-low", NULL) && 319 mode == GPIO_MODE_INPUT) { 320 mode = GPIO_MODE_OUTPUT; 321 odata = 0; 322 } 323 324 /* Check GPIO bank clock/base address against platform */ 325 ckeck_gpio_bank(fdt, bank, pinctrl_node); 326 327 if (found < count) { 328 struct stm32_pinctrl *ref = &pinctrl[found]; 329 330 ref->bank = (uint8_t)bank; 331 ref->pin = (uint8_t)pin; 332 ref->active_cfg.mode = mode; 333 ref->active_cfg.otype = opendrain ? 1 : 0; 334 ref->active_cfg.ospeed = speed; 335 ref->active_cfg.pupd = pull; 336 ref->active_cfg.od = odata; 337 ref->active_cfg.af = alternate; 338 /* Default to analog mode for standby state */ 339 ref->standby_cfg.mode = GPIO_MODE_ANALOG; 340 ref->standby_cfg.pupd = GPIO_PUPD_NO_PULL; 341 } 342 343 found++; 344 } 345 346 return (int)found; 347 } 348 349 /* Get bank ID from bank node property st,bank-name or panic on failure */ 350 static unsigned int dt_get_bank_id(const void *fdt, int node) 351 { 352 const int dt_name_len = strlen(DT_GPIO_BANK_NAME0); 353 const fdt32_t *cuint = NULL; 354 int len = 0; 355 356 /* Parse "st,bank-name" to get its id (eg: GPIOA -> 0) */ 357 cuint = fdt_getprop(fdt, node, "st,bank-name", &len); 358 if (!cuint || (len != dt_name_len + 1)) 359 panic("Missing/wrong st,bank-name property"); 360 361 if (strncmp((const char *)cuint, DT_GPIO_BANK_NAME0, dt_name_len - 1) || 362 strcmp((const char *)cuint, DT_GPIO_BANK_NAME0) < 0) 363 panic("Wrong st,bank-name property"); 364 365 return (unsigned int)strcmp((const char *)cuint, DT_GPIO_BANK_NAME0); 366 } 367 368 /* 369 * Return whether or not the GPIO bank related to a DT node is already 370 * registered in the GPIO bank link. 371 */ 372 static bool bank_is_registered(const void *fdt, int node) 373 { 374 unsigned int bank_id = dt_get_bank_id(fdt, node); 375 struct stm32_gpio_bank *bank = NULL; 376 377 STAILQ_FOREACH(bank, &bank_list, link) 378 if (bank->bank_id == bank_id) 379 return true; 380 381 return false; 382 } 383 384 /* Get GPIO bank information from the DT */ 385 static TEE_Result dt_stm32_gpio_bank(const void *fdt, int node, 386 const void *compat_data __unused, 387 int range_offset, 388 struct stm32_gpio_bank **out_bank) 389 { 390 TEE_Result res = TEE_ERROR_GENERIC; 391 struct stm32_gpio_bank *bank = NULL; 392 const fdt32_t *cuint = NULL; 393 struct io_pa_va pa_va = { }; 394 struct clk *clk = NULL; 395 size_t blen = 0; 396 paddr_t pa = 0; 397 int len = 0; 398 int i = 0; 399 400 assert(out_bank); 401 402 /* Probe deferrable devices first */ 403 res = clk_dt_get_by_index(fdt, node, 0, &clk); 404 if (res) 405 return res; 406 407 bank = calloc(1, sizeof(*bank)); 408 if (!bank) 409 return TEE_ERROR_OUT_OF_MEMORY; 410 411 /* 412 * Do not rely *only* on the "reg" property to get the address, 413 * but consider also the "ranges" translation property 414 */ 415 pa = fdt_reg_base_address(fdt, node); 416 if (pa == DT_INFO_INVALID_REG) 417 panic("missing reg property"); 418 419 pa_va.pa = pa + range_offset; 420 421 blen = fdt_reg_size(fdt, node); 422 if (blen == DT_INFO_INVALID_REG_SIZE) 423 panic("missing reg size property"); 424 425 DMSG("Bank name %s", fdt_get_name(fdt, node, NULL)); 426 bank->base = io_pa_or_va_secure(&pa_va, blen); 427 bank->bank_id = dt_get_bank_id(fdt, node); 428 bank->clock = clk; 429 430 /* Parse gpio-ranges with its 4 parameters */ 431 cuint = fdt_getprop(fdt, node, "gpio-ranges", &len); 432 len /= sizeof(*cuint); 433 if (len % 4) 434 panic("wrong gpio-ranges syntax"); 435 436 /* Get the last defined gpio line (offset + nb of pins) */ 437 for (i = 0; i < len / 4; i++) { 438 bank->ngpios = MAX(bank->ngpios, 439 (unsigned int)(fdt32_to_cpu(*(cuint + 1)) + 440 fdt32_to_cpu(*(cuint + 3)))); 441 cuint += 4; 442 } 443 444 *out_bank = bank; 445 return TEE_SUCCESS; 446 } 447 448 /* Parse a pinctrl node to register the GPIO banks it describes */ 449 static TEE_Result dt_stm32_gpio_pinctrl(const void *fdt, int node, 450 const void *compat_data) 451 { 452 TEE_Result res = TEE_SUCCESS; 453 const fdt32_t *cuint = NULL; 454 int range_offs = 0; 455 int b_node = 0; 456 int len = 0; 457 458 /* Read the ranges property (for regs memory translation) */ 459 cuint = fdt_getprop(fdt, node, "ranges", &len); 460 if (!cuint) 461 panic("missing ranges property"); 462 463 len /= sizeof(*cuint); 464 if (len == 3) 465 range_offs = fdt32_to_cpu(*(cuint + 1)) - fdt32_to_cpu(*cuint); 466 467 fdt_for_each_subnode(b_node, fdt, node) { 468 cuint = fdt_getprop(fdt, b_node, "gpio-controller", &len); 469 if (cuint) { 470 /* 471 * We found a property "gpio-controller" in the node: 472 * the node is a GPIO bank description, add it to the 473 * bank list. 474 */ 475 struct stm32_gpio_bank *bank = NULL; 476 477 if (fdt_get_status(fdt, b_node) == DT_STATUS_DISABLED || 478 bank_is_registered(fdt, b_node)) 479 continue; 480 481 res = dt_stm32_gpio_bank(fdt, b_node, compat_data, 482 range_offs, &bank); 483 if (res) 484 return res; 485 486 STAILQ_INSERT_TAIL(&bank_list, bank, link); 487 } else { 488 if (len != -FDT_ERR_NOTFOUND) 489 panic(); 490 } 491 } 492 493 return TEE_SUCCESS; 494 } 495 496 int stm32_pinctrl_fdt_get_pinctrl(void *fdt, int device_node, 497 struct stm32_pinctrl *pinctrl, size_t count) 498 { 499 const fdt32_t *cuint = NULL; 500 int lenp = 0; 501 int i = 0; 502 size_t found = 0; 503 504 cuint = fdt_getprop(fdt, device_node, "pinctrl-0", &lenp); 505 if (!cuint) 506 return -FDT_ERR_NOTFOUND; 507 508 for (i = 0; i < (lenp / 4); i++) { 509 int node = 0; 510 int subnode = 0; 511 512 node = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 513 if (node < 0) 514 return -FDT_ERR_NOTFOUND; 515 516 fdt_for_each_subnode(subnode, fdt, node) { 517 size_t n = 0; 518 int rc = 0; 519 520 if (count > found) 521 n = count - found; 522 else 523 n = 0; 524 525 rc = get_pinctrl_from_fdt(fdt, subnode, 526 &pinctrl[found], n); 527 if (rc < 0) 528 return rc; 529 530 found += (size_t)rc; 531 } 532 533 cuint++; 534 } 535 536 return (int)found; 537 } 538 539 int stm32_get_gpio_count(void *fdt, int pinctrl_node, unsigned int bank) 540 { 541 int node = 0; 542 const fdt32_t *cuint = NULL; 543 544 fdt_for_each_subnode(node, fdt, pinctrl_node) { 545 if (!fdt_getprop(fdt, node, "gpio-controller", NULL)) 546 continue; 547 548 cuint = fdt_getprop(fdt, node, "reg", NULL); 549 if (!cuint) 550 continue; 551 552 if (fdt32_to_cpu(*cuint) != stm32_get_gpio_bank_offset(bank)) 553 continue; 554 555 cuint = fdt_getprop(fdt, node, "ngpios", NULL); 556 if (!cuint) 557 panic(); 558 559 return (int)fdt32_to_cpu(*cuint); 560 } 561 562 return -1; 563 } 564 565 static __maybe_unused bool valid_gpio_config(unsigned int bank_id, 566 unsigned int pin, bool input) 567 { 568 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 569 uint32_t mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> 570 (pin << 1)) & GPIO_MODE_MASK; 571 572 if (pin > GPIO_PIN_MAX) 573 return false; 574 575 if (input) 576 return mode == GPIO_MODE_INPUT; 577 else 578 return mode == GPIO_MODE_OUTPUT; 579 } 580 581 int stm32_gpio_get_input_level(unsigned int bank_id, unsigned int pin) 582 { 583 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 584 int rc = 0; 585 586 if (clk_enable(bank->clock)) 587 panic(); 588 589 assert(valid_gpio_config(bank_id, pin, true)); 590 591 if (io_read32(bank->base + GPIO_IDR_OFFSET) == BIT(pin)) 592 rc = 1; 593 594 clk_disable(bank->clock); 595 596 return rc; 597 } 598 599 void stm32_gpio_set_output_level(unsigned int bank_id, unsigned int pin, 600 int level) 601 { 602 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 603 604 if (clk_enable(bank->clock)) 605 panic(); 606 607 assert(valid_gpio_config(bank_id, pin, false)); 608 609 if (level) 610 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(pin)); 611 else 612 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(pin + 16)); 613 614 clk_disable(bank->clock); 615 } 616 617 void stm32_gpio_set_secure_cfg(unsigned int bank_id, unsigned int pin, 618 bool secure) 619 { 620 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 621 uint32_t exceptions = cpu_spin_lock_xsave(&gpio_lock); 622 623 if (clk_enable(bank->clock)) 624 panic(); 625 626 if (secure) 627 io_setbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 628 else 629 io_clrbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 630 631 clk_disable(bank->clock); 632 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 633 } 634 635 static TEE_Result stm32_pinctrl_probe(const void *fdt, int node, 636 const void *compat_data) 637 { 638 /* Register GPIO banks described in this pin control node */ 639 return dt_stm32_gpio_pinctrl(fdt, node, compat_data); 640 } 641 642 static const struct dt_device_match stm32_pinctrl_match_table[] = { 643 { .compatible = "st,stm32mp135-pinctrl" }, 644 { .compatible = "st,stm32mp157-pinctrl" }, 645 { .compatible = "st,stm32mp157-z-pinctrl" }, 646 { } 647 }; 648 649 DEFINE_DT_DRIVER(stm32_pinctrl_dt_driver) = { 650 .name = "stm32_gpio-pinctrl", 651 .type = DT_DRIVER_PINCTRL, 652 .match_table = stm32_pinctrl_match_table, 653 .probe = stm32_pinctrl_probe, 654 }; 655