1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2023, STMicroelectronics 4 * 5 * STM32 GPIO driver is used as pin controller for stm32mp SoCs. 6 */ 7 8 #include <assert.h> 9 #include <compiler.h> 10 #include <drivers/clk.h> 11 #include <drivers/clk_dt.h> 12 #include <drivers/gpio.h> 13 #include <drivers/pinctrl.h> 14 #include <drivers/stm32_gpio.h> 15 #include <dt-bindings/gpio/stm32mp_gpio.h> 16 #include <io.h> 17 #include <kernel/dt.h> 18 #include <kernel/boot.h> 19 #include <kernel/panic.h> 20 #include <kernel/spinlock.h> 21 #include <libfdt.h> 22 #include <mm/core_memprot.h> 23 #include <stdbool.h> 24 #include <stdint.h> 25 #include <stm32_util.h> 26 #include <sys/queue.h> 27 #include <trace.h> 28 #include <util.h> 29 30 #ifndef CFG_DRIVERS_GPIO 31 #error stm32_gpio driver expects CFG_DRIVERS_GPIO 32 #endif 33 34 #define GPIO_PIN_MAX 15 35 36 #define GPIO_MODER_OFFSET U(0x00) 37 #define GPIO_OTYPER_OFFSET U(0x04) 38 #define GPIO_OSPEEDR_OFFSET U(0x08) 39 #define GPIO_PUPDR_OFFSET U(0x0c) 40 #define GPIO_IDR_OFFSET U(0x10) 41 #define GPIO_ODR_OFFSET U(0x14) 42 #define GPIO_BSRR_OFFSET U(0x18) 43 #define GPIO_AFRL_OFFSET U(0x20) 44 #define GPIO_AFRH_OFFSET U(0x24) 45 #define GPIO_SECR_OFFSET U(0x30) 46 47 #define GPIO_ALT_LOWER_LIMIT U(0x8) 48 49 #define GPIO_MODE_MASK GENMASK_32(1, 0) 50 #define GPIO_OSPEED_MASK GENMASK_32(1, 0) 51 #define GPIO_PUPD_PULL_MASK GENMASK_32(1, 0) 52 #define GPIO_ALTERNATE_MASK GENMASK_32(3, 0) 53 54 #define DT_GPIO_BANK_SHIFT U(12) 55 #define DT_GPIO_BANK_MASK GENMASK_32(16, 12) 56 #define DT_GPIO_PIN_SHIFT U(8) 57 #define DT_GPIO_PIN_MASK GENMASK_32(11, 8) 58 #define DT_GPIO_MODE_MASK GENMASK_32(7, 0) 59 60 #define DT_GPIO_BANK_NAME0 "GPIOA" 61 62 #define GPIO_MODE_INPUT U(0x0) 63 #define GPIO_MODE_OUTPUT U(0x1) 64 #define GPIO_MODE_ALTERNATE U(0x2) 65 #define GPIO_MODE_ANALOG U(0x3) 66 67 #define GPIO_OTYPE_PUSH_PULL U(0x0) 68 #define GPIO_OTYPE_OPEN_DRAIN U(0x1) 69 70 #define GPIO_OSPEED_LOW U(0x0) 71 #define GPIO_OSPEED_MEDIUM U(0x1) 72 #define GPIO_OSPEED_HIGH U(0x2) 73 #define GPIO_OSPEED_VERY_HIGH U(0x3) 74 75 #define GPIO_PUPD_NO_PULL U(0x0) 76 #define GPIO_PUPD_PULL_UP U(0x1) 77 #define GPIO_PUPD_PULL_DOWN U(0x2) 78 79 #define GPIO_OD_LEVEL_LOW U(0x0) 80 #define GPIO_OD_LEVEL_HIGH U(0x1) 81 82 /* 83 * GPIO configuration description structured as single 16bit word 84 * for efficient save/restore when GPIO pin suspends or resumes. 85 * 86 * @mode: One of GPIO_MODE_* 87 * @otype: One of GPIO_OTYPE_* 88 * @ospeed: One of GPIO_OSPEED_* 89 * @pupd: One of GPIO_PUPD_* 90 * @od: One of GPIO_OD_* 91 * @af: Alternate function numerical ID between 0 and 15 92 */ 93 struct gpio_cfg { 94 uint16_t mode: 2; 95 uint16_t otype: 1; 96 uint16_t ospeed: 2; 97 uint16_t pupd: 2; 98 uint16_t od: 1; 99 uint16_t af: 4; 100 }; 101 102 /* 103 * Description of a pin and its muxing 104 * 105 * @bank: GPIO bank identifier as assigned by the platform 106 * @pin: Pin number in the GPIO bank 107 * @cfg: Pin configuration 108 */ 109 struct stm32_pinctrl { 110 uint8_t bank; 111 uint8_t pin; 112 struct gpio_cfg cfg; 113 }; 114 115 /* 116 * struct stm32_pinctrl_array - Array of pins in a pin control state 117 * @count: Number of cells in @pinctrl 118 * @pinctrl: Pin control configuration 119 */ 120 struct stm32_pinctrl_array { 121 size_t count; 122 struct stm32_pinctrl pinctrl[]; 123 }; 124 125 /** 126 * struct stm32_gpio_bank - GPIO bank instance 127 * 128 * @base: base address of the GPIO controller registers. 129 * @clock: clock identifier. 130 * @gpio_chip: GPIO chip reference for that GPIO bank 131 * @ngpios: number of GPIOs. 132 * @bank_id: Id of the bank. 133 * @lock: lock protecting the GPIO bank access. 134 * @sec_support: True if bank supports pin security protection, otherwise false 135 * @link: Link in bank list 136 */ 137 struct stm32_gpio_bank { 138 vaddr_t base; 139 struct clk *clock; 140 struct gpio_chip gpio_chip; 141 unsigned int ngpios; 142 unsigned int bank_id; 143 unsigned int lock; 144 bool sec_support; 145 STAILQ_ENTRY(stm32_gpio_bank) link; 146 }; 147 148 /** 149 * Compatibility information of supported banks 150 * 151 * @gpioz: True if bank is a GPIOZ bank 152 * @secure_control: Identify GPIO security bank capability. 153 */ 154 struct bank_compat { 155 bool gpioz; 156 bool secure_control; 157 }; 158 159 static unsigned int gpio_lock; 160 161 static STAILQ_HEAD(, stm32_gpio_bank) bank_list = 162 STAILQ_HEAD_INITIALIZER(bank_list); 163 164 static bool is_stm32_gpio_chip(struct gpio_chip *chip); 165 166 static struct stm32_gpio_bank *gpio_chip_to_bank(struct gpio_chip *chip) 167 { 168 return container_of(chip, struct stm32_gpio_bank, gpio_chip); 169 } 170 171 static enum gpio_level stm32_gpio_get_level(struct gpio_chip *chip, 172 unsigned int gpio_pin) 173 { 174 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 175 enum gpio_level level = GPIO_LEVEL_HIGH; 176 unsigned int reg_offset = 0; 177 unsigned int mode = 0; 178 179 assert(gpio_pin < bank->ngpios); 180 181 if (clk_enable(bank->clock)) 182 panic(); 183 184 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 185 GPIO_MODE_MASK; 186 187 switch (mode) { 188 case GPIO_MODE_INPUT: 189 reg_offset = GPIO_IDR_OFFSET; 190 break; 191 case GPIO_MODE_OUTPUT: 192 reg_offset = GPIO_ODR_OFFSET; 193 break; 194 default: 195 panic(); 196 } 197 198 if (io_read32(bank->base + reg_offset) & BIT(gpio_pin)) 199 level = GPIO_LEVEL_HIGH; 200 else 201 level = GPIO_LEVEL_LOW; 202 203 clk_disable(bank->clock); 204 205 return level; 206 } 207 208 static void stm32_gpio_set_level(struct gpio_chip *chip, unsigned int gpio_pin, 209 enum gpio_level level) 210 { 211 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 212 213 assert(gpio_pin < bank->ngpios); 214 215 if (clk_enable(bank->clock)) 216 panic(); 217 218 assert(((io_read32(bank->base + GPIO_MODER_OFFSET) >> 219 (gpio_pin << 1)) & GPIO_MODE_MASK) == GPIO_MODE_OUTPUT); 220 221 if (level == GPIO_LEVEL_HIGH) 222 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin)); 223 else 224 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin + 16)); 225 226 clk_disable(bank->clock); 227 } 228 229 static enum gpio_dir stm32_gpio_get_direction(struct gpio_chip *chip, 230 unsigned int gpio_pin) 231 { 232 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 233 uint32_t mode = 0; 234 235 assert(gpio_pin < bank->ngpios); 236 237 if (clk_enable(bank->clock)) 238 panic(); 239 240 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 241 GPIO_MODE_MASK; 242 243 clk_disable(bank->clock); 244 245 switch (mode) { 246 case GPIO_MODE_INPUT: 247 return GPIO_DIR_IN; 248 case GPIO_MODE_OUTPUT: 249 return GPIO_DIR_OUT; 250 default: 251 panic(); 252 } 253 } 254 255 static void stm32_gpio_set_direction(struct gpio_chip *chip, 256 unsigned int gpio_pin, 257 enum gpio_dir direction) 258 { 259 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 260 uint32_t exceptions = 0; 261 uint32_t mode = 0; 262 263 assert(gpio_pin < bank->ngpios); 264 265 if (direction == GPIO_DIR_IN) 266 mode = GPIO_MODE_INPUT; 267 else 268 mode = GPIO_MODE_OUTPUT; 269 270 if (clk_enable(bank->clock)) 271 panic(); 272 exceptions = cpu_spin_lock_xsave(&gpio_lock); 273 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 274 SHIFT_U32(GPIO_MODE_MASK, gpio_pin << 1), 275 SHIFT_U32(mode, gpio_pin << 1)); 276 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 277 clk_disable(bank->clock); 278 } 279 280 static void stm32_gpio_put_gpio(struct gpio_chip *chip __maybe_unused, 281 struct gpio *gpio) 282 { 283 assert(is_stm32_gpio_chip(chip)); 284 free(gpio); 285 } 286 287 static const struct gpio_ops stm32_gpio_ops = { 288 .get_direction = stm32_gpio_get_direction, 289 .set_direction = stm32_gpio_set_direction, 290 .get_value = stm32_gpio_get_level, 291 .set_value = stm32_gpio_set_level, 292 .put = stm32_gpio_put_gpio, 293 }; 294 295 static bool __maybe_unused is_stm32_gpio_chip(struct gpio_chip *chip) 296 { 297 return chip && chip->ops == &stm32_gpio_ops; 298 } 299 300 static struct stm32_gpio_bank *stm32_gpio_get_bank(unsigned int bank_id) 301 { 302 struct stm32_gpio_bank *bank = NULL; 303 304 STAILQ_FOREACH(bank, &bank_list, link) 305 if (bank_id == bank->bank_id) 306 return bank; 307 308 panic(); 309 } 310 311 /* Save to output @cfg the current GPIO (@bank_id/@pin) configuration */ 312 static void __maybe_unused get_gpio_cfg(uint32_t bank_id, uint32_t pin, 313 struct gpio_cfg *cfg) 314 { 315 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 316 317 if (clk_enable(bank->clock)) 318 panic(); 319 320 /* 321 * Save GPIO configuration bits spread over the few bank registers. 322 * 1bit fields are accessed at bit position being the pin index. 323 * 2bit fields are accessed at bit position being twice the pin index. 324 * 4bit fields are accessed at bit position being fourth the pin index 325 * but accessed from 2 32bit registers at incremental addresses. 326 */ 327 cfg->mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (pin << 1)) & 328 GPIO_MODE_MASK; 329 330 cfg->otype = (io_read32(bank->base + GPIO_OTYPER_OFFSET) >> pin) & 1; 331 332 cfg->ospeed = (io_read32(bank->base + GPIO_OSPEEDR_OFFSET) >> 333 (pin << 1)) & GPIO_OSPEED_MASK; 334 335 cfg->pupd = (io_read32(bank->base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & 336 GPIO_PUPD_PULL_MASK; 337 338 cfg->od = (io_read32(bank->base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; 339 340 if (pin < GPIO_ALT_LOWER_LIMIT) 341 cfg->af = (io_read32(bank->base + GPIO_AFRL_OFFSET) >> 342 (pin << 2)) & GPIO_ALTERNATE_MASK; 343 else 344 cfg->af = (io_read32(bank->base + GPIO_AFRH_OFFSET) >> 345 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) & 346 GPIO_ALTERNATE_MASK; 347 348 clk_disable(bank->clock); 349 } 350 351 /* Apply GPIO (@bank/@pin) configuration described by @cfg */ 352 static void set_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 353 { 354 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 355 uint32_t exceptions = 0; 356 357 if (clk_enable(bank->clock)) 358 panic(); 359 exceptions = cpu_spin_lock_xsave(&gpio_lock); 360 361 /* Load GPIO MODE value, 2bit value shifted by twice the pin number */ 362 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 363 SHIFT_U32(GPIO_MODE_MASK, pin << 1), 364 SHIFT_U32(cfg->mode, pin << 1)); 365 366 /* Load GPIO Output TYPE value, 1bit shifted by pin number value */ 367 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, BIT(pin), 368 SHIFT_U32(cfg->otype, pin)); 369 370 /* Load GPIO Output Speed confguration, 2bit value */ 371 io_clrsetbits32(bank->base + GPIO_OSPEEDR_OFFSET, 372 SHIFT_U32(GPIO_OSPEED_MASK, pin << 1), 373 SHIFT_U32(cfg->ospeed, pin << 1)); 374 375 /* Load GPIO pull configuration, 2bit value */ 376 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, BIT(pin), 377 SHIFT_U32(cfg->pupd, pin << 1)); 378 379 /* Load pin mux Alternate Function configuration, 4bit value */ 380 if (pin < GPIO_ALT_LOWER_LIMIT) { 381 io_clrsetbits32(bank->base + GPIO_AFRL_OFFSET, 382 SHIFT_U32(GPIO_ALTERNATE_MASK, pin << 2), 383 SHIFT_U32(cfg->af, pin << 2)); 384 } else { 385 size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2; 386 387 io_clrsetbits32(bank->base + GPIO_AFRH_OFFSET, 388 SHIFT_U32(GPIO_ALTERNATE_MASK, shift), 389 SHIFT_U32(cfg->af, shift)); 390 } 391 392 /* Load GPIO Output direction confuguration, 1bit */ 393 io_clrsetbits32(bank->base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin); 394 395 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 396 clk_disable(bank->clock); 397 } 398 399 /* Count pins described in the DT node and get related data if possible */ 400 static int get_pinctrl_from_fdt(const void *fdt, int node, 401 struct stm32_pinctrl *pinctrl, size_t count) 402 { 403 const fdt32_t *cuint = NULL; 404 const fdt32_t *slewrate = NULL; 405 int len = 0; 406 uint32_t i = 0; 407 uint32_t speed = GPIO_OSPEED_LOW; 408 uint32_t pull = GPIO_PUPD_NO_PULL; 409 size_t found = 0; 410 411 cuint = fdt_getprop(fdt, node, "pinmux", &len); 412 if (!cuint) 413 return -FDT_ERR_NOTFOUND; 414 415 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); 416 if (slewrate) 417 speed = fdt32_to_cpu(*slewrate); 418 419 if (fdt_getprop(fdt, node, "bias-pull-up", NULL)) 420 pull = GPIO_PUPD_PULL_UP; 421 if (fdt_getprop(fdt, node, "bias-pull-down", NULL)) 422 pull = GPIO_PUPD_PULL_DOWN; 423 424 for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 425 uint32_t pincfg = 0; 426 uint32_t bank = 0; 427 uint32_t pin = 0; 428 uint32_t mode = 0; 429 uint32_t alternate = 0; 430 uint32_t odata = 0; 431 bool opendrain = false; 432 433 pincfg = fdt32_to_cpu(*cuint); 434 cuint++; 435 436 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; 437 438 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT; 439 440 mode = pincfg & DT_GPIO_MODE_MASK; 441 442 switch (mode) { 443 case 0: 444 mode = GPIO_MODE_INPUT; 445 break; 446 case 1: 447 case 2: 448 case 3: 449 case 4: 450 case 5: 451 case 6: 452 case 7: 453 case 8: 454 case 9: 455 case 10: 456 case 11: 457 case 12: 458 case 13: 459 case 14: 460 case 15: 461 case 16: 462 alternate = mode - 1U; 463 mode = GPIO_MODE_ALTERNATE; 464 break; 465 case 17: 466 mode = GPIO_MODE_ANALOG; 467 break; 468 default: 469 mode = GPIO_MODE_OUTPUT; 470 break; 471 } 472 473 if (fdt_getprop(fdt, node, "drive-open-drain", NULL)) 474 opendrain = true; 475 476 if (fdt_getprop(fdt, node, "output-high", NULL) && 477 mode == GPIO_MODE_INPUT) { 478 mode = GPIO_MODE_OUTPUT; 479 odata = 1; 480 } 481 482 if (fdt_getprop(fdt, node, "output-low", NULL) && 483 mode == GPIO_MODE_INPUT) { 484 mode = GPIO_MODE_OUTPUT; 485 odata = 0; 486 } 487 488 if (found < count) { 489 struct stm32_pinctrl *ref = &pinctrl[found]; 490 491 ref->bank = (uint8_t)bank; 492 ref->pin = (uint8_t)pin; 493 ref->cfg.mode = mode; 494 if (opendrain) 495 ref->cfg.otype = GPIO_OTYPE_OPEN_DRAIN; 496 else 497 ref->cfg.otype = GPIO_OTYPE_PUSH_PULL; 498 ref->cfg.ospeed = speed; 499 ref->cfg.pupd = pull; 500 ref->cfg.od = odata; 501 ref->cfg.af = alternate; 502 } 503 504 found++; 505 } 506 507 return (int)found; 508 } 509 510 static TEE_Result stm32_gpio_get_dt(struct dt_pargs *pargs, void *data, 511 struct gpio **out_gpio) 512 { 513 TEE_Result res = TEE_ERROR_GENERIC; 514 struct stm32_gpio_bank *bank = data; 515 struct gpio *gpio = NULL; 516 unsigned int shift_1b = 0; 517 unsigned int shift_2b = 0; 518 uint32_t exceptions = 0; 519 uint32_t otype = 0; 520 uint32_t pupd = 0; 521 uint32_t mode = 0; 522 523 res = gpio_dt_alloc_pin(pargs, &gpio); 524 if (res) 525 return res; 526 527 if (gpio->pin >= bank->ngpios) { 528 DMSG("Invalid GPIO reference"); 529 free(gpio); 530 return TEE_ERROR_GENERIC; 531 } 532 533 shift_1b = gpio->pin; 534 shift_2b = SHIFT_U32(gpio->pin, 1); 535 536 if (gpio->dt_flags & GPIO_PULL_UP) 537 pupd = GPIO_PUPD_PULL_UP; 538 else if (gpio->dt_flags & GPIO_PULL_DOWN) 539 pupd = GPIO_PUPD_PULL_DOWN; 540 else 541 pupd = GPIO_PUPD_NO_PULL; 542 543 if (gpio->dt_flags & GPIO_LINE_OPEN_DRAIN) 544 otype = GPIO_OTYPE_OPEN_DRAIN; 545 else 546 otype = GPIO_OTYPE_PUSH_PULL; 547 548 if (clk_enable(bank->clock)) 549 panic(); 550 exceptions = cpu_spin_lock_xsave(&gpio_lock); 551 552 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 553 SHIFT_U32(GPIO_MODE_MASK, shift_2b), 554 SHIFT_U32(mode, shift_2b)); 555 556 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, 557 SHIFT_U32(GPIO_OTYPE_OPEN_DRAIN, shift_1b), 558 SHIFT_U32(otype, shift_1b)); 559 560 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, 561 SHIFT_U32(GPIO_PUPD_PULL_MASK, shift_2b), 562 SHIFT_U32(pupd, shift_2b)); 563 564 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 565 clk_disable(bank->clock); 566 567 gpio->chip = &bank->gpio_chip; 568 569 *out_gpio = gpio; 570 571 return TEE_SUCCESS; 572 } 573 574 /* Get bank ID from bank node property st,bank-name or panic on failure */ 575 static unsigned int dt_get_bank_id(const void *fdt, int node) 576 { 577 const int dt_name_len = strlen(DT_GPIO_BANK_NAME0); 578 const fdt32_t *cuint = NULL; 579 int len = 0; 580 581 /* Parse "st,bank-name" to get its id (eg: GPIOA -> 0) */ 582 cuint = fdt_getprop(fdt, node, "st,bank-name", &len); 583 if (!cuint || (len != dt_name_len + 1)) 584 panic("Missing/wrong st,bank-name property"); 585 586 if (strncmp((const char *)cuint, DT_GPIO_BANK_NAME0, dt_name_len - 1) || 587 strcmp((const char *)cuint, DT_GPIO_BANK_NAME0) < 0) 588 panic("Wrong st,bank-name property"); 589 590 return (unsigned int)strcmp((const char *)cuint, DT_GPIO_BANK_NAME0); 591 } 592 593 /* 594 * Return whether or not the GPIO bank related to a DT node is already 595 * registered in the GPIO bank link. 596 */ 597 static bool bank_is_registered(const void *fdt, int node) 598 { 599 unsigned int bank_id = dt_get_bank_id(fdt, node); 600 struct stm32_gpio_bank *bank = NULL; 601 602 STAILQ_FOREACH(bank, &bank_list, link) 603 if (bank->bank_id == bank_id) 604 return true; 605 606 return false; 607 } 608 609 /* Get GPIO bank information from the DT */ 610 static TEE_Result dt_stm32_gpio_bank(const void *fdt, int node, 611 const void *compat_data, 612 int range_offset, 613 struct stm32_gpio_bank **out_bank) 614 { 615 const struct bank_compat *compat = compat_data; 616 TEE_Result res = TEE_ERROR_GENERIC; 617 struct stm32_gpio_bank *bank = NULL; 618 const fdt32_t *cuint = NULL; 619 struct io_pa_va pa_va = { }; 620 struct clk *clk = NULL; 621 size_t blen = 0; 622 paddr_t pa = 0; 623 int len = 0; 624 int i = 0; 625 626 assert(out_bank); 627 628 /* Probe deferrable devices first */ 629 res = clk_dt_get_by_index(fdt, node, 0, &clk); 630 if (res) 631 return res; 632 633 bank = calloc(1, sizeof(*bank)); 634 if (!bank) 635 return TEE_ERROR_OUT_OF_MEMORY; 636 637 /* 638 * Do not rely *only* on the "reg" property to get the address, 639 * but consider also the "ranges" translation property 640 */ 641 pa = fdt_reg_base_address(fdt, node); 642 if (pa == DT_INFO_INVALID_REG) 643 panic("missing reg property"); 644 645 pa_va.pa = pa + range_offset; 646 647 blen = fdt_reg_size(fdt, node); 648 if (blen == DT_INFO_INVALID_REG_SIZE) 649 panic("missing reg size property"); 650 651 DMSG("Bank name %s", fdt_get_name(fdt, node, NULL)); 652 bank->bank_id = dt_get_bank_id(fdt, node); 653 bank->clock = clk; 654 bank->gpio_chip.ops = &stm32_gpio_ops; 655 bank->sec_support = compat->secure_control; 656 if (bank->sec_support) 657 bank->base = io_pa_or_va_secure(&pa_va, blen); 658 else 659 bank->base = io_pa_or_va_nsec(&pa_va, blen); 660 assert(bank->base); 661 662 /* Parse gpio-ranges with its 4 parameters */ 663 cuint = fdt_getprop(fdt, node, "gpio-ranges", &len); 664 len /= sizeof(*cuint); 665 if (len % 4) 666 panic("wrong gpio-ranges syntax"); 667 668 /* Get the last defined gpio line (offset + nb of pins) */ 669 for (i = 0; i < len / 4; i++) { 670 bank->ngpios = MAX(bank->ngpios, 671 (unsigned int)(fdt32_to_cpu(*(cuint + 1)) + 672 fdt32_to_cpu(*(cuint + 3)))); 673 cuint += 4; 674 } 675 676 if (compat->gpioz) 677 stm32mp_register_gpioz_pin_count(bank->ngpios); 678 679 *out_bank = bank; 680 return TEE_SUCCESS; 681 } 682 683 static void set_bank_gpio_non_secure(struct stm32_gpio_bank *bank) 684 { 685 unsigned int pin = 0; 686 687 for (pin = 0; pin < bank->ngpios; pin++) 688 stm32_gpio_set_secure_cfg(bank->bank_id, pin, false); 689 } 690 691 /* Parse a pinctrl node to register and configure the GPIO banks it describes */ 692 static TEE_Result dt_stm32_gpio_pinctrl(const void *fdt, int node, 693 const void *compat_data) 694 { 695 TEE_Result res = TEE_SUCCESS; 696 const fdt32_t *cuint = NULL; 697 int range_offs = 0; 698 int b_node = 0; 699 int len = 0; 700 701 /* Read the ranges property (for regs memory translation) */ 702 cuint = fdt_getprop(fdt, node, "ranges", &len); 703 if (!cuint) 704 panic("missing ranges property"); 705 706 len /= sizeof(*cuint); 707 if (len == 3) 708 range_offs = fdt32_to_cpu(*(cuint + 1)) - fdt32_to_cpu(*cuint); 709 710 fdt_for_each_subnode(b_node, fdt, node) { 711 cuint = fdt_getprop(fdt, b_node, "gpio-controller", &len); 712 if (cuint) { 713 /* 714 * We found a property "gpio-controller" in the node: 715 * the node is a GPIO bank description, add it to the 716 * bank list. 717 */ 718 struct stm32_gpio_bank *bank = NULL; 719 720 if (fdt_get_status(fdt, b_node) == DT_STATUS_DISABLED || 721 bank_is_registered(fdt, b_node)) 722 continue; 723 724 res = dt_stm32_gpio_bank(fdt, b_node, compat_data, 725 range_offs, &bank); 726 if (res) 727 return res; 728 729 /* Registering a provider should not defer probe */ 730 res = gpio_register_provider(fdt, b_node, 731 stm32_gpio_get_dt, bank); 732 if (res) 733 panic(); 734 735 STAILQ_INSERT_TAIL(&bank_list, bank, link); 736 737 DMSG("Registered GPIO bank %c (%d pins) @%#"PRIxVA, 738 bank->bank_id + 'A', bank->ngpios, bank->base); 739 740 assert(bank->ngpios <= GPIO_PIN_MAX + 1); 741 742 if (bank->sec_support) { 743 uint32_t seccfgr = 0; 744 unsigned int i = 0; 745 int lenp = 0; 746 747 cuint = fdt_getprop(fdt, b_node, "st,protreg", 748 &lenp); 749 if (!cuint) { 750 set_bank_gpio_non_secure(bank); 751 continue; 752 } 753 754 seccfgr = fdt32_to_cpu(*cuint); 755 for (i = 0; i < bank->ngpios; i++) 756 stm32_gpio_set_secure_cfg(bank->bank_id, 757 i, 758 seccfgr & 759 TZPROT(i)); 760 } 761 } else { 762 if (len != -FDT_ERR_NOTFOUND) 763 panic(); 764 } 765 } 766 767 return TEE_SUCCESS; 768 } 769 770 void stm32_gpio_set_secure_cfg(unsigned int bank_id, unsigned int pin, 771 bool secure) 772 { 773 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 774 uint32_t exceptions = 0; 775 776 if (clk_enable(bank->clock)) 777 panic(); 778 exceptions = cpu_spin_lock_xsave(&gpio_lock); 779 780 if (secure) 781 io_setbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 782 else 783 io_clrbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 784 785 FMSG("Set secure GPIO: bank %c pin %u", bank->bank_id + 'A', pin); 786 787 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 788 clk_disable(bank->clock); 789 } 790 791 #ifdef CFG_DRIVERS_PINCTRL 792 static TEE_Result stm32_pinctrl_conf_apply(struct pinconf *conf) 793 { 794 struct stm32_pinctrl_array *ref = conf->priv; 795 struct stm32_pinctrl *p = ref->pinctrl; 796 size_t pin_count = ref->count; 797 size_t n = 0; 798 799 for (n = 0; n < pin_count; n++) 800 set_gpio_cfg(p[n].bank, p[n].pin, &p[n].cfg); 801 802 return TEE_SUCCESS; 803 } 804 805 static void stm32_pinctrl_conf_free(struct pinconf *conf) 806 { 807 free(conf); 808 } 809 810 static const struct pinctrl_ops stm32_pinctrl_ops = { 811 .conf_apply = stm32_pinctrl_conf_apply, 812 .conf_free = stm32_pinctrl_conf_free, 813 }; 814 815 DECLARE_KEEP_PAGER(stm32_pinctrl_ops); 816 817 void stm32_gpio_pinctrl_bank_pin(struct pinctrl_state *pinctrl, 818 unsigned int *bank, unsigned int *pin, 819 unsigned int *count) 820 { 821 size_t conf_index = 0; 822 size_t pin_count = 0; 823 size_t n = 0; 824 825 assert(count); 826 if (!pinctrl) 827 goto out; 828 829 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 830 struct pinconf *pinconf = pinctrl->confs[conf_index]; 831 struct stm32_pinctrl_array *ref = pinconf->priv; 832 833 /* Consider only the stm32_gpio pins */ 834 if (pinconf->ops != &stm32_pinctrl_ops) 835 continue; 836 837 if (bank || pin) { 838 for (n = 0; n < ref->count; n++) { 839 if (bank && pin_count < *count) 840 bank[pin_count] = ref->pinctrl[n].bank; 841 if (pin && pin_count < *count) 842 pin[pin_count] = ref->pinctrl[n].pin; 843 pin_count++; 844 } 845 } else { 846 pin_count += ref->count; 847 } 848 } 849 850 out: 851 *count = pin_count; 852 } 853 854 void stm32_pinctrl_set_secure_cfg(struct pinctrl_state *pinctrl, bool secure) 855 { 856 size_t conf_index = 0; 857 858 if (!pinctrl) 859 return; 860 861 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 862 struct pinconf *pinconf = pinctrl->confs[conf_index]; 863 struct stm32_pinctrl_array *ref = pinconf->priv; 864 struct stm32_pinctrl *pc = NULL; 865 size_t n = 0; 866 867 for (n = 0; n < ref->count; n++) { 868 if (pinconf->ops != &stm32_pinctrl_ops) 869 continue; 870 871 pc = ref->pinctrl + n; 872 stm32_gpio_set_secure_cfg(pc->bank, pc->pin, secure); 873 } 874 } 875 } 876 877 /* Allocate and return a pinctrl configuration from a DT reference */ 878 static TEE_Result stm32_pinctrl_dt_get(struct dt_pargs *pargs, 879 void *data __unused, 880 struct pinconf **out_pinconf) 881 { 882 struct conf { 883 struct pinconf pinconf; 884 struct stm32_pinctrl_array array_ref; 885 } *loc_conf = NULL; 886 struct stm32_pinctrl *pinctrl = NULL; 887 struct pinconf *pinconf = NULL; 888 const void *fdt = NULL; 889 size_t pin_count = 0; 890 int pinctrl_node = 0; 891 int pinmux_node = 0; 892 int count = 0; 893 894 pinctrl_node = pargs->phandle_node; 895 fdt = pargs->fdt; 896 assert(fdt && pinctrl_node); 897 898 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 899 if (fdt_getprop(fdt, pinmux_node, "pinmux", &count)) 900 pin_count += (size_t)count / sizeof(uint32_t); 901 else if (count != -FDT_ERR_NOTFOUND) 902 panic(); 903 } 904 905 loc_conf = calloc(1, sizeof(*loc_conf) + sizeof(*pinctrl) * pin_count); 906 if (!loc_conf) 907 return TEE_ERROR_OUT_OF_MEMORY; 908 909 pinconf = &loc_conf->pinconf; 910 pinconf->ops = &stm32_pinctrl_ops; 911 pinconf->priv = &loc_conf->array_ref; 912 913 loc_conf->array_ref.count = pin_count; 914 pinctrl = loc_conf->array_ref.pinctrl; 915 916 count = 0; 917 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 918 int found = 0; 919 920 found = get_pinctrl_from_fdt(fdt, pinmux_node, pinctrl + count, 921 pin_count - count); 922 if (found <= 0 && found > ((int)pin_count - count)) { 923 /* We can't recover from an error here so let's panic */ 924 panic(); 925 } 926 927 count += found; 928 } 929 930 *out_pinconf = pinconf; 931 932 return TEE_SUCCESS; 933 } 934 #endif /*CFG_DRIVERS_PINCTRL*/ 935 936 static TEE_Result stm32_pinctrl_probe(const void *fdt, int node, 937 const void *compat_data) 938 { 939 TEE_Result res = TEE_ERROR_GENERIC; 940 941 /* Register GPIO banks described in this pin control node */ 942 res = dt_stm32_gpio_pinctrl(fdt, node, compat_data); 943 if (res) 944 return res; 945 946 #ifdef CFG_DRIVERS_PINCTRL 947 res = pinctrl_register_provider(fdt, node, stm32_pinctrl_dt_get, 948 (void *)compat_data); 949 if (res) 950 return res; 951 #endif 952 953 return TEE_SUCCESS; 954 } 955 956 static const struct dt_device_match stm32_pinctrl_match_table[] = { 957 { 958 .compatible = "st,stm32mp135-pinctrl", 959 .compat_data = &(struct bank_compat){ 960 .secure_control = true, 961 }, 962 }, 963 { 964 .compatible = "st,stm32mp157-pinctrl", 965 .compat_data = &(struct bank_compat){ 966 .secure_control = false, 967 }, 968 }, 969 { 970 .compatible = "st,stm32mp157-z-pinctrl", 971 .compat_data = &(struct bank_compat){ 972 .gpioz = true, 973 .secure_control = true, 974 }, 975 }, 976 { } 977 }; 978 979 DEFINE_DT_DRIVER(stm32_pinctrl_dt_driver) = { 980 .name = "stm32_gpio-pinctrl", 981 .type = DT_DRIVER_PINCTRL, 982 .match_table = stm32_pinctrl_match_table, 983 .probe = stm32_pinctrl_probe, 984 }; 985