1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2023, STMicroelectronics 4 * 5 * STM32 GPIO driver is used as pin controller for stm32mp SoCs. 6 */ 7 8 #include <assert.h> 9 #include <compiler.h> 10 #include <drivers/clk.h> 11 #include <drivers/clk_dt.h> 12 #include <drivers/gpio.h> 13 #include <drivers/pinctrl.h> 14 #include <drivers/stm32_gpio.h> 15 #include <io.h> 16 #include <kernel/dt.h> 17 #include <kernel/boot.h> 18 #include <kernel/panic.h> 19 #include <kernel/spinlock.h> 20 #include <libfdt.h> 21 #include <mm/core_memprot.h> 22 #include <stdbool.h> 23 #include <stdint.h> 24 #include <stm32_util.h> 25 #include <sys/queue.h> 26 #include <trace.h> 27 #include <util.h> 28 29 #ifndef CFG_DRIVERS_GPIO 30 #error stm32_gpio driver expects CFG_DRIVERS_GPIO 31 #endif 32 33 #define GPIO_PIN_MAX 15 34 35 #define GPIO_MODER_OFFSET 0x00 36 #define GPIO_OTYPER_OFFSET 0x04 37 #define GPIO_OSPEEDR_OFFSET 0x08 38 #define GPIO_PUPDR_OFFSET 0x0c 39 #define GPIO_IDR_OFFSET 0x10 40 #define GPIO_ODR_OFFSET 0x14 41 #define GPIO_BSRR_OFFSET 0x18 42 #define GPIO_AFRL_OFFSET 0x20 43 #define GPIO_AFRH_OFFSET 0x24 44 #define GPIO_SECR_OFFSET 0x30 45 46 #define GPIO_ALT_LOWER_LIMIT 0x8 47 48 #define GPIO_MODE_MASK GENMASK_32(1, 0) 49 #define GPIO_OSPEED_MASK GENMASK_32(1, 0) 50 #define GPIO_PUPD_PULL_MASK GENMASK_32(1, 0) 51 #define GPIO_ALTERNATE_MASK GENMASK_32(3, 0) 52 53 #define DT_GPIO_BANK_SHIFT 12 54 #define DT_GPIO_BANK_MASK GENMASK_32(16, 12) 55 #define DT_GPIO_PIN_SHIFT 8 56 #define DT_GPIO_PIN_MASK GENMASK_32(11, 8) 57 #define DT_GPIO_MODE_MASK GENMASK_32(7, 0) 58 59 #define DT_GPIO_BANK_NAME0 "GPIOA" 60 61 #define GPIO_MODE_INPUT U(0x0) 62 #define GPIO_MODE_OUTPUT U(0x1) 63 #define GPIO_MODE_ALTERNATE U(0x2) 64 #define GPIO_MODE_ANALOG U(0x3) 65 66 #define GPIO_OTYPE_PUSH_PULL U(0x0) 67 #define GPIO_OTYPE_OPEN_DRAIN U(0x1) 68 69 #define GPIO_OSPEED_LOW U(0x0) 70 #define GPIO_OSPEED_MEDIUM U(0x1) 71 #define GPIO_OSPEED_HIGH U(0x2) 72 #define GPIO_OSPEED_VERY_HIGH U(0x3) 73 74 #define GPIO_PUPD_NO_PULL U(0x0) 75 #define GPIO_PUPD_PULL_UP U(0x1) 76 #define GPIO_PUPD_PULL_DOWN U(0x2) 77 78 #define GPIO_OD_LEVEL_LOW U(0x0) 79 #define GPIO_OD_LEVEL_HIGH U(0x1) 80 81 /* 82 * GPIO configuration description structured as single 16bit word 83 * for efficient save/restore when GPIO pin suspends or resumes. 84 * 85 * @mode: One of GPIO_MODE_* 86 * @otype: One of GPIO_OTYPE_* 87 * @ospeed: One of GPIO_OSPEED_* 88 * @pupd: One of GPIO_PUPD_* 89 * @od: One of GPIO_OD_* 90 * @af: Alternate function numerical ID between 0 and 15 91 */ 92 struct gpio_cfg { 93 uint16_t mode: 2; 94 uint16_t otype: 1; 95 uint16_t ospeed: 2; 96 uint16_t pupd: 2; 97 uint16_t od: 1; 98 uint16_t af: 4; 99 }; 100 101 /* 102 * Description of a pin and its muxing 103 * 104 * @bank: GPIO bank identifier as assigned by the platform 105 * @pin: Pin number in the GPIO bank 106 * @cfg: Pin configuration 107 */ 108 struct stm32_pinctrl { 109 uint8_t bank; 110 uint8_t pin; 111 struct gpio_cfg cfg; 112 }; 113 114 /* 115 * struct stm32_pinctrl_array - Array of pins in a pin control state 116 * @count: Number of cells in @pinctrl 117 * @pinctrl: Pin control configuration 118 */ 119 struct stm32_pinctrl_array { 120 size_t count; 121 struct stm32_pinctrl pinctrl[]; 122 }; 123 124 /** 125 * struct stm32_gpio_bank - GPIO bank instance 126 * 127 * @base: base address of the GPIO controller registers. 128 * @clock: clock identifier. 129 * @gpio_chip: GPIO chip reference for that GPIO bank 130 * @ngpios: number of GPIOs. 131 * @bank_id: Id of the bank. 132 * @lock: lock protecting the GPIO bank access. 133 * @sec_support: True if bank supports pin security protection, otherwise false 134 * @seccfgr: Secure configuration register value. 135 * @link: Link in bank list 136 */ 137 struct stm32_gpio_bank { 138 vaddr_t base; 139 struct clk *clock; 140 struct gpio_chip gpio_chip; 141 unsigned int ngpios; 142 unsigned int bank_id; 143 unsigned int lock; 144 STAILQ_ENTRY(stm32_gpio_bank) link; 145 }; 146 147 /* 148 * Compatibility information of supported banks 149 * @gpioz True if bank is a GPIOZ bank 150 */ 151 struct bank_compat { 152 bool gpioz; 153 }; 154 155 static unsigned int gpio_lock; 156 157 static STAILQ_HEAD(, stm32_gpio_bank) bank_list = 158 STAILQ_HEAD_INITIALIZER(bank_list); 159 160 static bool is_stm32_gpio_chip(struct gpio_chip *chip); 161 162 static struct stm32_gpio_bank *gpio_chip_to_bank(struct gpio_chip *chip) 163 { 164 return container_of(chip, struct stm32_gpio_bank, gpio_chip); 165 } 166 167 static enum gpio_level stm32_gpio_get_level(struct gpio_chip *chip, 168 unsigned int gpio_pin) 169 { 170 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 171 enum gpio_level level = GPIO_LEVEL_HIGH; 172 unsigned int reg_offset = 0; 173 unsigned int mode = 0; 174 175 assert(gpio_pin < bank->ngpios); 176 177 if (clk_enable(bank->clock)) 178 panic(); 179 180 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 181 GPIO_MODE_MASK; 182 183 switch (mode) { 184 case GPIO_MODE_INPUT: 185 reg_offset = GPIO_IDR_OFFSET; 186 break; 187 case GPIO_MODE_OUTPUT: 188 reg_offset = GPIO_ODR_OFFSET; 189 break; 190 default: 191 panic(); 192 } 193 194 if (io_read32(bank->base + reg_offset) & BIT(gpio_pin)) 195 level = GPIO_LEVEL_HIGH; 196 else 197 level = GPIO_LEVEL_LOW; 198 199 clk_disable(bank->clock); 200 201 return level; 202 } 203 204 static void stm32_gpio_set_level(struct gpio_chip *chip, unsigned int gpio_pin, 205 enum gpio_level level) 206 { 207 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 208 209 assert(gpio_pin < bank->ngpios); 210 211 if (clk_enable(bank->clock)) 212 panic(); 213 214 assert(((io_read32(bank->base + GPIO_MODER_OFFSET) >> 215 (gpio_pin << 1)) & GPIO_MODE_MASK) == GPIO_MODE_OUTPUT); 216 217 if (level == GPIO_LEVEL_HIGH) 218 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin)); 219 else 220 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin + 16)); 221 222 clk_disable(bank->clock); 223 } 224 225 static enum gpio_dir stm32_gpio_get_direction(struct gpio_chip *chip, 226 unsigned int gpio_pin) 227 { 228 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 229 uint32_t mode = 0; 230 231 assert(gpio_pin < bank->ngpios); 232 233 if (clk_enable(bank->clock)) 234 panic(); 235 236 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 237 GPIO_MODE_MASK; 238 239 clk_disable(bank->clock); 240 241 switch (mode) { 242 case GPIO_MODE_INPUT: 243 return GPIO_DIR_IN; 244 case GPIO_MODE_OUTPUT: 245 return GPIO_DIR_OUT; 246 default: 247 panic(); 248 } 249 } 250 251 static void stm32_gpio_set_direction(struct gpio_chip *chip, 252 unsigned int gpio_pin, 253 enum gpio_dir direction) 254 { 255 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 256 uint32_t exceptions = 0; 257 uint32_t mode = 0; 258 259 assert(gpio_pin < bank->ngpios); 260 261 if (direction == GPIO_DIR_IN) 262 mode = GPIO_MODE_INPUT; 263 else 264 mode = GPIO_MODE_OUTPUT; 265 266 if (clk_enable(bank->clock)) 267 panic(); 268 exceptions = cpu_spin_lock_xsave(&gpio_lock); 269 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 270 SHIFT_U32(GPIO_MODE_MASK, gpio_pin << 1), 271 SHIFT_U32(mode, gpio_pin << 1)); 272 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 273 clk_disable(bank->clock); 274 } 275 276 static void stm32_gpio_put_gpio(struct gpio_chip *chip __maybe_unused, 277 struct gpio *gpio) 278 { 279 assert(is_stm32_gpio_chip(chip)); 280 free(gpio); 281 } 282 283 static const struct gpio_ops stm32_gpio_ops = { 284 .get_direction = stm32_gpio_get_direction, 285 .set_direction = stm32_gpio_set_direction, 286 .get_value = stm32_gpio_get_level, 287 .set_value = stm32_gpio_set_level, 288 .put = stm32_gpio_put_gpio, 289 }; 290 291 static bool __maybe_unused is_stm32_gpio_chip(struct gpio_chip *chip) 292 { 293 return chip && chip->ops == &stm32_gpio_ops; 294 } 295 296 static struct stm32_gpio_bank *stm32_gpio_get_bank(unsigned int bank_id) 297 { 298 struct stm32_gpio_bank *bank = NULL; 299 300 STAILQ_FOREACH(bank, &bank_list, link) 301 if (bank_id == bank->bank_id) 302 return bank; 303 304 panic(); 305 } 306 307 /* Save to output @cfg the current GPIO (@bank_id/@pin) configuration */ 308 static void __maybe_unused get_gpio_cfg(uint32_t bank_id, uint32_t pin, 309 struct gpio_cfg *cfg) 310 { 311 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 312 313 if (clk_enable(bank->clock)) 314 panic(); 315 316 /* 317 * Save GPIO configuration bits spread over the few bank registers. 318 * 1bit fields are accessed at bit position being the pin index. 319 * 2bit fields are accessed at bit position being twice the pin index. 320 * 4bit fields are accessed at bit position being fourth the pin index 321 * but accessed from 2 32bit registers at incremental addresses. 322 */ 323 cfg->mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (pin << 1)) & 324 GPIO_MODE_MASK; 325 326 cfg->otype = (io_read32(bank->base + GPIO_OTYPER_OFFSET) >> pin) & 1; 327 328 cfg->ospeed = (io_read32(bank->base + GPIO_OSPEEDR_OFFSET) >> 329 (pin << 1)) & GPIO_OSPEED_MASK; 330 331 cfg->pupd = (io_read32(bank->base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & 332 GPIO_PUPD_PULL_MASK; 333 334 cfg->od = (io_read32(bank->base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; 335 336 if (pin < GPIO_ALT_LOWER_LIMIT) 337 cfg->af = (io_read32(bank->base + GPIO_AFRL_OFFSET) >> 338 (pin << 2)) & GPIO_ALTERNATE_MASK; 339 else 340 cfg->af = (io_read32(bank->base + GPIO_AFRH_OFFSET) >> 341 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) & 342 GPIO_ALTERNATE_MASK; 343 344 clk_disable(bank->clock); 345 } 346 347 /* Apply GPIO (@bank/@pin) configuration described by @cfg */ 348 static void set_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 349 { 350 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 351 uint32_t exceptions = 0; 352 353 if (clk_enable(bank->clock)) 354 panic(); 355 exceptions = cpu_spin_lock_xsave(&gpio_lock); 356 357 /* Load GPIO MODE value, 2bit value shifted by twice the pin number */ 358 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 359 SHIFT_U32(GPIO_MODE_MASK, pin << 1), 360 SHIFT_U32(cfg->mode, pin << 1)); 361 362 /* Load GPIO Output TYPE value, 1bit shifted by pin number value */ 363 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, BIT(pin), 364 SHIFT_U32(cfg->otype, pin)); 365 366 /* Load GPIO Output Speed confguration, 2bit value */ 367 io_clrsetbits32(bank->base + GPIO_OSPEEDR_OFFSET, 368 SHIFT_U32(GPIO_OSPEED_MASK, pin << 1), 369 SHIFT_U32(cfg->ospeed, pin << 1)); 370 371 /* Load GPIO pull configuration, 2bit value */ 372 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, BIT(pin), 373 SHIFT_U32(cfg->pupd, pin << 1)); 374 375 /* Load pin mux Alternate Function configuration, 4bit value */ 376 if (pin < GPIO_ALT_LOWER_LIMIT) { 377 io_clrsetbits32(bank->base + GPIO_AFRL_OFFSET, 378 SHIFT_U32(GPIO_ALTERNATE_MASK, pin << 2), 379 SHIFT_U32(cfg->af, pin << 2)); 380 } else { 381 size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2; 382 383 io_clrsetbits32(bank->base + GPIO_AFRH_OFFSET, 384 SHIFT_U32(GPIO_ALTERNATE_MASK, shift), 385 SHIFT_U32(cfg->af, shift)); 386 } 387 388 /* Load GPIO Output direction confuguration, 1bit */ 389 io_clrsetbits32(bank->base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin); 390 391 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 392 clk_disable(bank->clock); 393 } 394 395 /* Count pins described in the DT node and get related data if possible */ 396 static int get_pinctrl_from_fdt(const void *fdt, int node, 397 struct stm32_pinctrl *pinctrl, size_t count) 398 { 399 const fdt32_t *cuint = NULL; 400 const fdt32_t *slewrate = NULL; 401 int len = 0; 402 uint32_t i = 0; 403 uint32_t speed = GPIO_OSPEED_LOW; 404 uint32_t pull = GPIO_PUPD_NO_PULL; 405 size_t found = 0; 406 407 cuint = fdt_getprop(fdt, node, "pinmux", &len); 408 if (!cuint) 409 return -FDT_ERR_NOTFOUND; 410 411 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); 412 if (slewrate) 413 speed = fdt32_to_cpu(*slewrate); 414 415 if (fdt_getprop(fdt, node, "bias-pull-up", NULL)) 416 pull = GPIO_PUPD_PULL_UP; 417 if (fdt_getprop(fdt, node, "bias-pull-down", NULL)) 418 pull = GPIO_PUPD_PULL_DOWN; 419 420 for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 421 uint32_t pincfg = 0; 422 uint32_t bank = 0; 423 uint32_t pin = 0; 424 uint32_t mode = 0; 425 uint32_t alternate = 0; 426 uint32_t odata = 0; 427 bool opendrain = false; 428 429 pincfg = fdt32_to_cpu(*cuint); 430 cuint++; 431 432 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; 433 434 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT; 435 436 mode = pincfg & DT_GPIO_MODE_MASK; 437 438 switch (mode) { 439 case 0: 440 mode = GPIO_MODE_INPUT; 441 break; 442 case 1: 443 case 2: 444 case 3: 445 case 4: 446 case 5: 447 case 6: 448 case 7: 449 case 8: 450 case 9: 451 case 10: 452 case 11: 453 case 12: 454 case 13: 455 case 14: 456 case 15: 457 case 16: 458 alternate = mode - 1U; 459 mode = GPIO_MODE_ALTERNATE; 460 break; 461 case 17: 462 mode = GPIO_MODE_ANALOG; 463 break; 464 default: 465 mode = GPIO_MODE_OUTPUT; 466 break; 467 } 468 469 if (fdt_getprop(fdt, node, "drive-open-drain", NULL)) 470 opendrain = true; 471 472 if (fdt_getprop(fdt, node, "output-high", NULL) && 473 mode == GPIO_MODE_INPUT) { 474 mode = GPIO_MODE_OUTPUT; 475 odata = 1; 476 } 477 478 if (fdt_getprop(fdt, node, "output-low", NULL) && 479 mode == GPIO_MODE_INPUT) { 480 mode = GPIO_MODE_OUTPUT; 481 odata = 0; 482 } 483 484 if (found < count) { 485 struct stm32_pinctrl *ref = &pinctrl[found]; 486 487 ref->bank = (uint8_t)bank; 488 ref->pin = (uint8_t)pin; 489 ref->cfg.mode = mode; 490 if (opendrain) 491 ref->cfg.otype = GPIO_OTYPE_OPEN_DRAIN; 492 else 493 ref->cfg.otype = GPIO_OTYPE_PUSH_PULL; 494 ref->cfg.ospeed = speed; 495 ref->cfg.pupd = pull; 496 ref->cfg.od = odata; 497 ref->cfg.af = alternate; 498 } 499 500 found++; 501 } 502 503 return (int)found; 504 } 505 506 static TEE_Result stm32_gpio_get_dt(struct dt_pargs *pargs, void *data, 507 struct gpio **out_gpio) 508 { 509 TEE_Result res = TEE_ERROR_GENERIC; 510 struct stm32_gpio_bank *bank = data; 511 struct gpio *gpio = NULL; 512 unsigned int shift_1b = 0; 513 unsigned int shift_2b = 0; 514 uint32_t exceptions = 0; 515 uint32_t otype = 0; 516 uint32_t pupd = 0; 517 uint32_t mode = 0; 518 519 res = gpio_dt_alloc_pin(pargs, &gpio); 520 if (res) 521 return res; 522 523 if (gpio->pin >= bank->ngpios) { 524 DMSG("Invalid GPIO reference"); 525 free(gpio); 526 return TEE_ERROR_GENERIC; 527 } 528 529 shift_1b = gpio->pin; 530 shift_2b = SHIFT_U32(gpio->pin, 1); 531 532 if (gpio->dt_flags & GPIO_PULL_UP) 533 pupd = GPIO_PUPD_PULL_UP; 534 else if (gpio->dt_flags & GPIO_PULL_DOWN) 535 pupd = GPIO_PUPD_PULL_DOWN; 536 else 537 pupd = GPIO_PUPD_NO_PULL; 538 539 if (gpio->dt_flags & GPIO_LINE_OPEN_DRAIN) 540 otype = GPIO_OTYPE_OPEN_DRAIN; 541 else 542 otype = GPIO_OTYPE_PUSH_PULL; 543 544 if (clk_enable(bank->clock)) 545 panic(); 546 exceptions = cpu_spin_lock_xsave(&gpio_lock); 547 548 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 549 SHIFT_U32(GPIO_MODE_MASK, shift_2b), 550 SHIFT_U32(mode, shift_2b)); 551 552 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, 553 SHIFT_U32(GPIO_OTYPE_OPEN_DRAIN, shift_1b), 554 SHIFT_U32(otype, shift_1b)); 555 556 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, 557 SHIFT_U32(GPIO_PUPD_PULL_MASK, shift_2b), 558 SHIFT_U32(pupd, shift_2b)); 559 560 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 561 clk_disable(bank->clock); 562 563 gpio->chip = &bank->gpio_chip; 564 565 *out_gpio = gpio; 566 567 return TEE_SUCCESS; 568 } 569 570 /* Get bank ID from bank node property st,bank-name or panic on failure */ 571 static unsigned int dt_get_bank_id(const void *fdt, int node) 572 { 573 const int dt_name_len = strlen(DT_GPIO_BANK_NAME0); 574 const fdt32_t *cuint = NULL; 575 int len = 0; 576 577 /* Parse "st,bank-name" to get its id (eg: GPIOA -> 0) */ 578 cuint = fdt_getprop(fdt, node, "st,bank-name", &len); 579 if (!cuint || (len != dt_name_len + 1)) 580 panic("Missing/wrong st,bank-name property"); 581 582 if (strncmp((const char *)cuint, DT_GPIO_BANK_NAME0, dt_name_len - 1) || 583 strcmp((const char *)cuint, DT_GPIO_BANK_NAME0) < 0) 584 panic("Wrong st,bank-name property"); 585 586 return (unsigned int)strcmp((const char *)cuint, DT_GPIO_BANK_NAME0); 587 } 588 589 /* 590 * Return whether or not the GPIO bank related to a DT node is already 591 * registered in the GPIO bank link. 592 */ 593 static bool bank_is_registered(const void *fdt, int node) 594 { 595 unsigned int bank_id = dt_get_bank_id(fdt, node); 596 struct stm32_gpio_bank *bank = NULL; 597 598 STAILQ_FOREACH(bank, &bank_list, link) 599 if (bank->bank_id == bank_id) 600 return true; 601 602 return false; 603 } 604 605 /* Get GPIO bank information from the DT */ 606 static TEE_Result dt_stm32_gpio_bank(const void *fdt, int node, 607 const void *compat_data, 608 int range_offset, 609 struct stm32_gpio_bank **out_bank) 610 { 611 const struct bank_compat *compat = compat_data; 612 TEE_Result res = TEE_ERROR_GENERIC; 613 struct stm32_gpio_bank *bank = NULL; 614 const fdt32_t *cuint = NULL; 615 struct io_pa_va pa_va = { }; 616 struct clk *clk = NULL; 617 size_t blen = 0; 618 paddr_t pa = 0; 619 int len = 0; 620 int i = 0; 621 622 assert(out_bank); 623 624 /* Probe deferrable devices first */ 625 res = clk_dt_get_by_index(fdt, node, 0, &clk); 626 if (res) 627 return res; 628 629 bank = calloc(1, sizeof(*bank)); 630 if (!bank) 631 return TEE_ERROR_OUT_OF_MEMORY; 632 633 /* 634 * Do not rely *only* on the "reg" property to get the address, 635 * but consider also the "ranges" translation property 636 */ 637 pa = fdt_reg_base_address(fdt, node); 638 if (pa == DT_INFO_INVALID_REG) 639 panic("missing reg property"); 640 641 pa_va.pa = pa + range_offset; 642 643 blen = fdt_reg_size(fdt, node); 644 if (blen == DT_INFO_INVALID_REG_SIZE) 645 panic("missing reg size property"); 646 647 DMSG("Bank name %s", fdt_get_name(fdt, node, NULL)); 648 bank->base = io_pa_or_va_secure(&pa_va, blen); 649 bank->bank_id = dt_get_bank_id(fdt, node); 650 bank->clock = clk; 651 bank->gpio_chip.ops = &stm32_gpio_ops; 652 653 /* Parse gpio-ranges with its 4 parameters */ 654 cuint = fdt_getprop(fdt, node, "gpio-ranges", &len); 655 len /= sizeof(*cuint); 656 if (len % 4) 657 panic("wrong gpio-ranges syntax"); 658 659 /* Get the last defined gpio line (offset + nb of pins) */ 660 for (i = 0; i < len / 4; i++) { 661 bank->ngpios = MAX(bank->ngpios, 662 (unsigned int)(fdt32_to_cpu(*(cuint + 1)) + 663 fdt32_to_cpu(*(cuint + 3)))); 664 cuint += 4; 665 } 666 667 if (compat->gpioz) 668 stm32mp_register_gpioz_pin_count(bank->ngpios); 669 670 *out_bank = bank; 671 return TEE_SUCCESS; 672 } 673 674 static void set_bank_gpio_non_secure(struct stm32_gpio_bank *bank) 675 { 676 unsigned int pin = 0; 677 678 for (pin = 0; pin <= bank->ngpios; pin++) 679 stm32_gpio_set_secure_cfg(bank->bank_id, pin, false); 680 } 681 682 /* Parse a pinctrl node to register the GPIO banks it describes */ 683 static TEE_Result dt_stm32_gpio_pinctrl(const void *fdt, int node, 684 const void *compat_data) 685 { 686 TEE_Result res = TEE_SUCCESS; 687 const fdt32_t *cuint = NULL; 688 int range_offs = 0; 689 int b_node = 0; 690 int len = 0; 691 692 /* Read the ranges property (for regs memory translation) */ 693 cuint = fdt_getprop(fdt, node, "ranges", &len); 694 if (!cuint) 695 panic("missing ranges property"); 696 697 len /= sizeof(*cuint); 698 if (len == 3) 699 range_offs = fdt32_to_cpu(*(cuint + 1)) - fdt32_to_cpu(*cuint); 700 701 fdt_for_each_subnode(b_node, fdt, node) { 702 cuint = fdt_getprop(fdt, b_node, "gpio-controller", &len); 703 if (cuint) { 704 /* 705 * We found a property "gpio-controller" in the node: 706 * the node is a GPIO bank description, add it to the 707 * bank list. 708 */ 709 struct stm32_gpio_bank *bank = NULL; 710 711 if (fdt_get_status(fdt, b_node) == DT_STATUS_DISABLED || 712 bank_is_registered(fdt, b_node)) 713 continue; 714 715 res = dt_stm32_gpio_bank(fdt, b_node, compat_data, 716 range_offs, &bank); 717 if (res) 718 return res; 719 720 /* Registering a provider should not defer probe */ 721 res = gpio_register_provider(fdt, b_node, 722 stm32_gpio_get_dt, bank); 723 if (res) 724 panic(); 725 726 STAILQ_INSERT_TAIL(&bank_list, bank, link); 727 728 if (IS_ENABLED(CFG_STM32MP13)) 729 set_bank_gpio_non_secure(bank); 730 } else { 731 if (len != -FDT_ERR_NOTFOUND) 732 panic(); 733 } 734 } 735 736 return TEE_SUCCESS; 737 } 738 739 740 int stm32_get_gpio_count(void *fdt, int pinctrl_node, unsigned int bank) 741 { 742 int node = 0; 743 const fdt32_t *cuint = NULL; 744 745 fdt_for_each_subnode(node, fdt, pinctrl_node) { 746 if (!fdt_getprop(fdt, node, "gpio-controller", NULL)) 747 continue; 748 749 cuint = fdt_getprop(fdt, node, "reg", NULL); 750 if (!cuint) 751 continue; 752 753 if (fdt32_to_cpu(*cuint) != stm32_get_gpio_bank_offset(bank)) 754 continue; 755 756 cuint = fdt_getprop(fdt, node, "ngpios", NULL); 757 if (!cuint) 758 panic(); 759 760 return (int)fdt32_to_cpu(*cuint); 761 } 762 763 return -1; 764 } 765 766 void stm32_gpio_set_secure_cfg(unsigned int bank_id, unsigned int pin, 767 bool secure) 768 { 769 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 770 uint32_t exceptions = 0; 771 772 if (clk_enable(bank->clock)) 773 panic(); 774 exceptions = cpu_spin_lock_xsave(&gpio_lock); 775 776 if (secure) 777 io_setbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 778 else 779 io_clrbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 780 781 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 782 clk_disable(bank->clock); 783 } 784 785 #ifdef CFG_DRIVERS_PINCTRL 786 static TEE_Result stm32_pinctrl_conf_apply(struct pinconf *conf) 787 { 788 struct stm32_pinctrl_array *ref = conf->priv; 789 struct stm32_pinctrl *p = ref->pinctrl; 790 size_t pin_count = ref->count; 791 size_t n = 0; 792 793 for (n = 0; n < pin_count; n++) 794 set_gpio_cfg(p[n].bank, p[n].pin, &p[n].cfg); 795 796 return TEE_SUCCESS; 797 } 798 799 static void stm32_pinctrl_conf_free(struct pinconf *conf) 800 { 801 free(conf); 802 } 803 804 static const struct pinctrl_ops stm32_pinctrl_ops = { 805 .conf_apply = stm32_pinctrl_conf_apply, 806 .conf_free = stm32_pinctrl_conf_free, 807 }; 808 809 DECLARE_KEEP_PAGER(stm32_pinctrl_ops); 810 811 void stm32_gpio_pinctrl_bank_pin(struct pinctrl_state *pinctrl, 812 unsigned int *bank, unsigned int *pin, 813 unsigned int *count) 814 { 815 size_t conf_index = 0; 816 size_t pin_count = 0; 817 size_t n = 0; 818 819 assert(count); 820 if (!pinctrl) 821 goto out; 822 823 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 824 struct pinconf *pinconf = pinctrl->confs[conf_index]; 825 struct stm32_pinctrl_array *ref = pinconf->priv; 826 827 /* Consider only the stm32_gpio pins */ 828 if (pinconf->ops != &stm32_pinctrl_ops) 829 continue; 830 831 if (bank || pin) { 832 for (n = 0; n < ref->count; n++) { 833 if (bank && pin_count < *count) 834 bank[pin_count] = ref->pinctrl[n].bank; 835 if (pin && pin_count < *count) 836 pin[pin_count] = ref->pinctrl[n].pin; 837 pin_count++; 838 } 839 } else { 840 pin_count += ref->count; 841 } 842 } 843 844 out: 845 *count = pin_count; 846 } 847 848 void stm32_pinctrl_set_secure_cfg(struct pinctrl_state *pinctrl, bool secure) 849 { 850 size_t conf_index = 0; 851 852 if (!pinctrl) 853 return; 854 855 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 856 struct pinconf *pinconf = pinctrl->confs[conf_index]; 857 struct stm32_pinctrl_array *ref = pinconf->priv; 858 struct stm32_pinctrl *pc = NULL; 859 size_t n = 0; 860 861 for (n = 0; n < ref->count; n++) { 862 if (pinconf->ops != &stm32_pinctrl_ops) 863 continue; 864 865 pc = ref->pinctrl + n; 866 stm32_gpio_set_secure_cfg(pc->bank, pc->pin, secure); 867 } 868 } 869 } 870 871 /* Allocate and return a pinctrl configuration from a DT reference */ 872 static TEE_Result stm32_pinctrl_dt_get(struct dt_pargs *pargs, 873 void *data __unused, 874 struct pinconf **out_pinconf) 875 { 876 struct conf { 877 struct pinconf pinconf; 878 struct stm32_pinctrl_array array_ref; 879 } *loc_conf = NULL; 880 struct stm32_pinctrl *pinctrl = NULL; 881 struct pinconf *pinconf = NULL; 882 const void *fdt = NULL; 883 size_t pin_count = 0; 884 int pinctrl_node = 0; 885 int pinmux_node = 0; 886 int count = 0; 887 888 pinctrl_node = pargs->phandle_node; 889 fdt = pargs->fdt; 890 assert(fdt && pinctrl_node); 891 892 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 893 if (fdt_getprop(fdt, pinmux_node, "pinmux", &count)) 894 pin_count += (size_t)count / sizeof(uint32_t); 895 else if (count != -FDT_ERR_NOTFOUND) 896 panic(); 897 } 898 899 loc_conf = calloc(1, sizeof(*loc_conf) + sizeof(*pinctrl) * pin_count); 900 if (!loc_conf) 901 return TEE_ERROR_OUT_OF_MEMORY; 902 903 pinconf = &loc_conf->pinconf; 904 pinconf->ops = &stm32_pinctrl_ops; 905 pinconf->priv = &loc_conf->array_ref; 906 907 loc_conf->array_ref.count = pin_count; 908 pinctrl = loc_conf->array_ref.pinctrl; 909 910 count = 0; 911 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 912 int found = 0; 913 914 found = get_pinctrl_from_fdt(fdt, pinmux_node, pinctrl + count, 915 pin_count - count); 916 if (found <= 0 && found > ((int)pin_count - count)) { 917 /* We can't recover from an error here so let's panic */ 918 panic(); 919 } 920 921 count += found; 922 } 923 924 *out_pinconf = pinconf; 925 926 return TEE_SUCCESS; 927 } 928 #endif /*CFG_DRIVERS_PINCTRL*/ 929 930 static TEE_Result stm32_pinctrl_probe(const void *fdt, int node, 931 const void *compat_data) 932 { 933 TEE_Result res = TEE_ERROR_GENERIC; 934 935 /* Register GPIO banks described in this pin control node */ 936 res = dt_stm32_gpio_pinctrl(fdt, node, compat_data); 937 if (res) 938 return res; 939 940 #ifdef CFG_DRIVERS_PINCTRL 941 res = pinctrl_register_provider(fdt, node, stm32_pinctrl_dt_get, 942 (void *)compat_data); 943 if (res) 944 return res; 945 #endif 946 947 return TEE_SUCCESS; 948 } 949 950 static const struct dt_device_match stm32_pinctrl_match_table[] = { 951 { 952 .compatible = "st,stm32mp135-pinctrl", 953 .compat_data = &(struct bank_compat){ }, 954 955 }, 956 { 957 .compatible = "st,stm32mp157-pinctrl", 958 .compat_data = &(struct bank_compat){ }, 959 }, 960 { 961 .compatible = "st,stm32mp157-z-pinctrl", 962 .compat_data = &(struct bank_compat){ .gpioz = true, }, 963 }, 964 { } 965 }; 966 967 DEFINE_DT_DRIVER(stm32_pinctrl_dt_driver) = { 968 .name = "stm32_gpio-pinctrl", 969 .type = DT_DRIVER_PINCTRL, 970 .match_table = stm32_pinctrl_match_table, 971 .probe = stm32_pinctrl_probe, 972 }; 973