1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2023, STMicroelectronics 4 * 5 * STM32 GPIO driver is used as pin controller for stm32mp SoCs. 6 */ 7 8 #include <assert.h> 9 #include <compiler.h> 10 #include <drivers/clk.h> 11 #include <drivers/clk_dt.h> 12 #include <drivers/gpio.h> 13 #include <drivers/pinctrl.h> 14 #include <drivers/stm32_gpio.h> 15 #include <io.h> 16 #include <kernel/dt.h> 17 #include <kernel/boot.h> 18 #include <kernel/panic.h> 19 #include <kernel/spinlock.h> 20 #include <libfdt.h> 21 #include <mm/core_memprot.h> 22 #include <stdbool.h> 23 #include <stdint.h> 24 #include <stm32_util.h> 25 #include <sys/queue.h> 26 #include <trace.h> 27 #include <util.h> 28 29 #ifndef CFG_DRIVERS_GPIO 30 #error stm32_gpio driver expects CFG_DRIVERS_GPIO 31 #endif 32 33 #define GPIO_PIN_MAX 15 34 35 #define GPIO_MODER_OFFSET 0x00 36 #define GPIO_OTYPER_OFFSET 0x04 37 #define GPIO_OSPEEDR_OFFSET 0x08 38 #define GPIO_PUPDR_OFFSET 0x0c 39 #define GPIO_IDR_OFFSET 0x10 40 #define GPIO_ODR_OFFSET 0x14 41 #define GPIO_BSRR_OFFSET 0x18 42 #define GPIO_AFRL_OFFSET 0x20 43 #define GPIO_AFRH_OFFSET 0x24 44 #define GPIO_SECR_OFFSET 0x30 45 46 #define GPIO_ALT_LOWER_LIMIT 0x8 47 48 #define GPIO_MODE_MASK GENMASK_32(1, 0) 49 #define GPIO_OSPEED_MASK GENMASK_32(1, 0) 50 #define GPIO_PUPD_PULL_MASK GENMASK_32(1, 0) 51 #define GPIO_ALTERNATE_MASK GENMASK_32(3, 0) 52 53 #define DT_GPIO_BANK_SHIFT 12 54 #define DT_GPIO_BANK_MASK GENMASK_32(16, 12) 55 #define DT_GPIO_PIN_SHIFT 8 56 #define DT_GPIO_PIN_MASK GENMASK_32(11, 8) 57 #define DT_GPIO_MODE_MASK GENMASK_32(7, 0) 58 59 #define DT_GPIO_BANK_NAME0 "GPIOA" 60 61 #define GPIO_MODE_INPUT U(0x0) 62 #define GPIO_MODE_OUTPUT U(0x1) 63 #define GPIO_MODE_ALTERNATE U(0x2) 64 #define GPIO_MODE_ANALOG U(0x3) 65 66 #define GPIO_OTYPE_PUSH_PULL U(0x0) 67 #define GPIO_OTYPE_OPEN_DRAIN U(0x1) 68 69 #define GPIO_OSPEED_LOW U(0x0) 70 #define GPIO_OSPEED_MEDIUM U(0x1) 71 #define GPIO_OSPEED_HIGH U(0x2) 72 #define GPIO_OSPEED_VERY_HIGH U(0x3) 73 74 #define GPIO_PUPD_NO_PULL U(0x0) 75 #define GPIO_PUPD_PULL_UP U(0x1) 76 #define GPIO_PUPD_PULL_DOWN U(0x2) 77 78 #define GPIO_OD_LEVEL_LOW U(0x0) 79 #define GPIO_OD_LEVEL_HIGH U(0x1) 80 81 /* 82 * GPIO configuration description structured as single 16bit word 83 * for efficient save/restore when GPIO pin suspends or resumes. 84 * 85 * @mode: One of GPIO_MODE_* 86 * @otype: One of GPIO_OTYPE_* 87 * @ospeed: One of GPIO_OSPEED_* 88 * @pupd: One of GPIO_PUPD_* 89 * @od: One of GPIO_OD_* 90 * @af: Alternate function numerical ID between 0 and 15 91 */ 92 struct gpio_cfg { 93 uint16_t mode: 2; 94 uint16_t otype: 1; 95 uint16_t ospeed: 2; 96 uint16_t pupd: 2; 97 uint16_t od: 1; 98 uint16_t af: 4; 99 }; 100 101 /* 102 * Description of a pin and its muxing 103 * 104 * @bank: GPIO bank identifier as assigned by the platform 105 * @pin: Pin number in the GPIO bank 106 * @cfg: Pin configuration 107 */ 108 struct stm32_pinctrl { 109 uint8_t bank; 110 uint8_t pin; 111 struct gpio_cfg cfg; 112 }; 113 114 /* 115 * struct stm32_pinctrl_array - Array of pins in a pin control state 116 * @count: Number of cells in @pinctrl 117 * @pinctrl: Pin control configuration 118 */ 119 struct stm32_pinctrl_array { 120 size_t count; 121 struct stm32_pinctrl pinctrl[]; 122 }; 123 124 /** 125 * struct stm32_gpio_bank - GPIO bank instance 126 * 127 * @base: base address of the GPIO controller registers. 128 * @clock: clock identifier. 129 * @gpio_chip: GPIO chip reference for that GPIO bank 130 * @ngpios: number of GPIOs. 131 * @bank_id: Id of the bank. 132 * @lock: lock protecting the GPIO bank access. 133 * @sec_support: True if bank supports pin security protection, otherwise false 134 * @seccfgr: Secure configuration register value. 135 * @link: Link in bank list 136 */ 137 struct stm32_gpio_bank { 138 vaddr_t base; 139 struct clk *clock; 140 struct gpio_chip gpio_chip; 141 unsigned int ngpios; 142 unsigned int bank_id; 143 unsigned int lock; 144 STAILQ_ENTRY(stm32_gpio_bank) link; 145 }; 146 147 static unsigned int gpio_lock; 148 149 static STAILQ_HEAD(, stm32_gpio_bank) bank_list = 150 STAILQ_HEAD_INITIALIZER(bank_list); 151 152 static bool is_stm32_gpio_chip(struct gpio_chip *chip); 153 154 static struct stm32_gpio_bank *gpio_chip_to_bank(struct gpio_chip *chip) 155 { 156 return container_of(chip, struct stm32_gpio_bank, gpio_chip); 157 } 158 159 static enum gpio_level stm32_gpio_get_level(struct gpio_chip *chip, 160 unsigned int gpio_pin) 161 { 162 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 163 enum gpio_level level = GPIO_LEVEL_HIGH; 164 unsigned int reg_offset = 0; 165 unsigned int mode = 0; 166 167 assert(gpio_pin < bank->ngpios); 168 169 if (clk_enable(bank->clock)) 170 panic(); 171 172 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 173 GPIO_MODE_MASK; 174 175 switch (mode) { 176 case GPIO_MODE_INPUT: 177 reg_offset = GPIO_IDR_OFFSET; 178 break; 179 case GPIO_MODE_OUTPUT: 180 reg_offset = GPIO_ODR_OFFSET; 181 break; 182 default: 183 panic(); 184 } 185 186 if (io_read32(bank->base + reg_offset) & BIT(gpio_pin)) 187 level = GPIO_LEVEL_HIGH; 188 else 189 level = GPIO_LEVEL_LOW; 190 191 clk_disable(bank->clock); 192 193 return level; 194 } 195 196 static void stm32_gpio_set_level(struct gpio_chip *chip, unsigned int gpio_pin, 197 enum gpio_level level) 198 { 199 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 200 201 assert(gpio_pin < bank->ngpios); 202 203 if (clk_enable(bank->clock)) 204 panic(); 205 206 assert(((io_read32(bank->base + GPIO_MODER_OFFSET) >> 207 (gpio_pin << 1)) & GPIO_MODE_MASK) == GPIO_MODE_OUTPUT); 208 209 if (level == GPIO_LEVEL_HIGH) 210 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin)); 211 else 212 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin + 16)); 213 214 clk_disable(bank->clock); 215 } 216 217 static enum gpio_dir stm32_gpio_get_direction(struct gpio_chip *chip, 218 unsigned int gpio_pin) 219 { 220 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 221 uint32_t mode = 0; 222 223 assert(gpio_pin < bank->ngpios); 224 225 if (clk_enable(bank->clock)) 226 panic(); 227 228 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 229 GPIO_MODE_MASK; 230 231 clk_disable(bank->clock); 232 233 switch (mode) { 234 case GPIO_MODE_INPUT: 235 return GPIO_DIR_IN; 236 case GPIO_MODE_OUTPUT: 237 return GPIO_DIR_OUT; 238 default: 239 panic(); 240 } 241 } 242 243 static void stm32_gpio_set_direction(struct gpio_chip *chip, 244 unsigned int gpio_pin, 245 enum gpio_dir direction) 246 { 247 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 248 uint32_t exceptions = 0; 249 uint32_t mode = 0; 250 251 assert(gpio_pin < bank->ngpios); 252 253 if (direction == GPIO_DIR_IN) 254 mode = GPIO_MODE_INPUT; 255 else 256 mode = GPIO_MODE_OUTPUT; 257 258 if (clk_enable(bank->clock)) 259 panic(); 260 exceptions = cpu_spin_lock_xsave(&gpio_lock); 261 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 262 SHIFT_U32(GPIO_MODE_MASK, gpio_pin << 1), 263 SHIFT_U32(mode, gpio_pin << 1)); 264 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 265 clk_disable(bank->clock); 266 } 267 268 static void stm32_gpio_put_gpio(struct gpio_chip *chip __maybe_unused, 269 struct gpio *gpio) 270 { 271 assert(is_stm32_gpio_chip(chip)); 272 free(gpio); 273 } 274 275 static const struct gpio_ops stm32_gpio_ops = { 276 .get_direction = stm32_gpio_get_direction, 277 .set_direction = stm32_gpio_set_direction, 278 .get_value = stm32_gpio_get_level, 279 .set_value = stm32_gpio_set_level, 280 .put = stm32_gpio_put_gpio, 281 }; 282 283 static bool __maybe_unused is_stm32_gpio_chip(struct gpio_chip *chip) 284 { 285 return chip && chip->ops == &stm32_gpio_ops; 286 } 287 288 static struct stm32_gpio_bank *stm32_gpio_get_bank(unsigned int bank_id) 289 { 290 struct stm32_gpio_bank *bank = NULL; 291 292 STAILQ_FOREACH(bank, &bank_list, link) 293 if (bank_id == bank->bank_id) 294 return bank; 295 296 panic(); 297 } 298 299 /* Save to output @cfg the current GPIO (@bank_id/@pin) configuration */ 300 static void __maybe_unused get_gpio_cfg(uint32_t bank_id, uint32_t pin, 301 struct gpio_cfg *cfg) 302 { 303 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 304 305 if (clk_enable(bank->clock)) 306 panic(); 307 308 /* 309 * Save GPIO configuration bits spread over the few bank registers. 310 * 1bit fields are accessed at bit position being the pin index. 311 * 2bit fields are accessed at bit position being twice the pin index. 312 * 4bit fields are accessed at bit position being fourth the pin index 313 * but accessed from 2 32bit registers at incremental addresses. 314 */ 315 cfg->mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (pin << 1)) & 316 GPIO_MODE_MASK; 317 318 cfg->otype = (io_read32(bank->base + GPIO_OTYPER_OFFSET) >> pin) & 1; 319 320 cfg->ospeed = (io_read32(bank->base + GPIO_OSPEEDR_OFFSET) >> 321 (pin << 1)) & GPIO_OSPEED_MASK; 322 323 cfg->pupd = (io_read32(bank->base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & 324 GPIO_PUPD_PULL_MASK; 325 326 cfg->od = (io_read32(bank->base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; 327 328 if (pin < GPIO_ALT_LOWER_LIMIT) 329 cfg->af = (io_read32(bank->base + GPIO_AFRL_OFFSET) >> 330 (pin << 2)) & GPIO_ALTERNATE_MASK; 331 else 332 cfg->af = (io_read32(bank->base + GPIO_AFRH_OFFSET) >> 333 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) & 334 GPIO_ALTERNATE_MASK; 335 336 clk_disable(bank->clock); 337 } 338 339 /* Apply GPIO (@bank/@pin) configuration described by @cfg */ 340 static void set_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 341 { 342 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 343 uint32_t exceptions = 0; 344 345 if (clk_enable(bank->clock)) 346 panic(); 347 exceptions = cpu_spin_lock_xsave(&gpio_lock); 348 349 /* Load GPIO MODE value, 2bit value shifted by twice the pin number */ 350 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 351 SHIFT_U32(GPIO_MODE_MASK, pin << 1), 352 SHIFT_U32(cfg->mode, pin << 1)); 353 354 /* Load GPIO Output TYPE value, 1bit shifted by pin number value */ 355 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, BIT(pin), 356 SHIFT_U32(cfg->otype, pin)); 357 358 /* Load GPIO Output Speed confguration, 2bit value */ 359 io_clrsetbits32(bank->base + GPIO_OSPEEDR_OFFSET, 360 SHIFT_U32(GPIO_OSPEED_MASK, pin << 1), 361 SHIFT_U32(cfg->ospeed, pin << 1)); 362 363 /* Load GPIO pull configuration, 2bit value */ 364 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, BIT(pin), 365 SHIFT_U32(cfg->pupd, pin << 1)); 366 367 /* Load pin mux Alternate Function configuration, 4bit value */ 368 if (pin < GPIO_ALT_LOWER_LIMIT) { 369 io_clrsetbits32(bank->base + GPIO_AFRL_OFFSET, 370 SHIFT_U32(GPIO_ALTERNATE_MASK, pin << 2), 371 SHIFT_U32(cfg->af, pin << 2)); 372 } else { 373 size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2; 374 375 io_clrsetbits32(bank->base + GPIO_AFRH_OFFSET, 376 SHIFT_U32(GPIO_ALTERNATE_MASK, shift), 377 SHIFT_U32(cfg->af, shift)); 378 } 379 380 /* Load GPIO Output direction confuguration, 1bit */ 381 io_clrsetbits32(bank->base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin); 382 383 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 384 clk_disable(bank->clock); 385 } 386 387 /* Count pins described in the DT node and get related data if possible */ 388 static int get_pinctrl_from_fdt(const void *fdt, int node, 389 struct stm32_pinctrl *pinctrl, size_t count) 390 { 391 const fdt32_t *cuint = NULL; 392 const fdt32_t *slewrate = NULL; 393 int len = 0; 394 uint32_t i = 0; 395 uint32_t speed = GPIO_OSPEED_LOW; 396 uint32_t pull = GPIO_PUPD_NO_PULL; 397 size_t found = 0; 398 399 cuint = fdt_getprop(fdt, node, "pinmux", &len); 400 if (!cuint) 401 return -FDT_ERR_NOTFOUND; 402 403 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); 404 if (slewrate) 405 speed = fdt32_to_cpu(*slewrate); 406 407 if (fdt_getprop(fdt, node, "bias-pull-up", NULL)) 408 pull = GPIO_PUPD_PULL_UP; 409 if (fdt_getprop(fdt, node, "bias-pull-down", NULL)) 410 pull = GPIO_PUPD_PULL_DOWN; 411 412 for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 413 uint32_t pincfg = 0; 414 uint32_t bank = 0; 415 uint32_t pin = 0; 416 uint32_t mode = 0; 417 uint32_t alternate = 0; 418 uint32_t odata = 0; 419 bool opendrain = false; 420 421 pincfg = fdt32_to_cpu(*cuint); 422 cuint++; 423 424 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; 425 426 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT; 427 428 mode = pincfg & DT_GPIO_MODE_MASK; 429 430 switch (mode) { 431 case 0: 432 mode = GPIO_MODE_INPUT; 433 break; 434 case 1: 435 case 2: 436 case 3: 437 case 4: 438 case 5: 439 case 6: 440 case 7: 441 case 8: 442 case 9: 443 case 10: 444 case 11: 445 case 12: 446 case 13: 447 case 14: 448 case 15: 449 case 16: 450 alternate = mode - 1U; 451 mode = GPIO_MODE_ALTERNATE; 452 break; 453 case 17: 454 mode = GPIO_MODE_ANALOG; 455 break; 456 default: 457 mode = GPIO_MODE_OUTPUT; 458 break; 459 } 460 461 if (fdt_getprop(fdt, node, "drive-open-drain", NULL)) 462 opendrain = true; 463 464 if (fdt_getprop(fdt, node, "output-high", NULL) && 465 mode == GPIO_MODE_INPUT) { 466 mode = GPIO_MODE_OUTPUT; 467 odata = 1; 468 } 469 470 if (fdt_getprop(fdt, node, "output-low", NULL) && 471 mode == GPIO_MODE_INPUT) { 472 mode = GPIO_MODE_OUTPUT; 473 odata = 0; 474 } 475 476 if (found < count) { 477 struct stm32_pinctrl *ref = &pinctrl[found]; 478 479 ref->bank = (uint8_t)bank; 480 ref->pin = (uint8_t)pin; 481 ref->cfg.mode = mode; 482 if (opendrain) 483 ref->cfg.otype = GPIO_OTYPE_OPEN_DRAIN; 484 else 485 ref->cfg.otype = GPIO_OTYPE_PUSH_PULL; 486 ref->cfg.ospeed = speed; 487 ref->cfg.pupd = pull; 488 ref->cfg.od = odata; 489 ref->cfg.af = alternate; 490 } 491 492 found++; 493 } 494 495 return (int)found; 496 } 497 498 static TEE_Result stm32_gpio_get_dt(struct dt_pargs *pargs, void *data, 499 struct gpio **out_gpio) 500 { 501 TEE_Result res = TEE_ERROR_GENERIC; 502 struct stm32_gpio_bank *bank = data; 503 struct gpio *gpio = NULL; 504 unsigned int shift_1b = 0; 505 unsigned int shift_2b = 0; 506 uint32_t exceptions = 0; 507 uint32_t otype = 0; 508 uint32_t pupd = 0; 509 uint32_t mode = 0; 510 511 res = gpio_dt_alloc_pin(pargs, &gpio); 512 if (res) 513 return res; 514 515 if (gpio->pin >= bank->ngpios) { 516 DMSG("Invalid GPIO reference"); 517 free(gpio); 518 return TEE_ERROR_GENERIC; 519 } 520 521 shift_1b = gpio->pin; 522 shift_2b = SHIFT_U32(gpio->pin, 1); 523 524 if (gpio->dt_flags & GPIO_PULL_UP) 525 pupd = GPIO_PUPD_PULL_UP; 526 else if (gpio->dt_flags & GPIO_PULL_DOWN) 527 pupd = GPIO_PUPD_PULL_DOWN; 528 else 529 pupd = GPIO_PUPD_NO_PULL; 530 531 if (gpio->dt_flags & GPIO_LINE_OPEN_DRAIN) 532 otype = GPIO_OTYPE_OPEN_DRAIN; 533 else 534 otype = GPIO_OTYPE_PUSH_PULL; 535 536 if (clk_enable(bank->clock)) 537 panic(); 538 exceptions = cpu_spin_lock_xsave(&gpio_lock); 539 540 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 541 SHIFT_U32(GPIO_MODE_MASK, shift_2b), 542 SHIFT_U32(mode, shift_2b)); 543 544 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, 545 SHIFT_U32(GPIO_OTYPE_OPEN_DRAIN, shift_1b), 546 SHIFT_U32(otype, shift_1b)); 547 548 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, 549 SHIFT_U32(GPIO_PUPD_PULL_MASK, shift_2b), 550 SHIFT_U32(pupd, shift_2b)); 551 552 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 553 clk_disable(bank->clock); 554 555 gpio->chip = &bank->gpio_chip; 556 557 *out_gpio = gpio; 558 559 return TEE_SUCCESS; 560 } 561 562 /* Get bank ID from bank node property st,bank-name or panic on failure */ 563 static unsigned int dt_get_bank_id(const void *fdt, int node) 564 { 565 const int dt_name_len = strlen(DT_GPIO_BANK_NAME0); 566 const fdt32_t *cuint = NULL; 567 int len = 0; 568 569 /* Parse "st,bank-name" to get its id (eg: GPIOA -> 0) */ 570 cuint = fdt_getprop(fdt, node, "st,bank-name", &len); 571 if (!cuint || (len != dt_name_len + 1)) 572 panic("Missing/wrong st,bank-name property"); 573 574 if (strncmp((const char *)cuint, DT_GPIO_BANK_NAME0, dt_name_len - 1) || 575 strcmp((const char *)cuint, DT_GPIO_BANK_NAME0) < 0) 576 panic("Wrong st,bank-name property"); 577 578 return (unsigned int)strcmp((const char *)cuint, DT_GPIO_BANK_NAME0); 579 } 580 581 /* 582 * Return whether or not the GPIO bank related to a DT node is already 583 * registered in the GPIO bank link. 584 */ 585 static bool bank_is_registered(const void *fdt, int node) 586 { 587 unsigned int bank_id = dt_get_bank_id(fdt, node); 588 struct stm32_gpio_bank *bank = NULL; 589 590 STAILQ_FOREACH(bank, &bank_list, link) 591 if (bank->bank_id == bank_id) 592 return true; 593 594 return false; 595 } 596 597 /* Get GPIO bank information from the DT */ 598 static TEE_Result dt_stm32_gpio_bank(const void *fdt, int node, 599 const void *compat_data __unused, 600 int range_offset, 601 struct stm32_gpio_bank **out_bank) 602 { 603 TEE_Result res = TEE_ERROR_GENERIC; 604 struct stm32_gpio_bank *bank = NULL; 605 const fdt32_t *cuint = NULL; 606 struct io_pa_va pa_va = { }; 607 struct clk *clk = NULL; 608 size_t blen = 0; 609 paddr_t pa = 0; 610 int len = 0; 611 int i = 0; 612 613 assert(out_bank); 614 615 /* Probe deferrable devices first */ 616 res = clk_dt_get_by_index(fdt, node, 0, &clk); 617 if (res) 618 return res; 619 620 bank = calloc(1, sizeof(*bank)); 621 if (!bank) 622 return TEE_ERROR_OUT_OF_MEMORY; 623 624 /* 625 * Do not rely *only* on the "reg" property to get the address, 626 * but consider also the "ranges" translation property 627 */ 628 pa = fdt_reg_base_address(fdt, node); 629 if (pa == DT_INFO_INVALID_REG) 630 panic("missing reg property"); 631 632 pa_va.pa = pa + range_offset; 633 634 blen = fdt_reg_size(fdt, node); 635 if (blen == DT_INFO_INVALID_REG_SIZE) 636 panic("missing reg size property"); 637 638 DMSG("Bank name %s", fdt_get_name(fdt, node, NULL)); 639 bank->base = io_pa_or_va_secure(&pa_va, blen); 640 bank->bank_id = dt_get_bank_id(fdt, node); 641 bank->clock = clk; 642 bank->gpio_chip.ops = &stm32_gpio_ops; 643 644 /* Parse gpio-ranges with its 4 parameters */ 645 cuint = fdt_getprop(fdt, node, "gpio-ranges", &len); 646 len /= sizeof(*cuint); 647 if (len % 4) 648 panic("wrong gpio-ranges syntax"); 649 650 /* Get the last defined gpio line (offset + nb of pins) */ 651 for (i = 0; i < len / 4; i++) { 652 bank->ngpios = MAX(bank->ngpios, 653 (unsigned int)(fdt32_to_cpu(*(cuint + 1)) + 654 fdt32_to_cpu(*(cuint + 3)))); 655 cuint += 4; 656 } 657 658 *out_bank = bank; 659 return TEE_SUCCESS; 660 } 661 662 static void set_bank_gpio_non_secure(struct stm32_gpio_bank *bank) 663 { 664 unsigned int pin = 0; 665 666 for (pin = 0; pin <= bank->ngpios; pin++) 667 stm32_gpio_set_secure_cfg(bank->bank_id, pin, false); 668 } 669 670 /* Parse a pinctrl node to register the GPIO banks it describes */ 671 static TEE_Result dt_stm32_gpio_pinctrl(const void *fdt, int node, 672 const void *compat_data) 673 { 674 TEE_Result res = TEE_SUCCESS; 675 const fdt32_t *cuint = NULL; 676 int range_offs = 0; 677 int b_node = 0; 678 int len = 0; 679 680 /* Read the ranges property (for regs memory translation) */ 681 cuint = fdt_getprop(fdt, node, "ranges", &len); 682 if (!cuint) 683 panic("missing ranges property"); 684 685 len /= sizeof(*cuint); 686 if (len == 3) 687 range_offs = fdt32_to_cpu(*(cuint + 1)) - fdt32_to_cpu(*cuint); 688 689 fdt_for_each_subnode(b_node, fdt, node) { 690 cuint = fdt_getprop(fdt, b_node, "gpio-controller", &len); 691 if (cuint) { 692 /* 693 * We found a property "gpio-controller" in the node: 694 * the node is a GPIO bank description, add it to the 695 * bank list. 696 */ 697 struct stm32_gpio_bank *bank = NULL; 698 699 if (fdt_get_status(fdt, b_node) == DT_STATUS_DISABLED || 700 bank_is_registered(fdt, b_node)) 701 continue; 702 703 res = dt_stm32_gpio_bank(fdt, b_node, compat_data, 704 range_offs, &bank); 705 if (res) 706 return res; 707 708 /* Registering a provider should not defer probe */ 709 res = gpio_register_provider(fdt, b_node, 710 stm32_gpio_get_dt, bank); 711 if (res) 712 panic(); 713 714 STAILQ_INSERT_TAIL(&bank_list, bank, link); 715 716 if (IS_ENABLED(CFG_STM32MP13)) 717 set_bank_gpio_non_secure(bank); 718 } else { 719 if (len != -FDT_ERR_NOTFOUND) 720 panic(); 721 } 722 } 723 724 return TEE_SUCCESS; 725 } 726 727 728 int stm32_get_gpio_count(void *fdt, int pinctrl_node, unsigned int bank) 729 { 730 int node = 0; 731 const fdt32_t *cuint = NULL; 732 733 fdt_for_each_subnode(node, fdt, pinctrl_node) { 734 if (!fdt_getprop(fdt, node, "gpio-controller", NULL)) 735 continue; 736 737 cuint = fdt_getprop(fdt, node, "reg", NULL); 738 if (!cuint) 739 continue; 740 741 if (fdt32_to_cpu(*cuint) != stm32_get_gpio_bank_offset(bank)) 742 continue; 743 744 cuint = fdt_getprop(fdt, node, "ngpios", NULL); 745 if (!cuint) 746 panic(); 747 748 return (int)fdt32_to_cpu(*cuint); 749 } 750 751 return -1; 752 } 753 754 void stm32_gpio_set_secure_cfg(unsigned int bank_id, unsigned int pin, 755 bool secure) 756 { 757 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 758 uint32_t exceptions = 0; 759 760 if (clk_enable(bank->clock)) 761 panic(); 762 exceptions = cpu_spin_lock_xsave(&gpio_lock); 763 764 if (secure) 765 io_setbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 766 else 767 io_clrbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 768 769 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 770 clk_disable(bank->clock); 771 } 772 773 #ifdef CFG_DRIVERS_PINCTRL 774 static TEE_Result stm32_pinctrl_conf_apply(struct pinconf *conf) 775 { 776 struct stm32_pinctrl_array *ref = conf->priv; 777 struct stm32_pinctrl *p = ref->pinctrl; 778 size_t pin_count = ref->count; 779 size_t n = 0; 780 781 for (n = 0; n < pin_count; n++) 782 set_gpio_cfg(p[n].bank, p[n].pin, &p[n].cfg); 783 784 return TEE_SUCCESS; 785 } 786 787 static void stm32_pinctrl_conf_free(struct pinconf *conf) 788 { 789 free(conf); 790 } 791 792 static const struct pinctrl_ops stm32_pinctrl_ops = { 793 .conf_apply = stm32_pinctrl_conf_apply, 794 .conf_free = stm32_pinctrl_conf_free, 795 }; 796 797 DECLARE_KEEP_PAGER(stm32_pinctrl_ops); 798 799 void stm32_gpio_pinctrl_bank_pin(struct pinctrl_state *pinctrl, 800 unsigned int *bank, unsigned int *pin, 801 unsigned int *count) 802 { 803 size_t conf_index = 0; 804 size_t pin_count = 0; 805 size_t n = 0; 806 807 assert(count); 808 if (!pinctrl) 809 goto out; 810 811 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 812 struct pinconf *pinconf = pinctrl->confs[conf_index]; 813 struct stm32_pinctrl_array *ref = pinconf->priv; 814 815 /* Consider only the stm32_gpio pins */ 816 if (pinconf->ops != &stm32_pinctrl_ops) 817 continue; 818 819 if (bank || pin) { 820 for (n = 0; n < ref->count; n++) { 821 if (bank && pin_count < *count) 822 bank[pin_count] = ref->pinctrl[n].bank; 823 if (pin && pin_count < *count) 824 pin[pin_count] = ref->pinctrl[n].pin; 825 pin_count++; 826 } 827 } else { 828 pin_count += ref->count; 829 } 830 } 831 832 out: 833 *count = pin_count; 834 } 835 836 void stm32_pinctrl_set_secure_cfg(struct pinctrl_state *pinctrl, bool secure) 837 { 838 size_t conf_index = 0; 839 840 if (!pinctrl) 841 return; 842 843 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 844 struct pinconf *pinconf = pinctrl->confs[conf_index]; 845 struct stm32_pinctrl_array *ref = pinconf->priv; 846 struct stm32_pinctrl *pc = NULL; 847 size_t n = 0; 848 849 for (n = 0; n < ref->count; n++) { 850 if (pinconf->ops != &stm32_pinctrl_ops) 851 continue; 852 853 pc = ref->pinctrl + n; 854 stm32_gpio_set_secure_cfg(pc->bank, pc->pin, secure); 855 } 856 } 857 } 858 859 /* Allocate and return a pinctrl configuration from a DT reference */ 860 static TEE_Result stm32_pinctrl_dt_get(struct dt_pargs *pargs, 861 void *data __unused, 862 struct pinconf **out_pinconf) 863 { 864 struct conf { 865 struct pinconf pinconf; 866 struct stm32_pinctrl_array array_ref; 867 } *loc_conf = NULL; 868 struct stm32_pinctrl *pinctrl = NULL; 869 struct pinconf *pinconf = NULL; 870 const void *fdt = NULL; 871 size_t pin_count = 0; 872 int pinctrl_node = 0; 873 int pinmux_node = 0; 874 int count = 0; 875 876 pinctrl_node = pargs->phandle_node; 877 fdt = pargs->fdt; 878 assert(fdt && pinctrl_node); 879 880 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 881 if (fdt_getprop(fdt, pinmux_node, "pinmux", &count)) 882 pin_count += (size_t)count / sizeof(uint32_t); 883 else if (count != -FDT_ERR_NOTFOUND) 884 panic(); 885 } 886 887 loc_conf = calloc(1, sizeof(*loc_conf) + sizeof(*pinctrl) * pin_count); 888 if (!loc_conf) 889 return TEE_ERROR_OUT_OF_MEMORY; 890 891 pinconf = &loc_conf->pinconf; 892 pinconf->ops = &stm32_pinctrl_ops; 893 pinconf->priv = &loc_conf->array_ref; 894 895 loc_conf->array_ref.count = pin_count; 896 pinctrl = loc_conf->array_ref.pinctrl; 897 898 count = 0; 899 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 900 int found = 0; 901 902 found = get_pinctrl_from_fdt(fdt, pinmux_node, pinctrl + count, 903 pin_count - count); 904 if (found <= 0 && found > ((int)pin_count - count)) { 905 /* We can't recover from an error here so let's panic */ 906 panic(); 907 } 908 909 count += found; 910 } 911 912 *out_pinconf = pinconf; 913 914 return TEE_SUCCESS; 915 } 916 #endif /*CFG_DRIVERS_PINCTRL*/ 917 918 static TEE_Result stm32_pinctrl_probe(const void *fdt, int node, 919 const void *compat_data) 920 { 921 TEE_Result res = TEE_ERROR_GENERIC; 922 923 /* Register GPIO banks described in this pin control node */ 924 res = dt_stm32_gpio_pinctrl(fdt, node, compat_data); 925 if (res) 926 return res; 927 928 #ifdef CFG_DRIVERS_PINCTRL 929 res = pinctrl_register_provider(fdt, node, stm32_pinctrl_dt_get, 930 (void *)compat_data); 931 if (res) 932 return res; 933 #endif 934 935 return TEE_SUCCESS; 936 } 937 938 static const struct dt_device_match stm32_pinctrl_match_table[] = { 939 { .compatible = "st,stm32mp135-pinctrl" }, 940 { .compatible = "st,stm32mp157-pinctrl" }, 941 { .compatible = "st,stm32mp157-z-pinctrl" }, 942 { } 943 }; 944 945 DEFINE_DT_DRIVER(stm32_pinctrl_dt_driver) = { 946 .name = "stm32_gpio-pinctrl", 947 .type = DT_DRIVER_PINCTRL, 948 .match_table = stm32_pinctrl_match_table, 949 .probe = stm32_pinctrl_probe, 950 }; 951