1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2019, STMicroelectronics 4 * 5 * STM32 GPIO driver is used as pin controller for stm32mp SoCs. 6 * The driver API is defined in header file stm32_gpio.h. 7 */ 8 9 #include <assert.h> 10 #include <drivers/stm32_gpio.h> 11 #include <io.h> 12 #include <kernel/dt.h> 13 #include <kernel/generic_boot.h> 14 #include <kernel/panic.h> 15 #include <kernel/spinlock.h> 16 #include <mm/core_memprot.h> 17 #include <stdbool.h> 18 #include <stm32_util.h> 19 #include <trace.h> 20 #include <util.h> 21 22 #ifdef CFG_DT 23 #include <libfdt.h> 24 #endif 25 26 #define GPIO_PIN_MAX 15 27 28 #define GPIO_MODER_OFFSET 0x00 29 #define GPIO_OTYPER_OFFSET 0x04 30 #define GPIO_OSPEEDR_OFFSET 0x08 31 #define GPIO_PUPDR_OFFSET 0x0c 32 #define GPIO_IDR_OFFSET 0x10 33 #define GPIO_ODR_OFFSET 0x14 34 #define GPIO_BSRR_OFFSET 0x18 35 #define GPIO_AFRL_OFFSET 0x20 36 #define GPIO_AFRH_OFFSET 0x24 37 #define GPIO_SECR_OFFSET 0x30 38 39 #define GPIO_ALT_LOWER_LIMIT 0x8 40 41 #define GPIO_MODE_MASK GENMASK_32(1, 0) 42 #define GPIO_OSPEED_MASK GENMASK_32(1, 0) 43 #define GPIO_PUPD_PULL_MASK GENMASK_32(1, 0) 44 #define GPIO_ALTERNATE_MASK GENMASK_32(15, 0) 45 46 #define DT_GPIO_BANK_SHIFT 12 47 #define DT_GPIO_BANK_MASK GENMASK_32(16, 12) 48 #define DT_GPIO_PIN_SHIFT 8 49 #define DT_GPIO_PIN_MASK GENMASK_32(11, 8) 50 #define DT_GPIO_MODE_MASK GENMASK_32(7, 0) 51 52 static unsigned int gpio_lock; 53 54 /* Save to output @cfg the current GPIO (@bank/@pin) configuration */ 55 static void get_gpio_cfg(uint32_t bank, uint32_t pin, struct gpio_cfg *cfg) 56 { 57 vaddr_t base = stm32_get_gpio_bank_base(bank); 58 unsigned int clock = stm32_get_gpio_bank_clock(bank); 59 60 stm32_clock_enable(clock); 61 62 /* 63 * Save GPIO configuration bits spread over the few bank registers. 64 * 1bit fields are accessed at bit position being the pin index. 65 * 2bit fields are accessed at bit position being twice the pin index. 66 * 4bit fields are accessed at bit position being fourth the pin index 67 * but accessed from 2 32bit registers at incremental addresses. 68 */ 69 cfg->mode = (io_read32(base + GPIO_MODER_OFFSET) >> (pin << 1)) & 70 GPIO_MODE_MASK; 71 72 cfg->otype = (io_read32(base + GPIO_OTYPER_OFFSET) >> pin) & 1; 73 74 cfg->ospeed = (io_read32(base + GPIO_OSPEEDR_OFFSET) >> (pin << 1)) & 75 GPIO_OSPEED_MASK; 76 77 cfg->pupd = (io_read32(base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & 78 GPIO_PUPD_PULL_MASK; 79 80 cfg->od = (io_read32(base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; 81 82 if (pin < GPIO_ALT_LOWER_LIMIT) 83 cfg->af = (io_read32(base + GPIO_AFRL_OFFSET) >> (pin << 2)) & 84 GPIO_ALTERNATE_MASK; 85 else 86 cfg->af = (io_read32(base + GPIO_AFRH_OFFSET) >> 87 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) & 88 GPIO_ALTERNATE_MASK; 89 90 stm32_clock_disable(clock); 91 } 92 93 /* Apply GPIO (@bank/@pin) configuration described by @cfg */ 94 static void set_gpio_cfg(uint32_t bank, uint32_t pin, struct gpio_cfg *cfg) 95 { 96 vaddr_t base = stm32_get_gpio_bank_base(bank); 97 unsigned int clock = stm32_get_gpio_bank_clock(bank); 98 uint32_t exceptions = cpu_spin_lock_xsave(&gpio_lock); 99 100 stm32_clock_enable(clock); 101 102 /* Load GPIO MODE value, 2bit value shifted by twice the pin number */ 103 io_clrsetbits32(base + GPIO_MODER_OFFSET, 104 GPIO_MODE_MASK << (pin << 1), 105 cfg->mode << (pin << 1)); 106 107 /* Load GPIO Output TYPE value, 1bit shifted by pin number value */ 108 io_clrsetbits32(base + GPIO_OTYPER_OFFSET, BIT(pin), cfg->otype << pin); 109 110 /* Load GPIO Output Speed confguration, 2bit value */ 111 io_clrsetbits32(base + GPIO_OSPEEDR_OFFSET, 112 GPIO_OSPEED_MASK << (pin << 1), 113 cfg->ospeed << (pin << 1)); 114 115 /* Load GPIO pull configuration, 2bit value */ 116 io_clrsetbits32(base + GPIO_PUPDR_OFFSET, BIT(pin), 117 cfg->pupd << (pin << 1)); 118 119 /* Load pin mux Alternate Function configuration, 4bit value */ 120 if (pin < GPIO_ALT_LOWER_LIMIT) { 121 io_clrsetbits32(base + GPIO_AFRL_OFFSET, 122 GPIO_ALTERNATE_MASK << (pin << 2), 123 cfg->af << (pin << 2)); 124 } else { 125 size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2; 126 127 io_clrsetbits32(base + GPIO_AFRH_OFFSET, 128 GPIO_ALTERNATE_MASK << shift, 129 cfg->af << shift); 130 } 131 132 /* Load GPIO Output direction confuguration, 1bit */ 133 io_clrsetbits32(base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin); 134 135 stm32_clock_disable(clock); 136 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 137 } 138 139 void stm32_pinctrl_load_active_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 140 { 141 size_t n = 0; 142 143 for (n = 0; n < cnt; n++) 144 set_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 145 &pinctrl[n].active_cfg); 146 } 147 148 void stm32_pinctrl_load_standby_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 149 { 150 size_t n = 0; 151 152 for (n = 0; n < cnt; n++) 153 set_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 154 &pinctrl[n].standby_cfg); 155 } 156 157 void stm32_pinctrl_store_standby_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 158 { 159 size_t n = 0; 160 161 for (n = 0; n < cnt; n++) 162 get_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 163 &pinctrl[n].standby_cfg); 164 } 165 166 #ifdef CFG_DT 167 /* Panic if GPIO bank information from platform do not match DTB description */ 168 static void ckeck_gpio_bank(void *fdt, uint32_t bank, int pinctrl_node) 169 { 170 int pinctrl_subnode = 0; 171 172 fdt_for_each_subnode(pinctrl_subnode, fdt, pinctrl_node) { 173 const fdt32_t *cuint = NULL; 174 175 if (fdt_getprop(fdt, pinctrl_subnode, 176 "gpio-controller", NULL) == NULL) 177 continue; 178 179 /* Check bank register offset matches platform assumptions */ 180 cuint = fdt_getprop(fdt, pinctrl_subnode, "reg", NULL); 181 if (fdt32_to_cpu(*cuint) != stm32_get_gpio_bank_offset(bank)) 182 continue; 183 184 /* Check bank clock matches platform assumptions */ 185 cuint = fdt_getprop(fdt, pinctrl_subnode, "clocks", NULL); 186 if (!cuint) 187 panic(); 188 cuint++; 189 if (fdt32_to_cpu(*cuint) != stm32_get_gpio_bank_clock(bank)) 190 panic(); 191 192 /* Check controller is enabled */ 193 if (_fdt_get_status(fdt, pinctrl_subnode) == DT_STATUS_DISABLED) 194 panic(); 195 196 return; 197 } 198 199 panic(); 200 } 201 202 /* Count pins described in the DT node and get related data if possible */ 203 static int get_pinctrl_from_fdt(void *fdt, int node, 204 struct stm32_pinctrl *pinctrl, size_t count) 205 { 206 const fdt32_t *cuint, *slewrate; 207 int len = 0; 208 int pinctrl_node = 0; 209 uint32_t i = 0; 210 uint32_t speed = GPIO_OSPEED_LOW; 211 uint32_t pull = GPIO_PUPD_NO_PULL; 212 size_t found = 0; 213 214 cuint = fdt_getprop(fdt, node, "pinmux", &len); 215 if (!cuint) 216 return -FDT_ERR_NOTFOUND; 217 218 pinctrl_node = fdt_parent_offset(fdt, fdt_parent_offset(fdt, node)); 219 if (pinctrl_node < 0) 220 return -FDT_ERR_NOTFOUND; 221 222 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); 223 if (slewrate) 224 speed = fdt32_to_cpu(*slewrate); 225 226 if (fdt_getprop(fdt, node, "bias-pull-up", NULL)) 227 pull = GPIO_PUPD_PULL_UP; 228 if (fdt_getprop(fdt, node, "bias-pull-down", NULL)) 229 pull = GPIO_PUPD_PULL_DOWN; 230 231 for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 232 uint32_t pincfg = 0; 233 uint32_t bank = 0; 234 uint32_t pin = 0; 235 uint32_t mode = 0; 236 uint32_t alternate = 0; 237 bool opendrain = false; 238 239 pincfg = fdt32_to_cpu(*cuint); 240 cuint++; 241 242 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; 243 244 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT; 245 246 mode = pincfg & DT_GPIO_MODE_MASK; 247 248 switch (mode) { 249 case 0: 250 mode = GPIO_MODE_INPUT; 251 break; 252 case 1: 253 case 2: 254 case 3: 255 case 4: 256 case 5: 257 case 6: 258 case 7: 259 case 8: 260 case 9: 261 case 10: 262 case 11: 263 case 12: 264 case 13: 265 case 14: 266 case 15: 267 case 16: 268 alternate = mode - 1U; 269 mode = GPIO_MODE_ALTERNATE; 270 break; 271 case 17: 272 mode = GPIO_MODE_ANALOG; 273 break; 274 default: 275 mode = GPIO_MODE_OUTPUT; 276 break; 277 } 278 279 if (fdt_getprop(fdt, node, "drive-open-drain", NULL)) 280 opendrain = true; 281 282 /* Check GPIO bank clock/base address against platform */ 283 ckeck_gpio_bank(fdt, bank, pinctrl_node); 284 285 if (found < count) { 286 struct stm32_pinctrl *ref = &pinctrl[found]; 287 288 ref->bank = (uint8_t)bank; 289 ref->pin = (uint8_t)pin; 290 ref->active_cfg.mode = mode; 291 ref->active_cfg.otype = opendrain ? 1 : 0; 292 ref->active_cfg.ospeed = speed; 293 ref->active_cfg.pupd = pull; 294 ref->active_cfg.od = 0; 295 ref->active_cfg.af = alternate; 296 /* Default to analog mode for standby state */ 297 ref->standby_cfg.mode = GPIO_MODE_ANALOG; 298 ref->standby_cfg.pupd = GPIO_PUPD_NO_PULL; 299 } 300 301 found++; 302 } 303 304 return (int)found; 305 } 306 307 int stm32_pinctrl_fdt_get_pinctrl(void *fdt, int device_node, 308 struct stm32_pinctrl *pinctrl, size_t count) 309 { 310 const fdt32_t *cuint = NULL; 311 int lenp = 0; 312 int i = 0; 313 size_t found = 0; 314 315 cuint = fdt_getprop(fdt, device_node, "pinctrl-0", &lenp); 316 if (!cuint) 317 return -FDT_ERR_NOTFOUND; 318 319 for (i = 0; i < (lenp / 4); i++) { 320 int node = 0; 321 int subnode = 0; 322 323 node = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 324 if (node < 0) 325 return -FDT_ERR_NOTFOUND; 326 327 fdt_for_each_subnode(subnode, fdt, node) { 328 size_t n = 0; 329 int rc = 0; 330 331 if (count > found) 332 n = count - found; 333 else 334 n = 0; 335 336 rc = get_pinctrl_from_fdt(fdt, subnode, 337 &pinctrl[found], n); 338 if (rc < 0) 339 return rc; 340 341 found += (size_t)rc; 342 } 343 344 cuint++; 345 } 346 347 return (int)found; 348 } 349 350 int stm32_get_gpio_count(void *fdt, int pinctrl_node, unsigned int bank) 351 { 352 int node = 0; 353 const fdt32_t *cuint = NULL; 354 355 fdt_for_each_subnode(node, fdt, pinctrl_node) { 356 if (!fdt_getprop(fdt, node, "gpio-controller", NULL)) 357 continue; 358 359 cuint = fdt_getprop(fdt, node, "reg", NULL); 360 if (!cuint) 361 continue; 362 363 if (fdt32_to_cpu(*cuint) != stm32_get_gpio_bank_offset(bank)) 364 continue; 365 366 cuint = fdt_getprop(fdt, node, "ngpios", NULL); 367 if (!cuint) 368 panic(); 369 370 return (int)fdt32_to_cpu(*cuint); 371 } 372 373 return -1; 374 } 375 #endif /*CFG_DT*/ 376 377 static __maybe_unused bool valid_gpio_config(unsigned int bank, 378 unsigned int pin, bool input) 379 { 380 vaddr_t base = stm32_get_gpio_bank_base(bank); 381 uint32_t mode = (io_read32(base + GPIO_MODER_OFFSET) >> (pin << 1)) & 382 GPIO_MODE_MASK; 383 384 if (pin > GPIO_PIN_MAX) 385 return false; 386 387 if (input) 388 return mode == GPIO_MODE_INPUT; 389 else 390 return mode == GPIO_MODE_OUTPUT; 391 } 392 393 int stm32_gpio_get_input_level(unsigned int bank, unsigned int pin) 394 { 395 vaddr_t base = stm32_get_gpio_bank_base(bank); 396 unsigned int clock = stm32_get_gpio_bank_clock(bank); 397 int rc = 0; 398 399 assert(valid_gpio_config(bank, pin, true)); 400 401 stm32_clock_enable(clock); 402 403 if (io_read32(base + GPIO_IDR_OFFSET) == BIT(pin)) 404 rc = 1; 405 406 stm32_clock_disable(clock); 407 408 return rc; 409 } 410 411 void stm32_gpio_set_output_level(unsigned int bank, unsigned int pin, int level) 412 { 413 vaddr_t base = stm32_get_gpio_bank_base(bank); 414 unsigned int clock = stm32_get_gpio_bank_clock(bank); 415 416 assert(valid_gpio_config(bank, pin, false)); 417 418 stm32_clock_enable(clock); 419 420 if (level) 421 io_write32(base + GPIO_BSRR_OFFSET, BIT(pin)); 422 else 423 io_write32(base + GPIO_BSRR_OFFSET, BIT(pin + 16)); 424 425 stm32_clock_disable(clock); 426 } 427 428 void stm32_gpio_set_secure_cfg(unsigned int bank, unsigned int pin, bool secure) 429 { 430 vaddr_t base = stm32_get_gpio_bank_base(bank); 431 unsigned int clock = stm32_get_gpio_bank_clock(bank); 432 uint32_t exceptions = cpu_spin_lock_xsave(&gpio_lock); 433 434 stm32_clock_enable(clock); 435 436 if (secure) 437 io_setbits32(base + GPIO_SECR_OFFSET, BIT(pin)); 438 else 439 io_clrbits32(base + GPIO_SECR_OFFSET, BIT(pin)); 440 441 stm32_clock_disable(clock); 442 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 443 } 444