1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2024, STMicroelectronics 4 * 5 * STM32 GPIO driver is used as pin controller for stm32mp SoCs. 6 */ 7 8 #include <assert.h> 9 #include <compiler.h> 10 #include <drivers/clk.h> 11 #include <drivers/clk_dt.h> 12 #include <drivers/firewall.h> 13 #include <drivers/gpio.h> 14 #include <drivers/pinctrl.h> 15 #include <drivers/stm32_gpio.h> 16 #include <drivers/stm32_rif.h> 17 #include <dt-bindings/gpio/stm32mp_gpio.h> 18 #include <dt-bindings/pinctrl/stm32-pinfunc.h> 19 #include <io.h> 20 #include <kernel/dt.h> 21 #include <kernel/boot.h> 22 #include <kernel/panic.h> 23 #include <kernel/pm.h> 24 #include <kernel/spinlock.h> 25 #include <libfdt.h> 26 #include <mm/core_memprot.h> 27 #include <stdbool.h> 28 #include <stdint.h> 29 #include <stm32_util.h> 30 #include <sys/queue.h> 31 #include <trace.h> 32 #include <util.h> 33 34 #define GPIO_PIN_MAX 15 35 36 #define GPIO_MODER_OFFSET U(0x00) 37 #define GPIO_OTYPER_OFFSET U(0x04) 38 #define GPIO_OSPEEDR_OFFSET U(0x08) 39 #define GPIO_PUPDR_OFFSET U(0x0c) 40 #define GPIO_IDR_OFFSET U(0x10) 41 #define GPIO_ODR_OFFSET U(0x14) 42 #define GPIO_BSRR_OFFSET U(0x18) 43 #define GPIO_AFRL_OFFSET U(0x20) 44 #define GPIO_AFRH_OFFSET U(0x24) 45 #define GPIO_SECR_OFFSET U(0x30) 46 #define GPIO_PRIVCFGR_OFFSET U(0x34) 47 #define GPIO_RCFGLOCKR_OFFSET U(0x38) 48 #define GPIO_CIDCFGR(x) (U(0x50) + U(0x8) * (x)) 49 #define GPIO_SEMCR(x) (U(0x54) + U(0x8) * (x)) 50 51 #define GPIO_ALT_LOWER_LIMIT U(0x8) 52 53 /* 54 * CIDCFGR register bitfields 55 */ 56 #define GPIO_CIDCFGR_SEMWL_MASK GENMASK_32(23, 16) 57 #define GPIO_CIDCFGR_SCID_MASK GENMASK_32(6, 4) 58 #define GPIO_CIDCFGR_CONF_MASK (_CIDCFGR_CFEN | _CIDCFGR_SEMEN | \ 59 GPIO_CIDCFGR_SCID_MASK | \ 60 GPIO_CIDCFGR_SEMWL_MASK) 61 62 /* 63 * PRIVCFGR register bitfields 64 */ 65 #define GPIO_PRIVCFGR_MASK GENMASK_32(15, 0) 66 67 /* 68 * SECCFGR register bitfields 69 */ 70 #define GPIO_SECCFGR_MASK GENMASK_32(15, 0) 71 72 /* 73 * RCFGLOCKR register bitfields 74 */ 75 #define GPIO_RCFGLOCKR_MASK GENMASK_32(15, 0) 76 77 /* 78 * SEMCR register bitfields 79 */ 80 #define GPIO_SEMCR_SCID_M GENMASK_32(6, 4) 81 82 #define GPIO_MODE_MASK GENMASK_32(1, 0) 83 #define GPIO_OSPEED_MASK GENMASK_32(1, 0) 84 #define GPIO_PUPD_PULL_MASK GENMASK_32(1, 0) 85 #define GPIO_ALTERNATE_MASK GENMASK_32(3, 0) 86 87 #define DT_GPIO_BANK_SHIFT U(12) 88 #define DT_GPIO_BANK_MASK GENMASK_32(16, 12) 89 #define DT_GPIO_PIN_SHIFT U(8) 90 #define DT_GPIO_PIN_MASK GENMASK_32(11, 8) 91 #define DT_GPIO_MODE_MASK GENMASK_32(7, 0) 92 93 #define DT_GPIO_BANK_NAME0 "GPIOA" 94 95 #define GPIO_MODE_INPUT U(0x0) 96 #define GPIO_MODE_OUTPUT U(0x1) 97 #define GPIO_MODE_ALTERNATE U(0x2) 98 #define GPIO_MODE_ANALOG U(0x3) 99 100 #define GPIO_OTYPE_PUSH_PULL U(0x0) 101 #define GPIO_OTYPE_OPEN_DRAIN U(0x1) 102 103 #define GPIO_OSPEED_LOW U(0x0) 104 #define GPIO_OSPEED_MEDIUM U(0x1) 105 #define GPIO_OSPEED_HIGH U(0x2) 106 #define GPIO_OSPEED_VERY_HIGH U(0x3) 107 108 #define GPIO_PUPD_NO_PULL U(0x0) 109 #define GPIO_PUPD_PULL_UP U(0x1) 110 #define GPIO_PUPD_PULL_DOWN U(0x2) 111 112 #define GPIO_OD_LEVEL_LOW U(0x0) 113 #define GPIO_OD_LEVEL_HIGH U(0x1) 114 115 #define GPIO_MAX_CID_SUPPORTED U(3) 116 117 /* 118 * GPIO configuration description structured as single 16bit word 119 * for efficient save/restore when GPIO pin suspends or resumes. 120 * 121 * @mode: One of GPIO_MODE_* 122 * @otype: One of GPIO_OTYPE_* 123 * @ospeed: One of GPIO_OSPEED_* 124 * @pupd: One of GPIO_PUPD_* 125 * @od: One of GPIO_OD_* 126 * @af: Alternate function numerical ID between 0 and 15 127 * @nsec: Hint on expected secure state of the pin: 0 if secure, 1 otherwise 128 */ 129 struct gpio_cfg { 130 uint16_t mode: 2; 131 uint16_t otype: 1; 132 uint16_t ospeed: 2; 133 uint16_t pupd: 2; 134 uint16_t od: 1; 135 uint16_t af: 4; 136 uint16_t nsec: 1; 137 }; 138 139 /* 140 * Description of a pin and its muxing 141 * 142 * @bank: GPIO bank identifier as assigned by the platform 143 * @pin: Pin number in the GPIO bank 144 * @cfg: Pin configuration 145 */ 146 struct stm32_pinctrl { 147 uint8_t bank; 148 uint8_t pin; 149 struct gpio_cfg cfg; 150 }; 151 152 /* 153 * struct stm32_pinctrl_array - Array of pins in a pin control state 154 * @count: Number of cells in @pinctrl 155 * @pinctrl: Pin control configuration 156 */ 157 struct stm32_pinctrl_array { 158 size_t count; 159 struct stm32_pinctrl pinctrl[]; 160 }; 161 162 /** 163 * struct stm32_gpio_bank - GPIO bank instance 164 * 165 * @base: base address of the GPIO controller registers. 166 * @clock: clock identifier. 167 * @gpio_chip: GPIO chip reference for that GPIO bank 168 * @ngpios: number of GPIOs. 169 * @bank_id: Id of the bank. 170 * @lock: lock protecting the GPIO bank access. 171 * @rif_cfg: RIF configuration data 172 * @seccfgr: non-RIF bank secure configuration data 173 * @sec_support: True if bank supports pin security protection, else false 174 * @ready: True if configuration is applied, else false 175 * @is_tdcid: True if OP-TEE runs as Trusted Domain CID 176 * @link: Link in bank list 177 */ 178 struct stm32_gpio_bank { 179 vaddr_t base; 180 struct clk *clock; 181 struct gpio_chip gpio_chip; 182 unsigned int ngpios; 183 unsigned int bank_id; 184 unsigned int lock; 185 struct rif_conf_data *rif_cfg; 186 uint32_t seccfgr; 187 bool sec_support; 188 bool ready; 189 bool is_tdcid; 190 STAILQ_ENTRY(stm32_gpio_bank) link; 191 }; 192 193 /* 194 * struct stm32_gpio_pm_state - Consumed GPIO for PM purpose 195 * @gpio_pinctrl: Reference and configuration state for a consumed GPIO 196 * @level: GPIO level 197 * @link: Link in consumed GPIO list 198 */ 199 struct stm32_gpio_pm_state { 200 struct stm32_pinctrl gpio_pinctrl; 201 uint8_t level; 202 SLIST_ENTRY(stm32_gpio_pm_state) link; 203 }; 204 205 /** 206 * Compatibility information of supported banks 207 * 208 * @gpioz: True if bank is a GPIOZ bank 209 * @secure_control: Identify GPIO security bank capability. 210 * @secure_extended: Identify RIF presence. 211 */ 212 struct bank_compat { 213 bool gpioz; 214 bool secure_control; 215 bool secure_extended; 216 }; 217 218 static unsigned int gpio_lock; 219 220 static STAILQ_HEAD(, stm32_gpio_bank) bank_list = 221 STAILQ_HEAD_INITIALIZER(bank_list); 222 223 static SLIST_HEAD(, stm32_gpio_pm_state) consumed_gpios_head; 224 225 static bool is_stm32_gpio_chip(struct gpio_chip *chip); 226 227 static struct stm32_gpio_bank *gpio_chip_to_bank(struct gpio_chip *chip) 228 { 229 return container_of(chip, struct stm32_gpio_bank, gpio_chip); 230 } 231 232 static enum gpio_level stm32_gpio_get_level(struct gpio_chip *chip, 233 unsigned int gpio_pin) 234 { 235 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 236 enum gpio_level level = GPIO_LEVEL_HIGH; 237 unsigned int reg_offset = 0; 238 unsigned int mode = 0; 239 240 assert(gpio_pin < bank->ngpios); 241 242 if (clk_enable(bank->clock)) 243 panic(); 244 245 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 246 GPIO_MODE_MASK; 247 248 switch (mode) { 249 case GPIO_MODE_INPUT: 250 reg_offset = GPIO_IDR_OFFSET; 251 break; 252 case GPIO_MODE_OUTPUT: 253 reg_offset = GPIO_ODR_OFFSET; 254 break; 255 default: 256 panic(); 257 } 258 259 if (io_read32(bank->base + reg_offset) & BIT(gpio_pin)) 260 level = GPIO_LEVEL_HIGH; 261 else 262 level = GPIO_LEVEL_LOW; 263 264 clk_disable(bank->clock); 265 266 return level; 267 } 268 269 static void stm32_gpio_set_level(struct gpio_chip *chip, unsigned int gpio_pin, 270 enum gpio_level level) 271 { 272 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 273 274 assert(gpio_pin < bank->ngpios); 275 276 if (clk_enable(bank->clock)) 277 panic(); 278 279 assert(((io_read32(bank->base + GPIO_MODER_OFFSET) >> 280 (gpio_pin << 1)) & GPIO_MODE_MASK) == GPIO_MODE_OUTPUT); 281 282 if (level == GPIO_LEVEL_HIGH) 283 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin)); 284 else 285 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin + 16)); 286 287 clk_disable(bank->clock); 288 } 289 290 static enum gpio_dir stm32_gpio_get_direction(struct gpio_chip *chip, 291 unsigned int gpio_pin) 292 { 293 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 294 uint32_t mode = 0; 295 296 assert(gpio_pin < bank->ngpios); 297 298 if (clk_enable(bank->clock)) 299 panic(); 300 301 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 302 GPIO_MODE_MASK; 303 304 clk_disable(bank->clock); 305 306 switch (mode) { 307 case GPIO_MODE_INPUT: 308 return GPIO_DIR_IN; 309 case GPIO_MODE_OUTPUT: 310 return GPIO_DIR_OUT; 311 default: 312 panic(); 313 } 314 } 315 316 static void stm32_gpio_set_direction(struct gpio_chip *chip, 317 unsigned int gpio_pin, 318 enum gpio_dir direction) 319 { 320 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 321 uint32_t exceptions = 0; 322 uint32_t mode = 0; 323 324 assert(gpio_pin < bank->ngpios); 325 326 if (direction == GPIO_DIR_IN) 327 mode = GPIO_MODE_INPUT; 328 else 329 mode = GPIO_MODE_OUTPUT; 330 331 if (clk_enable(bank->clock)) 332 panic(); 333 exceptions = cpu_spin_lock_xsave(&gpio_lock); 334 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 335 SHIFT_U32(GPIO_MODE_MASK, gpio_pin << 1), 336 SHIFT_U32(mode, gpio_pin << 1)); 337 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 338 clk_disable(bank->clock); 339 } 340 341 /* Forward reference to the PM callback handler for consumed GPIOs */ 342 static TEE_Result consumed_gpios_pm(enum pm_op op, unsigned int pm_hint, 343 const struct pm_callback_handle *pm_hdl); 344 345 /* Forward reference to RIF semaphore release helper function */ 346 static void release_rif_semaphore_if_acquired(struct stm32_gpio_bank *bank, 347 unsigned int pin); 348 349 static void stm32_gpio_put_gpio(struct gpio_chip *chip, struct gpio *gpio) 350 { 351 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 352 struct stm32_gpio_pm_state *tstate = NULL; 353 struct stm32_gpio_pm_state *state = NULL; 354 uint32_t exceptions = 0; 355 356 assert(is_stm32_gpio_chip(chip)); 357 358 exceptions = cpu_spin_lock_xsave(&gpio_lock); 359 360 SLIST_FOREACH_SAFE(state, &consumed_gpios_head, link, tstate) { 361 if (state->gpio_pinctrl.bank == bank->bank_id && 362 state->gpio_pinctrl.pin == gpio->pin) { 363 SLIST_REMOVE(&consumed_gpios_head, state, 364 stm32_gpio_pm_state, link); 365 unregister_pm_driver_cb(consumed_gpios_pm, state); 366 release_rif_semaphore_if_acquired(bank, gpio->pin); 367 free(state); 368 free(gpio); 369 break; 370 } 371 } 372 assert(state); 373 374 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 375 } 376 377 static const struct gpio_ops stm32_gpio_ops = { 378 .get_direction = stm32_gpio_get_direction, 379 .set_direction = stm32_gpio_set_direction, 380 .get_value = stm32_gpio_get_level, 381 .set_value = stm32_gpio_set_level, 382 .put = stm32_gpio_put_gpio, 383 }; 384 385 static bool __maybe_unused is_stm32_gpio_chip(struct gpio_chip *chip) 386 { 387 return chip && chip->ops == &stm32_gpio_ops; 388 } 389 390 static struct stm32_gpio_bank *stm32_gpio_get_bank(unsigned int bank_id) 391 { 392 struct stm32_gpio_bank *bank = NULL; 393 394 STAILQ_FOREACH(bank, &bank_list, link) 395 if (bank_id == bank->bank_id) 396 return bank; 397 398 panic(); 399 } 400 401 #if defined(CFG_STM32_RIF) 402 static bool pin_is_accessible(struct stm32_gpio_bank *bank, unsigned int pin) 403 { 404 bool accessible = false; 405 uint32_t cidcfgr = 0; 406 407 if (!bank->rif_cfg) 408 return true; 409 410 if (clk_enable(bank->clock)) 411 panic(); 412 413 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin)); 414 415 if (!(cidcfgr & _CIDCFGR_CFEN)) { 416 /* Resource can be accessed when CID filtering is disabled */ 417 accessible = true; 418 } else if (stm32_rif_scid_ok(cidcfgr, GPIO_CIDCFGR_SCID_MASK, 419 RIF_CID1)) { 420 /* Resource can be accessed if CID1 is statically allowed */ 421 accessible = true; 422 } else if (stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) { 423 /* CID1 is allowed to request the semaphore */ 424 accessible = true; 425 } 426 427 clk_disable(bank->clock); 428 429 return accessible; 430 } 431 432 static TEE_Result acquire_rif_semaphore_if_needed(struct stm32_gpio_bank *bank, 433 unsigned int pin) 434 { 435 TEE_Result res = TEE_SUCCESS; 436 uint32_t cidcfgr = 0; 437 438 if (!bank->rif_cfg) 439 return TEE_SUCCESS; 440 441 res = clk_enable(bank->clock); 442 if (res) 443 return res; 444 445 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin)); 446 447 if (stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) 448 res = stm32_rif_acquire_semaphore(bank->base + GPIO_SEMCR(pin), 449 GPIO_MAX_CID_SUPPORTED); 450 451 clk_disable(bank->clock); 452 453 return res; 454 } 455 456 static uint32_t semaphore_current_cid(struct stm32_gpio_bank *bank, 457 unsigned int pin) 458 { 459 return (io_read32(bank->base + GPIO_SEMCR(pin)) >> 460 _CIDCFGR_SCID_SHIFT) & 461 GENMASK_32(GPIO_MAX_CID_SUPPORTED - 1, 0); 462 } 463 464 static void release_rif_semaphore_if_acquired(struct stm32_gpio_bank *bank, 465 unsigned int pin) 466 { 467 TEE_Result res = TEE_ERROR_GENERIC; 468 uint32_t cidcfgr = 0; 469 470 if (!bank->rif_cfg) 471 return; 472 473 res = clk_enable(bank->clock); 474 if (res) 475 panic(); 476 477 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(pin)); 478 479 if (stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1) && 480 semaphore_current_cid(bank, pin) == RIF_CID1) { 481 res = stm32_rif_release_semaphore(bank->base + GPIO_SEMCR(pin), 482 GPIO_MAX_CID_SUPPORTED); 483 if (res) { 484 EMSG("Failed to release GPIO %c%u semaphore", 485 bank->bank_id + 'A', pin); 486 panic(); 487 } 488 } 489 490 clk_disable(bank->clock); 491 } 492 #else 493 static bool pin_is_accessible(struct stm32_gpio_bank *bank __unused, 494 unsigned int pin __unused) 495 { 496 return true; 497 } 498 499 static TEE_Result 500 acquire_rif_semaphore_if_needed(struct stm32_gpio_bank *bank __unused, 501 unsigned int pin __unused) 502 { 503 return TEE_SUCCESS; 504 } 505 506 static void 507 release_rif_semaphore_if_acquired(struct stm32_gpio_bank *bank __unused, 508 unsigned int pin __unused) 509 { 510 } 511 #endif /*CFG_STM32_RIF*/ 512 513 static bool pin_is_secure(struct stm32_gpio_bank *bank, unsigned int pin) 514 { 515 bool secure = false; 516 517 if (bank->rif_cfg || bank->sec_support) { 518 if (clk_enable(bank->clock)) 519 panic(); 520 521 secure = io_read32(bank->base + GPIO_SECR_OFFSET) & BIT(pin); 522 523 clk_disable(bank->clock); 524 } 525 526 return secure; 527 } 528 529 /* Save to output @cfg the current GPIO (@bank_id/@pin) configuration */ 530 static void get_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 531 { 532 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 533 534 if (clk_enable(bank->clock)) 535 panic(); 536 537 /* 538 * Save GPIO configuration bits spread over the few bank registers. 539 * 1bit fields are accessed at bit position being the pin index. 540 * 2bit fields are accessed at bit position being twice the pin index. 541 * 4bit fields are accessed at bit position being fourth the pin index 542 * but accessed from 2 32bit registers at incremental addresses. 543 */ 544 cfg->mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (pin << 1)) & 545 GPIO_MODE_MASK; 546 547 cfg->otype = (io_read32(bank->base + GPIO_OTYPER_OFFSET) >> pin) & 1; 548 549 cfg->ospeed = (io_read32(bank->base + GPIO_OSPEEDR_OFFSET) >> 550 (pin << 1)) & GPIO_OSPEED_MASK; 551 552 cfg->pupd = (io_read32(bank->base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & 553 GPIO_PUPD_PULL_MASK; 554 555 cfg->od = (io_read32(bank->base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; 556 557 if (pin < GPIO_ALT_LOWER_LIMIT) 558 cfg->af = (io_read32(bank->base + GPIO_AFRL_OFFSET) >> 559 (pin << 2)) & GPIO_ALTERNATE_MASK; 560 else 561 cfg->af = (io_read32(bank->base + GPIO_AFRH_OFFSET) >> 562 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) & 563 GPIO_ALTERNATE_MASK; 564 565 clk_disable(bank->clock); 566 } 567 568 /* Apply GPIO (@bank/@pin) configuration described by @cfg */ 569 static void set_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 570 { 571 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 572 uint32_t exceptions = 0; 573 574 if (clk_enable(bank->clock)) 575 panic(); 576 exceptions = cpu_spin_lock_xsave(&gpio_lock); 577 578 /* Load GPIO MODE value, 2bit value shifted by twice the pin number */ 579 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 580 SHIFT_U32(GPIO_MODE_MASK, pin << 1), 581 SHIFT_U32(cfg->mode, pin << 1)); 582 583 /* Load GPIO Output TYPE value, 1bit shifted by pin number value */ 584 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, BIT(pin), 585 SHIFT_U32(cfg->otype, pin)); 586 587 /* Load GPIO Output Speed confguration, 2bit value */ 588 io_clrsetbits32(bank->base + GPIO_OSPEEDR_OFFSET, 589 SHIFT_U32(GPIO_OSPEED_MASK, pin << 1), 590 SHIFT_U32(cfg->ospeed, pin << 1)); 591 592 /* Load GPIO pull configuration, 2bit value */ 593 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, BIT(pin), 594 SHIFT_U32(cfg->pupd, pin << 1)); 595 596 /* Load pin mux Alternate Function configuration, 4bit value */ 597 if (pin < GPIO_ALT_LOWER_LIMIT) { 598 io_clrsetbits32(bank->base + GPIO_AFRL_OFFSET, 599 SHIFT_U32(GPIO_ALTERNATE_MASK, pin << 2), 600 SHIFT_U32(cfg->af, pin << 2)); 601 } else { 602 size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2; 603 604 io_clrsetbits32(bank->base + GPIO_AFRH_OFFSET, 605 SHIFT_U32(GPIO_ALTERNATE_MASK, shift), 606 SHIFT_U32(cfg->af, shift)); 607 } 608 609 /* Load GPIO Output direction confuguration, 1bit */ 610 io_clrsetbits32(bank->base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin); 611 612 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 613 clk_disable(bank->clock); 614 } 615 616 /* Count pins described in the DT node and get related data if possible */ 617 static int get_pinctrl_from_fdt(const void *fdt, int node, 618 int consumer_node __maybe_unused, 619 struct stm32_pinctrl *pinctrl, size_t count) 620 { 621 struct stm32_gpio_bank *bank_ref = NULL; 622 const fdt32_t *cuint = NULL; 623 const fdt32_t *slewrate = NULL; 624 int len = 0; 625 uint32_t i = 0; 626 uint32_t speed = GPIO_OSPEED_LOW; 627 uint32_t pull = GPIO_PUPD_NO_PULL; 628 size_t found = 0; 629 bool do_panic = false; 630 631 cuint = fdt_getprop(fdt, node, "pinmux", &len); 632 if (!cuint) 633 return -FDT_ERR_NOTFOUND; 634 635 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); 636 if (slewrate) 637 speed = fdt32_to_cpu(*slewrate); 638 639 if (fdt_getprop(fdt, node, "bias-pull-up", NULL)) 640 pull = GPIO_PUPD_PULL_UP; 641 if (fdt_getprop(fdt, node, "bias-pull-down", NULL)) 642 pull = GPIO_PUPD_PULL_DOWN; 643 644 for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 645 uint32_t pincfg = 0; 646 uint32_t bank = 0; 647 uint32_t pin = 0; 648 uint32_t mode = 0; 649 uint32_t alternate = 0; 650 uint32_t odata = 0; 651 bool opendrain = false; 652 bool pin_non_secure = true; 653 654 pincfg = fdt32_to_cpu(*cuint); 655 cuint++; 656 657 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; 658 659 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT; 660 661 mode = pincfg & DT_GPIO_MODE_MASK; 662 663 pin_non_secure = pincfg & STM32_PIN_NSEC; 664 665 switch (mode) { 666 case 0: 667 mode = GPIO_MODE_INPUT; 668 break; 669 case 1: 670 case 2: 671 case 3: 672 case 4: 673 case 5: 674 case 6: 675 case 7: 676 case 8: 677 case 9: 678 case 10: 679 case 11: 680 case 12: 681 case 13: 682 case 14: 683 case 15: 684 case 16: 685 alternate = mode - 1U; 686 mode = GPIO_MODE_ALTERNATE; 687 break; 688 case 17: 689 mode = GPIO_MODE_ANALOG; 690 break; 691 default: 692 mode = GPIO_MODE_OUTPUT; 693 break; 694 } 695 696 if (fdt_getprop(fdt, node, "drive-open-drain", NULL)) 697 opendrain = true; 698 699 if (fdt_getprop(fdt, node, "output-high", NULL) && 700 mode == GPIO_MODE_INPUT) { 701 mode = GPIO_MODE_OUTPUT; 702 odata = 1; 703 } 704 705 if (fdt_getprop(fdt, node, "output-low", NULL) && 706 mode == GPIO_MODE_INPUT) { 707 mode = GPIO_MODE_OUTPUT; 708 odata = 0; 709 } 710 711 if (found < count) { 712 struct stm32_pinctrl *ref = &pinctrl[found]; 713 714 ref->bank = (uint8_t)bank; 715 ref->pin = (uint8_t)pin; 716 ref->cfg.mode = mode; 717 if (opendrain) 718 ref->cfg.otype = GPIO_OTYPE_OPEN_DRAIN; 719 else 720 ref->cfg.otype = GPIO_OTYPE_PUSH_PULL; 721 ref->cfg.ospeed = speed; 722 ref->cfg.pupd = pull; 723 ref->cfg.od = odata; 724 ref->cfg.af = alternate; 725 ref->cfg.nsec = pin_non_secure; 726 727 bank_ref = stm32_gpio_get_bank(bank); 728 729 if (pin >= bank_ref->ngpios) { 730 EMSG("node %s requests pin %c%u that does not exist", 731 fdt_get_name(fdt, consumer_node, NULL), 732 bank + 'A', pin); 733 do_panic = true; 734 } 735 } 736 737 found++; 738 } 739 740 if (do_panic) 741 panic(); 742 743 return (int)found; 744 } 745 746 static TEE_Result consumed_gpios_pm(enum pm_op op, 747 unsigned int pm_hint __unused, 748 const struct pm_callback_handle *pm_hdl) 749 { 750 struct stm32_gpio_pm_state *handle = pm_hdl->handle; 751 unsigned int bank_id = handle->gpio_pinctrl.bank; 752 unsigned int pin = handle->gpio_pinctrl.pin; 753 struct gpio_chip *chip = &stm32_gpio_get_bank(bank_id)->gpio_chip; 754 755 if (op == PM_OP_RESUME) { 756 set_gpio_cfg(bank_id, pin, &handle->gpio_pinctrl.cfg); 757 if (handle->gpio_pinctrl.cfg.mode == GPIO_MODE_OUTPUT) 758 stm32_gpio_set_level(chip, pin, handle->level); 759 } else { 760 get_gpio_cfg(bank_id, pin, &handle->gpio_pinctrl.cfg); 761 if (handle->gpio_pinctrl.cfg.mode == GPIO_MODE_OUTPUT) 762 handle->level = stm32_gpio_get_level(chip, pin); 763 } 764 765 return TEE_SUCCESS; 766 } 767 DECLARE_KEEP_PAGER(consumed_gpios_pm); 768 769 static TEE_Result stm32_gpio_get_dt(struct dt_pargs *pargs, void *data, 770 struct gpio **out_gpio) 771 { 772 TEE_Result res = TEE_ERROR_GENERIC; 773 const char *consumer_name __maybe_unused = NULL; 774 struct stm32_gpio_pm_state *reg_state = NULL; 775 struct stm32_gpio_pm_state *state = NULL; 776 struct stm32_gpio_bank *bank = data; 777 struct gpio *gpio = NULL; 778 unsigned int shift_1b = 0; 779 unsigned int shift_2b = 0; 780 bool gpio_secure = true; 781 uint32_t exceptions = 0; 782 uint32_t otype = 0; 783 uint32_t pupd = 0; 784 uint32_t mode = 0; 785 786 consumer_name = fdt_get_name(pargs->fdt, pargs->consumer_node, 787 NULL); 788 789 res = gpio_dt_alloc_pin(pargs, &gpio); 790 if (res) 791 return res; 792 793 if (gpio->pin >= bank->ngpios) { 794 DMSG("Invalid GPIO reference"); 795 free(gpio); 796 return TEE_ERROR_GENERIC; 797 } 798 799 if (gpio->dt_flags & GPIO_STM32_NSEC) 800 gpio_secure = false; 801 802 state = calloc(1, sizeof(*state)); 803 if (!state) { 804 free(gpio); 805 return TEE_ERROR_OUT_OF_MEMORY; 806 } 807 808 SLIST_FOREACH(reg_state, &consumed_gpios_head, link) { 809 if (reg_state->gpio_pinctrl.bank == bank->bank_id && 810 reg_state->gpio_pinctrl.pin == gpio->pin) { 811 EMSG("node %s: GPIO %c%u is used by another device", 812 consumer_name, bank->bank_id + 'A', gpio->pin); 813 free(state); 814 free(gpio); 815 return TEE_ERROR_GENERIC; 816 } 817 } 818 819 if (!pin_is_accessible(bank, gpio->pin)) { 820 EMSG("node %s requests pin on GPIO %c%u which access is denied", 821 consumer_name, bank->bank_id + 'A', gpio->pin); 822 panic(); 823 } 824 825 res = acquire_rif_semaphore_if_needed(bank, gpio->pin); 826 if (res) { 827 EMSG("Failed to acquire GPIO %c%u semaphore for node %s", 828 bank->bank_id + 'A', gpio->pin, consumer_name); 829 return res; 830 } 831 832 if (gpio_secure && !(bank->rif_cfg || bank->sec_support)) { 833 EMSG("node %s requests secure GPIO %c%u that cannot be secured", 834 consumer_name, bank->bank_id + 'A', gpio->pin); 835 panic(); 836 } 837 838 if (gpio_secure != pin_is_secure(bank, gpio->pin)) { 839 IMSG("WARNING: node %s requests %s GPIO %c%u but pin is %s. Check st,protreg in GPIO bank node %s", 840 consumer_name, gpio_secure ? "secure" : "non-secure", 841 bank->bank_id + 'A', gpio->pin, 842 pin_is_secure(bank, gpio->pin) ? "secure" : "non-secure", 843 fdt_get_name(pargs->fdt, pargs->phandle_node, NULL)); 844 if (!IS_ENABLED(CFG_INSECURE)) 845 panic(); 846 } 847 848 state->gpio_pinctrl.pin = gpio->pin; 849 state->gpio_pinctrl.bank = bank->bank_id; 850 SLIST_INSERT_HEAD(&consumed_gpios_head, state, link); 851 852 register_pm_driver_cb(consumed_gpios_pm, state, "stm32-gpio-state"); 853 854 shift_1b = gpio->pin; 855 shift_2b = SHIFT_U32(gpio->pin, 1); 856 857 if (gpio->dt_flags & GPIO_PULL_UP) 858 pupd = GPIO_PUPD_PULL_UP; 859 else if (gpio->dt_flags & GPIO_PULL_DOWN) 860 pupd = GPIO_PUPD_PULL_DOWN; 861 else 862 pupd = GPIO_PUPD_NO_PULL; 863 864 if (gpio->dt_flags & GPIO_LINE_OPEN_DRAIN) 865 otype = GPIO_OTYPE_OPEN_DRAIN; 866 else 867 otype = GPIO_OTYPE_PUSH_PULL; 868 869 if (clk_enable(bank->clock)) 870 panic(); 871 exceptions = cpu_spin_lock_xsave(&gpio_lock); 872 873 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 874 SHIFT_U32(GPIO_MODE_MASK, shift_2b), 875 SHIFT_U32(mode, shift_2b)); 876 877 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, 878 SHIFT_U32(GPIO_OTYPE_OPEN_DRAIN, shift_1b), 879 SHIFT_U32(otype, shift_1b)); 880 881 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, 882 SHIFT_U32(GPIO_PUPD_PULL_MASK, shift_2b), 883 SHIFT_U32(pupd, shift_2b)); 884 885 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 886 clk_disable(bank->clock); 887 888 gpio->chip = &bank->gpio_chip; 889 890 *out_gpio = gpio; 891 892 return TEE_SUCCESS; 893 } 894 895 /* Get bank ID from bank node property st,bank-name or panic on failure */ 896 static unsigned int dt_get_bank_id(const void *fdt, int node) 897 { 898 const int dt_name_len = strlen(DT_GPIO_BANK_NAME0); 899 const fdt32_t *cuint = NULL; 900 int len = 0; 901 902 /* Parse "st,bank-name" to get its id (eg: GPIOA -> 0) */ 903 cuint = fdt_getprop(fdt, node, "st,bank-name", &len); 904 if (!cuint || (len != dt_name_len + 1)) 905 panic("Missing/wrong st,bank-name property"); 906 907 if (strncmp((const char *)cuint, DT_GPIO_BANK_NAME0, dt_name_len - 1) || 908 strcmp((const char *)cuint, DT_GPIO_BANK_NAME0) < 0) 909 panic("Wrong st,bank-name property"); 910 911 return (unsigned int)strcmp((const char *)cuint, DT_GPIO_BANK_NAME0); 912 } 913 914 /* 915 * Return whether or not the GPIO bank related to a DT node is already 916 * registered in the GPIO bank link. 917 */ 918 static bool bank_is_registered(const void *fdt, int node) 919 { 920 unsigned int bank_id = dt_get_bank_id(fdt, node); 921 struct stm32_gpio_bank *bank = NULL; 922 923 STAILQ_FOREACH(bank, &bank_list, link) 924 if (bank->bank_id == bank_id) 925 return true; 926 927 return false; 928 } 929 930 #ifdef CFG_STM32_RIF 931 static TEE_Result handle_available_semaphores(struct stm32_gpio_bank *bank, 932 uint32_t gpios_mask) 933 { 934 TEE_Result res = TEE_ERROR_GENERIC; 935 uint32_t cidcfgr = 0; 936 unsigned int i = 0; 937 938 for (i = 0 ; i < bank->ngpios; i++) { 939 if (!(BIT(i) & gpios_mask)) 940 continue; 941 942 cidcfgr = io_read32(bank->base + GPIO_CIDCFGR(i)); 943 944 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) 945 continue; 946 947 if (!(io_read32(bank->base + GPIO_SECR_OFFSET) & BIT(i))) { 948 res = stm32_rif_release_semaphore(bank->base + 949 GPIO_SEMCR(i), 950 MAX_CID_SUPPORTED); 951 if (res) { 952 EMSG("Cannot release semaphore for resource %u", 953 i); 954 return res; 955 } 956 } else { 957 res = stm32_rif_acquire_semaphore(bank->base + 958 GPIO_SEMCR(i), 959 MAX_CID_SUPPORTED); 960 if (res) { 961 EMSG("Cannot acquire semaphore for resource %u", 962 i); 963 return res; 964 } 965 } 966 } 967 968 return TEE_SUCCESS; 969 } 970 971 static TEE_Result apply_rif_config(struct stm32_gpio_bank *bank, 972 uint32_t gpios_mask) 973 { 974 TEE_Result res = TEE_ERROR_GENERIC; 975 unsigned int i = 0; 976 977 if (!bank->rif_cfg) 978 return TEE_SUCCESS; 979 980 if (clk_enable(bank->clock)) 981 panic(); 982 983 if (bank->is_tdcid) { 984 for (i = 0; i < bank->ngpios; i++) { 985 if (!(BIT(i) & gpios_mask)) 986 continue; 987 988 /* 989 * When TDCID, OP-TEE should be the one to set the CID 990 * filtering configuration. Clearing previous 991 * configuration prevents undesired events during the 992 * only legitimate configuration. 993 */ 994 io_clrbits32(bank->base + GPIO_CIDCFGR(i), 995 GPIO_CIDCFGR_CONF_MASK); 996 } 997 } else { 998 res = handle_available_semaphores(bank, gpios_mask); 999 if (res) 1000 panic(); 1001 } 1002 1003 /* Security and privilege RIF configuration */ 1004 io_mask32(bank->base + GPIO_PRIVCFGR_OFFSET, 1005 bank->rif_cfg->priv_conf[0], gpios_mask); 1006 io_mask32(bank->base + GPIO_SECR_OFFSET, 1007 bank->rif_cfg->sec_conf[0], gpios_mask); 1008 1009 if (!bank->is_tdcid) { 1010 res = TEE_SUCCESS; 1011 goto out; 1012 } 1013 1014 for (i = 0; i < bank->ngpios; i++) { 1015 if (!(BIT(i) & gpios_mask)) 1016 continue; 1017 1018 io_clrsetbits32(bank->base + GPIO_CIDCFGR(i), 1019 GPIO_CIDCFGR_CONF_MASK, 1020 bank->rif_cfg->cid_confs[i]); 1021 } 1022 1023 /* 1024 * Lock RIF configuration if configured. This cannot be undone until 1025 * next reset. 1026 */ 1027 io_setbits32(bank->base + GPIO_RCFGLOCKR_OFFSET, 1028 bank->rif_cfg->lock_conf[0]); 1029 1030 res = handle_available_semaphores(bank, gpios_mask); 1031 if (res) 1032 panic(); 1033 1034 out: 1035 if (IS_ENABLED(CFG_TEE_CORE_DEBUG)) { 1036 /* Check that RIF config are applied, panic otherwise */ 1037 if ((io_read32(bank->base + GPIO_PRIVCFGR_OFFSET) & 1038 gpios_mask) != 1039 (bank->rif_cfg->priv_conf[0] & gpios_mask)) { 1040 EMSG("GPIO bank%c priv conf is incorrect", 1041 'A' + bank->bank_id); 1042 panic(); 1043 } 1044 1045 if ((io_read32(bank->base + GPIO_SECR_OFFSET) & gpios_mask) != 1046 (bank->rif_cfg->sec_conf[0] & gpios_mask)) { 1047 EMSG("GPIO bank %c sec conf is incorrect", 1048 'A' + bank->bank_id); 1049 panic(); 1050 } 1051 } 1052 1053 clk_disable(bank->clock); 1054 1055 return res; 1056 } 1057 #else /* CFG_STM32_RIF */ 1058 static TEE_Result apply_rif_config(struct stm32_gpio_bank *bank __unused, 1059 uint32_t gpios_mask __unused) 1060 { 1061 return TEE_SUCCESS; 1062 } 1063 #endif /* CFG_STM32_RIF */ 1064 1065 /* Forward reference to stm32_gpio_set_conf_sec() defined below */ 1066 static void stm32_gpio_set_conf_sec(struct stm32_gpio_bank *bank); 1067 1068 static TEE_Result stm32_gpio_fw_configure(struct firewall_query *firewall) 1069 { 1070 struct stm32_gpio_bank *bank = firewall->ctrl->priv; 1071 uint32_t firewall_arg = 0; 1072 uint32_t gpios_mask = 0; 1073 bool secure = true; 1074 1075 assert(bank->sec_support); 1076 1077 if (firewall->arg_count != 1) 1078 return TEE_ERROR_BAD_PARAMETERS; 1079 1080 firewall_arg = firewall->args[0]; 1081 1082 if (bank->rif_cfg) { 1083 gpios_mask = BIT(RIF_CHANNEL_ID(firewall_arg)); 1084 1085 /* We're about to change a specific GPIO config */ 1086 bank->rif_cfg->access_mask[0] |= gpios_mask; 1087 1088 /* 1089 * Update bank RIF config with firewall configuration data 1090 * and apply it. 1091 */ 1092 stm32_rif_parse_cfg(firewall_arg, bank->rif_cfg, 1093 bank->ngpios); 1094 return apply_rif_config(bank, gpios_mask); 1095 } 1096 1097 /* 1098 * Non RIF GPIO banks use a single cell as a bit mask (bits 0 to 15) 1099 * to define the a group of GPIO pins (one or several) to configure 1100 * for that bank, and GPIO_STM32_NSEC bit flag to set if these pins 1101 * are non-secure (flag set) or non-secure (flag cleared). 1102 */ 1103 gpios_mask = firewall_arg & GENMASK_32(15, 0); 1104 1105 secure = !(firewall_arg & GPIO_STM32_NSEC); 1106 1107 if (gpios_mask & ~GENMASK_32(bank->ngpios, 0)) { 1108 EMSG("Invalid bitmask %#"PRIx32" for GPIO bank %c", 1109 gpios_mask, 'A' + bank->bank_id); 1110 return TEE_ERROR_GENERIC; 1111 } 1112 1113 /* Update bank secure register configuration data and apply it */ 1114 if (secure) 1115 bank->seccfgr |= gpios_mask; 1116 else 1117 bank->seccfgr &= ~gpios_mask; 1118 1119 stm32_gpio_set_conf_sec(bank); 1120 1121 return TEE_SUCCESS; 1122 } 1123 1124 static const struct firewall_controller_ops stm32_gpio_firewall_ops = { 1125 .set_conf = stm32_gpio_fw_configure, 1126 }; 1127 1128 static void stm32_gpio_save_rif_config(struct stm32_gpio_bank *bank) 1129 { 1130 size_t i = 0; 1131 1132 for (i = 0; i < bank->ngpios; i++) 1133 bank->rif_cfg->cid_confs[i] = io_read32(bank->base + 1134 GPIO_CIDCFGR(i)); 1135 1136 bank->rif_cfg->priv_conf[0] = io_read32(bank->base + 1137 GPIO_PRIVCFGR_OFFSET); 1138 bank->rif_cfg->sec_conf[0] = io_read32(bank->base + 1139 GPIO_SECR_OFFSET); 1140 bank->rif_cfg->lock_conf[0] = io_read32(bank->base + 1141 GPIO_RCFGLOCKR_OFFSET); 1142 } 1143 1144 static void stm32_parse_gpio_rif_conf(struct stm32_gpio_bank *bank, 1145 const void *fdt, int node) 1146 { 1147 unsigned int i = 0; 1148 unsigned int nb_rif_conf = 0; 1149 int lenp = 0; 1150 const fdt32_t *cuint = NULL; 1151 1152 cuint = fdt_getprop(fdt, node, "st,protreg", &lenp); 1153 if (!cuint) { 1154 DMSG("No RIF configuration available"); 1155 return; 1156 } 1157 1158 bank->rif_cfg = calloc(1, sizeof(*bank->rif_cfg)); 1159 if (!bank->rif_cfg) 1160 panic(); 1161 1162 bank->rif_cfg->sec_conf = calloc(1, sizeof(uint32_t)); 1163 if (!bank->rif_cfg->sec_conf) 1164 panic(); 1165 1166 nb_rif_conf = (unsigned int)(lenp / sizeof(uint32_t)); 1167 assert(nb_rif_conf <= bank->ngpios); 1168 1169 bank->rif_cfg->cid_confs = calloc(bank->ngpios, sizeof(uint32_t)); 1170 bank->rif_cfg->priv_conf = calloc(1, sizeof(uint32_t)); 1171 bank->rif_cfg->lock_conf = calloc(1, sizeof(uint32_t)); 1172 bank->rif_cfg->access_mask = calloc(1, sizeof(uint32_t)); 1173 if (!bank->rif_cfg->cid_confs || !bank->rif_cfg->access_mask || 1174 !bank->rif_cfg->priv_conf || !bank->rif_cfg->lock_conf) 1175 panic("Missing memory capacity for GPIOS RIF configuration"); 1176 1177 for (i = 0; i < nb_rif_conf; i++) 1178 stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), bank->rif_cfg, 1179 bank->ngpios); 1180 } 1181 1182 /* Get GPIO bank information from the DT */ 1183 static TEE_Result dt_stm32_gpio_bank(const void *fdt, int node, 1184 const void *compat_data, 1185 int range_offset, 1186 struct stm32_gpio_bank **out_bank) 1187 { 1188 const struct bank_compat *compat = compat_data; 1189 TEE_Result res = TEE_ERROR_GENERIC; 1190 struct stm32_gpio_bank *bank = NULL; 1191 const fdt32_t *cuint = NULL; 1192 struct io_pa_va pa_va = { }; 1193 struct clk *clk = NULL; 1194 size_t blen = 0; 1195 paddr_t pa = 0; 1196 int len = 0; 1197 int i = 0; 1198 1199 assert(out_bank); 1200 1201 /* Probe deferrable devices first */ 1202 res = clk_dt_get_by_index(fdt, node, 0, &clk); 1203 if (res) 1204 return res; 1205 1206 bank = calloc(1, sizeof(*bank)); 1207 if (!bank) 1208 return TEE_ERROR_OUT_OF_MEMORY; 1209 1210 if (compat->secure_extended) { 1211 res = stm32_rifsc_check_tdcid(&bank->is_tdcid); 1212 if (res) { 1213 free(bank); 1214 return res; 1215 } 1216 } 1217 1218 /* 1219 * Do not rely *only* on the "reg" property to get the address, 1220 * but consider also the "ranges" translation property 1221 */ 1222 if (fdt_reg_info(fdt, node, &pa, &blen)) 1223 panic("missing reg or reg size property"); 1224 1225 pa_va.pa = pa + range_offset; 1226 1227 DMSG("Bank name %s", fdt_get_name(fdt, node, NULL)); 1228 bank->bank_id = dt_get_bank_id(fdt, node); 1229 bank->clock = clk; 1230 bank->gpio_chip.ops = &stm32_gpio_ops; 1231 bank->sec_support = compat->secure_control; 1232 1233 /* Parse gpio-ranges with its 4 parameters */ 1234 cuint = fdt_getprop(fdt, node, "gpio-ranges", &len); 1235 len /= sizeof(*cuint); 1236 if (len % 4) 1237 panic("wrong gpio-ranges syntax"); 1238 1239 /* Get the last defined gpio line (offset + nb of pins) */ 1240 for (i = 0; i < len / 4; i++) { 1241 bank->ngpios = MAX(bank->ngpios, 1242 (unsigned int)(fdt32_to_cpu(*(cuint + 1)) + 1243 fdt32_to_cpu(*(cuint + 3)))); 1244 cuint += 4; 1245 } 1246 1247 if (compat->secure_extended) { 1248 /* RIF configuration */ 1249 bank->base = io_pa_or_va_secure(&pa_va, blen); 1250 1251 stm32_parse_gpio_rif_conf(bank, fdt, node); 1252 } else if (bank->sec_support) { 1253 /* Secure configuration */ 1254 bank->base = io_pa_or_va_secure(&pa_va, blen); 1255 cuint = fdt_getprop(fdt, node, "st,protreg", NULL); 1256 if (cuint) 1257 bank->seccfgr = fdt32_to_cpu(*cuint); 1258 else 1259 DMSG("GPIO bank %c assigned to non-secure", 1260 bank->bank_id + 'A'); 1261 } else { 1262 bank->base = io_pa_or_va_nsec(&pa_va, blen); 1263 } 1264 1265 *out_bank = bank; 1266 1267 return TEE_SUCCESS; 1268 } 1269 1270 static TEE_Result stm32_gpio_firewall_register(const void *fdt, int node, 1271 struct stm32_gpio_bank *bank) 1272 { 1273 struct firewall_controller *controller = NULL; 1274 TEE_Result res = TEE_ERROR_GENERIC; 1275 char bank_name[] = "gpio-bank-X"; 1276 char *name = NULL; 1277 1278 if (!IS_ENABLED(CFG_DRIVERS_FIREWALL) || 1279 !bank->sec_support) 1280 return TEE_SUCCESS; 1281 1282 controller = calloc(1, sizeof(*controller)); 1283 if (!controller) 1284 return TEE_ERROR_OUT_OF_MEMORY; 1285 1286 bank_name[sizeof(bank_name) - 2] = 'A' + bank->bank_id; 1287 name = strdup(bank_name); 1288 1289 controller->name = name; 1290 controller->priv = bank; 1291 controller->ops = &stm32_gpio_firewall_ops; 1292 1293 if (!controller->name) 1294 EMSG("Warning: out of memory to store bank name"); 1295 1296 res = firewall_dt_controller_register(fdt, node, controller); 1297 if (res) { 1298 free(name); 1299 free(controller); 1300 } 1301 1302 return res; 1303 } 1304 1305 /* Parse a pinctrl node to register the GPIO banks it describes */ 1306 static TEE_Result dt_stm32_gpio_pinctrl(const void *fdt, int node, 1307 const void *compat_data) 1308 { 1309 TEE_Result res = TEE_SUCCESS; 1310 const fdt32_t *cuint = NULL; 1311 int range_offs = 0; 1312 int b_node = 0; 1313 int len = 0; 1314 1315 /* Read the ranges property (for regs memory translation) */ 1316 cuint = fdt_getprop(fdt, node, "ranges", &len); 1317 if (!cuint) 1318 panic("missing ranges property"); 1319 1320 len /= sizeof(*cuint); 1321 if (len == 3) 1322 range_offs = fdt32_to_cpu(*(cuint + 1)) - fdt32_to_cpu(*cuint); 1323 1324 fdt_for_each_subnode(b_node, fdt, node) { 1325 cuint = fdt_getprop(fdt, b_node, "gpio-controller", &len); 1326 if (cuint) { 1327 /* 1328 * We found a property "gpio-controller" in the node: 1329 * the node is a GPIO bank description, add it to the 1330 * bank list. 1331 */ 1332 struct stm32_gpio_bank *bank = NULL; 1333 1334 if (fdt_get_status(fdt, b_node) == DT_STATUS_DISABLED || 1335 bank_is_registered(fdt, b_node)) 1336 continue; 1337 1338 res = dt_stm32_gpio_bank(fdt, b_node, compat_data, 1339 range_offs, &bank); 1340 if (res) 1341 return res; 1342 1343 /* Registering a provider should not defer probe */ 1344 res = gpio_register_provider(fdt, b_node, 1345 stm32_gpio_get_dt, bank); 1346 if (res) 1347 panic(); 1348 1349 res = stm32_gpio_firewall_register(fdt, b_node, bank); 1350 if (res) 1351 panic(); 1352 1353 STAILQ_INSERT_TAIL(&bank_list, bank, link); 1354 } else { 1355 if (len != -FDT_ERR_NOTFOUND) 1356 panic(); 1357 } 1358 } 1359 1360 return TEE_SUCCESS; 1361 } 1362 1363 #ifdef CFG_DRIVERS_PINCTRL 1364 static TEE_Result stm32_pinctrl_conf_apply(struct pinconf *conf) 1365 { 1366 struct stm32_pinctrl_array *ref = conf->priv; 1367 struct stm32_pinctrl *p = ref->pinctrl; 1368 struct stm32_gpio_bank *bank = NULL; 1369 TEE_Result res = TEE_ERROR_GENERIC; 1370 size_t pin_count = ref->count; 1371 size_t n = 0; 1372 bool error = false; 1373 1374 for (n = 0; n < pin_count; n++) { 1375 bank = stm32_gpio_get_bank(p[n].bank); 1376 1377 if (!pin_is_accessible(bank, p[n].pin)) { 1378 EMSG("Apply pinctrl for pin %c%u that cannot be accessed", 1379 p[n].bank + 'A', p[n].pin); 1380 error = true; 1381 continue; 1382 } 1383 1384 res = acquire_rif_semaphore_if_needed(bank, p[n].pin); 1385 if (res) { 1386 EMSG("Failed to acquire GPIO %c%u semaphore", 1387 bank->bank_id + 'A', p[n].pin); 1388 error = true; 1389 continue; 1390 } 1391 1392 if (p[n].cfg.nsec == !pin_is_secure(bank, p[n].pin)) 1393 continue; 1394 1395 if (IS_ENABLED(CFG_INSECURE)) { 1396 IMSG("WARNING: apply pinctrl for %ssecure pin %c%u that is %ssecure", 1397 p[n].cfg.nsec ? "non-" : "", 1398 p[n].bank + 'A', p[n].pin, 1399 pin_is_secure(bank, p[n].pin) ? "" : "non-"); 1400 } else { 1401 EMSG("Apply pinctrl for %ssecure pin %c%u that is %ssecure", 1402 p[n].cfg.nsec ? "non-" : "", 1403 p[n].bank + 'A', p[n].pin, 1404 pin_is_secure(bank, p[n].pin) ? "" : "non-"); 1405 error = true; 1406 } 1407 } 1408 1409 if (error) { 1410 for (n = 0; n < pin_count; n++) { 1411 bank = stm32_gpio_get_bank(p[n].bank); 1412 release_rif_semaphore_if_acquired(bank, p[n].pin); 1413 } 1414 1415 return TEE_ERROR_SECURITY; 1416 } 1417 1418 for (n = 0; n < pin_count; n++) 1419 set_gpio_cfg(p[n].bank, p[n].pin, &p[n].cfg); 1420 1421 return TEE_SUCCESS; 1422 } 1423 1424 static void stm32_pinctrl_conf_free(struct pinconf *conf) 1425 { 1426 free(conf); 1427 } 1428 1429 static const struct pinctrl_ops stm32_pinctrl_ops = { 1430 .conf_apply = stm32_pinctrl_conf_apply, 1431 .conf_free = stm32_pinctrl_conf_free, 1432 }; 1433 1434 DECLARE_KEEP_PAGER(stm32_pinctrl_ops); 1435 1436 void stm32_gpio_pinctrl_bank_pin(struct pinctrl_state *pinctrl, 1437 unsigned int *bank, unsigned int *pin, 1438 unsigned int *count) 1439 { 1440 size_t conf_index = 0; 1441 size_t pin_count = 0; 1442 size_t n = 0; 1443 1444 assert(count); 1445 if (!pinctrl) 1446 goto out; 1447 1448 for (conf_index = 0; conf_index < pinctrl->conf_count; conf_index++) { 1449 struct pinconf *pinconf = pinctrl->confs[conf_index]; 1450 struct stm32_pinctrl_array *ref = pinconf->priv; 1451 1452 /* Consider only the stm32_gpio pins */ 1453 if (pinconf->ops != &stm32_pinctrl_ops) 1454 continue; 1455 1456 if (bank || pin) { 1457 for (n = 0; n < ref->count; n++) { 1458 if (bank && pin_count < *count) 1459 bank[pin_count] = ref->pinctrl[n].bank; 1460 if (pin && pin_count < *count) 1461 pin[pin_count] = ref->pinctrl[n].pin; 1462 pin_count++; 1463 } 1464 } else { 1465 pin_count += ref->count; 1466 } 1467 } 1468 1469 out: 1470 *count = pin_count; 1471 } 1472 1473 /* Allocate and return a pinctrl configuration from a DT reference */ 1474 static TEE_Result stm32_pinctrl_dt_get(struct dt_pargs *pargs, 1475 void *data __unused, 1476 struct pinconf **out_pinconf) 1477 { 1478 struct conf { 1479 struct pinconf pinconf; 1480 struct stm32_pinctrl_array array_ref; 1481 } *loc_conf = NULL; 1482 struct stm32_pinctrl *pinctrl = NULL; 1483 struct pinconf *pinconf = NULL; 1484 const void *fdt = NULL; 1485 size_t pin_count = 0; 1486 int pinctrl_node = 0; 1487 int pinmux_node = 0; 1488 int count = 0; 1489 1490 pinctrl_node = pargs->phandle_node; 1491 fdt = pargs->fdt; 1492 assert(fdt && pinctrl_node); 1493 1494 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 1495 if (fdt_getprop(fdt, pinmux_node, "pinmux", &count)) 1496 pin_count += (size_t)count / sizeof(uint32_t); 1497 else if (count != -FDT_ERR_NOTFOUND) 1498 panic(); 1499 } 1500 1501 loc_conf = calloc(1, sizeof(*loc_conf) + sizeof(*pinctrl) * pin_count); 1502 if (!loc_conf) 1503 return TEE_ERROR_OUT_OF_MEMORY; 1504 1505 pinconf = &loc_conf->pinconf; 1506 pinconf->ops = &stm32_pinctrl_ops; 1507 pinconf->priv = &loc_conf->array_ref; 1508 1509 loc_conf->array_ref.count = pin_count; 1510 pinctrl = loc_conf->array_ref.pinctrl; 1511 1512 count = 0; 1513 fdt_for_each_subnode(pinmux_node, fdt, pinctrl_node) { 1514 int found = 0; 1515 1516 found = get_pinctrl_from_fdt(fdt, pinmux_node, 1517 pargs->consumer_node, 1518 pinctrl + count, 1519 pin_count - count); 1520 if (found <= 0 && found > ((int)pin_count - count)) { 1521 /* We can't recover from an error here so let's panic */ 1522 panic(); 1523 } 1524 1525 count += found; 1526 } 1527 1528 *out_pinconf = pinconf; 1529 1530 return TEE_SUCCESS; 1531 } 1532 #endif /*CFG_DRIVERS_PINCTRL*/ 1533 1534 static void stm32_gpio_get_conf_sec(struct stm32_gpio_bank *bank) 1535 { 1536 if (bank->sec_support) { 1537 clk_enable(bank->clock); 1538 bank->seccfgr = io_read32(bank->base + GPIO_SECR_OFFSET); 1539 clk_disable(bank->clock); 1540 } 1541 } 1542 1543 static void stm32_gpio_set_conf_sec(struct stm32_gpio_bank *bank) 1544 { 1545 if (bank->sec_support) { 1546 clk_enable(bank->clock); 1547 io_write32(bank->base + GPIO_SECR_OFFSET, bank->seccfgr); 1548 clk_disable(bank->clock); 1549 } 1550 } 1551 1552 static TEE_Result stm32_gpio_sec_config_resume(void) 1553 { 1554 TEE_Result res = TEE_ERROR_GENERIC; 1555 struct stm32_gpio_bank *bank = NULL; 1556 1557 STAILQ_FOREACH(bank, &bank_list, link) { 1558 if (bank->rif_cfg) { 1559 if (!bank->is_tdcid) 1560 continue; 1561 1562 bank->rif_cfg->access_mask[0] = GENMASK_32(bank->ngpios, 1563 0); 1564 1565 res = apply_rif_config(bank, 1566 bank->rif_cfg->access_mask[0]); 1567 if (res) { 1568 EMSG("Failed to set GPIO bank %c RIF config", 1569 'A' + bank->bank_id); 1570 return res; 1571 } 1572 } else { 1573 stm32_gpio_set_conf_sec(bank); 1574 } 1575 } 1576 1577 return TEE_SUCCESS; 1578 } 1579 1580 static TEE_Result stm32_gpio_sec_config_suspend(void) 1581 { 1582 struct stm32_gpio_bank *bank = NULL; 1583 1584 STAILQ_FOREACH(bank, &bank_list, link) { 1585 if (bank->rif_cfg) { 1586 if (bank->is_tdcid) 1587 stm32_gpio_save_rif_config(bank); 1588 } else { 1589 stm32_gpio_get_conf_sec(bank); 1590 } 1591 } 1592 1593 return TEE_SUCCESS; 1594 } 1595 1596 static TEE_Result 1597 stm32_gpio_sec_config_pm(enum pm_op op, unsigned int pm_hint, 1598 const struct pm_callback_handle *hdl __unused) 1599 { 1600 TEE_Result ret = TEE_ERROR_GENERIC; 1601 1602 if (!PM_HINT_IS_STATE(pm_hint, CONTEXT)) 1603 return TEE_SUCCESS; 1604 1605 if (op == PM_OP_RESUME) 1606 ret = stm32_gpio_sec_config_resume(); 1607 else 1608 ret = stm32_gpio_sec_config_suspend(); 1609 1610 return ret; 1611 } 1612 DECLARE_KEEP_PAGER(stm32_gpio_sec_config_pm); 1613 1614 /* 1615 * Several pinctrl nodes can be probed. Their bank will be put in the unique 1616 * bank_list. To avoid multiple configuration set for a bank when looping 1617 * over each bank in the bank list, ready is set to true when a bank is 1618 * configured. Therefore, during other bank probes, the configuration won't 1619 * be set again. 1620 */ 1621 static TEE_Result apply_sec_cfg(void) 1622 { 1623 TEE_Result res = TEE_ERROR_GENERIC; 1624 struct stm32_gpio_bank *bank = NULL; 1625 unsigned int pin = 0; 1626 1627 STAILQ_FOREACH(bank, &bank_list, link) { 1628 if (bank->ready) 1629 continue; 1630 1631 if (bank->rif_cfg) { 1632 res = apply_rif_config(bank, 1633 bank->rif_cfg->access_mask[0]); 1634 if (res) { 1635 EMSG("Failed to set GPIO bank %c RIF config", 1636 'A' + bank->bank_id); 1637 STAILQ_REMOVE(&bank_list, bank, stm32_gpio_bank, 1638 link); 1639 free(bank); 1640 return res; 1641 } 1642 1643 /* 1644 * Semaphores for pinctrl and GPIO are taken when 1645 * these are used (pinctrl state applied, GPIO 1646 * consumed) or when an explicit firewall configuration 1647 * is requested through the firewall framework. 1648 * Therefore release here the taken semaphores. 1649 */ 1650 for (pin = 0; pin < bank->ngpios; pin++) 1651 release_rif_semaphore_if_acquired(bank, pin); 1652 1653 } else { 1654 stm32_gpio_set_conf_sec(bank); 1655 } 1656 1657 bank->ready = true; 1658 } 1659 1660 return TEE_SUCCESS; 1661 } 1662 1663 static TEE_Result stm32_pinctrl_probe(const void *fdt, int node, 1664 const void *compat_data) 1665 { 1666 static bool pm_register; 1667 TEE_Result res = TEE_ERROR_GENERIC; 1668 1669 /* Register GPIO banks described in this pin control node */ 1670 res = dt_stm32_gpio_pinctrl(fdt, node, compat_data); 1671 if (res) 1672 return res; 1673 1674 if (STAILQ_EMPTY(&bank_list)) 1675 DMSG("no gpio bank for that driver"); 1676 else if (apply_sec_cfg()) 1677 panic(); 1678 1679 if (!pm_register) { 1680 /* 1681 * Register to PM once for all probed banks to restore 1682 * their secure configuration. 1683 */ 1684 register_pm_driver_cb(stm32_gpio_sec_config_pm, NULL, 1685 "stm32-gpio-secure-config"); 1686 pm_register = true; 1687 } 1688 1689 #ifdef CFG_DRIVERS_PINCTRL 1690 res = pinctrl_register_provider(fdt, node, stm32_pinctrl_dt_get, 1691 (void *)compat_data); 1692 if (res) 1693 panic(); 1694 #endif 1695 1696 return TEE_SUCCESS; 1697 } 1698 1699 static const struct dt_device_match stm32_pinctrl_match_table[] = { 1700 { 1701 .compatible = "st,stm32mp135-pinctrl", 1702 .compat_data = &(struct bank_compat){ 1703 .secure_control = true, 1704 .secure_extended = false, 1705 }, 1706 }, 1707 { 1708 .compatible = "st,stm32mp157-pinctrl", 1709 .compat_data = &(struct bank_compat){ 1710 .secure_control = false, 1711 .secure_extended = false, 1712 }, 1713 }, 1714 { 1715 .compatible = "st,stm32mp157-z-pinctrl", 1716 .compat_data = &(struct bank_compat){ 1717 .gpioz = true, 1718 .secure_control = true, 1719 .secure_extended = false, 1720 }, 1721 }, 1722 { 1723 .compatible = "st,stm32mp257-pinctrl", 1724 .compat_data = &(struct bank_compat){ 1725 .secure_control = true, 1726 .secure_extended = true, 1727 }, 1728 }, 1729 { 1730 .compatible = "st,stm32mp257-z-pinctrl", 1731 .compat_data = &(struct bank_compat){ 1732 .gpioz = true, 1733 .secure_control = true, 1734 .secure_extended = true, 1735 }, 1736 }, 1737 { } 1738 }; 1739 1740 DEFINE_DT_DRIVER(stm32_pinctrl_dt_driver) = { 1741 .name = "stm32_gpio-pinctrl", 1742 .type = DT_DRIVER_PINCTRL, 1743 .match_table = stm32_pinctrl_match_table, 1744 .probe = stm32_pinctrl_probe, 1745 }; 1746