1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2023, STMicroelectronics 4 * 5 * STM32 GPIO driver is used as pin controller for stm32mp SoCs. 6 */ 7 8 #include <assert.h> 9 #include <drivers/clk.h> 10 #include <drivers/clk_dt.h> 11 #include <drivers/gpio.h> 12 #include <drivers/stm32_gpio.h> 13 #include <io.h> 14 #include <kernel/dt.h> 15 #include <kernel/boot.h> 16 #include <kernel/panic.h> 17 #include <kernel/spinlock.h> 18 #include <libfdt.h> 19 #include <mm/core_memprot.h> 20 #include <stdbool.h> 21 #include <stm32_util.h> 22 #include <sys/queue.h> 23 #include <trace.h> 24 #include <util.h> 25 26 #ifndef CFG_DRIVERS_GPIO 27 #error stm32_gpio driver expects CFG_DRIVERS_GPIO 28 #endif 29 30 #define GPIO_PIN_MAX 15 31 32 #define GPIO_MODER_OFFSET 0x00 33 #define GPIO_OTYPER_OFFSET 0x04 34 #define GPIO_OSPEEDR_OFFSET 0x08 35 #define GPIO_PUPDR_OFFSET 0x0c 36 #define GPIO_IDR_OFFSET 0x10 37 #define GPIO_ODR_OFFSET 0x14 38 #define GPIO_BSRR_OFFSET 0x18 39 #define GPIO_AFRL_OFFSET 0x20 40 #define GPIO_AFRH_OFFSET 0x24 41 #define GPIO_SECR_OFFSET 0x30 42 43 #define GPIO_ALT_LOWER_LIMIT 0x8 44 45 #define GPIO_MODE_MASK GENMASK_32(1, 0) 46 #define GPIO_OSPEED_MASK GENMASK_32(1, 0) 47 #define GPIO_PUPD_PULL_MASK GENMASK_32(1, 0) 48 #define GPIO_ALTERNATE_MASK GENMASK_32(3, 0) 49 50 #define DT_GPIO_BANK_SHIFT 12 51 #define DT_GPIO_BANK_MASK GENMASK_32(16, 12) 52 #define DT_GPIO_PIN_SHIFT 8 53 #define DT_GPIO_PIN_MASK GENMASK_32(11, 8) 54 #define DT_GPIO_MODE_MASK GENMASK_32(7, 0) 55 56 #define DT_GPIO_BANK_NAME0 "GPIOA" 57 58 /** 59 * struct stm32_gpio_bank - GPIO bank instance 60 * 61 * @base: base address of the GPIO controller registers. 62 * @clock: clock identifier. 63 * @gpio_chip: GPIO chip reference for that GPIO bank 64 * @ngpios: number of GPIOs. 65 * @bank_id: Id of the bank. 66 * @lock: lock protecting the GPIO bank access. 67 * @sec_support: True if bank supports pin security protection, otherwise false 68 * @seccfgr: Secure configuration register value. 69 * @link: Link in bank list 70 */ 71 struct stm32_gpio_bank { 72 vaddr_t base; 73 struct clk *clock; 74 struct gpio_chip gpio_chip; 75 unsigned int ngpios; 76 unsigned int bank_id; 77 unsigned int lock; 78 STAILQ_ENTRY(stm32_gpio_bank) link; 79 }; 80 81 static unsigned int gpio_lock; 82 83 static STAILQ_HEAD(, stm32_gpio_bank) bank_list = 84 STAILQ_HEAD_INITIALIZER(bank_list); 85 86 static bool is_stm32_gpio_chip(struct gpio_chip *chip); 87 88 static struct stm32_gpio_bank *gpio_chip_to_bank(struct gpio_chip *chip) 89 { 90 return container_of(chip, struct stm32_gpio_bank, gpio_chip); 91 } 92 93 static enum gpio_level stm32_gpio_get_level(struct gpio_chip *chip, 94 unsigned int gpio_pin) 95 { 96 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 97 enum gpio_level level = GPIO_LEVEL_HIGH; 98 unsigned int reg_offset = 0; 99 unsigned int mode = 0; 100 101 assert(gpio_pin < bank->ngpios); 102 clk_enable(bank->clock); 103 104 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 105 GPIO_MODE_MASK; 106 107 switch (mode) { 108 case GPIO_MODE_INPUT: 109 reg_offset = GPIO_IDR_OFFSET; 110 break; 111 case GPIO_MODE_OUTPUT: 112 reg_offset = GPIO_ODR_OFFSET; 113 break; 114 default: 115 panic(); 116 } 117 118 if (io_read32(bank->base + reg_offset) & BIT(gpio_pin)) 119 level = GPIO_LEVEL_HIGH; 120 else 121 level = GPIO_LEVEL_LOW; 122 123 clk_disable(bank->clock); 124 125 return level; 126 } 127 128 static void stm32_gpio_set_level(struct gpio_chip *chip, unsigned int gpio_pin, 129 enum gpio_level level) 130 { 131 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 132 133 assert(gpio_pin < bank->ngpios); 134 clk_enable(bank->clock); 135 136 assert(((io_read32(bank->base + GPIO_MODER_OFFSET) >> 137 (gpio_pin << 1)) & GPIO_MODE_MASK) == GPIO_MODE_OUTPUT); 138 139 if (level == GPIO_LEVEL_HIGH) 140 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin)); 141 else 142 io_write32(bank->base + GPIO_BSRR_OFFSET, BIT(gpio_pin + 16)); 143 144 clk_disable(bank->clock); 145 } 146 147 static enum gpio_dir stm32_gpio_get_direction(struct gpio_chip *chip, 148 unsigned int gpio_pin) 149 { 150 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 151 uint32_t mode = 0; 152 153 assert(gpio_pin < bank->ngpios); 154 clk_enable(bank->clock); 155 156 mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (gpio_pin << 1)) & 157 GPIO_MODE_MASK; 158 159 clk_disable(bank->clock); 160 161 switch (mode) { 162 case GPIO_MODE_INPUT: 163 return GPIO_DIR_IN; 164 case GPIO_MODE_OUTPUT: 165 return GPIO_DIR_OUT; 166 default: 167 panic(); 168 } 169 } 170 171 static void stm32_gpio_set_direction(struct gpio_chip *chip, 172 unsigned int gpio_pin, 173 enum gpio_dir direction) 174 { 175 struct stm32_gpio_bank *bank = gpio_chip_to_bank(chip); 176 uint32_t exceptions = 0; 177 uint32_t mode = 0; 178 179 assert(gpio_pin < bank->ngpios); 180 181 if (direction == GPIO_DIR_IN) 182 mode = GPIO_MODE_INPUT; 183 else 184 mode = GPIO_MODE_OUTPUT; 185 186 clk_enable(bank->clock); 187 exceptions = cpu_spin_lock_xsave(&gpio_lock); 188 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 189 SHIFT_U32(GPIO_MODE_MASK, gpio_pin << 1), 190 SHIFT_U32(mode, gpio_pin << 1)); 191 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 192 clk_disable(bank->clock); 193 } 194 195 static void stm32_gpio_put_gpio(struct gpio_chip *chip __maybe_unused, 196 struct gpio *gpio) 197 { 198 assert(is_stm32_gpio_chip(chip)); 199 free(gpio); 200 } 201 202 static const struct gpio_ops stm32_gpio_ops = { 203 .get_direction = stm32_gpio_get_direction, 204 .set_direction = stm32_gpio_set_direction, 205 .get_value = stm32_gpio_get_level, 206 .set_value = stm32_gpio_set_level, 207 .put = stm32_gpio_put_gpio, 208 }; 209 210 static bool __maybe_unused is_stm32_gpio_chip(struct gpio_chip *chip) 211 { 212 return chip && chip->ops == &stm32_gpio_ops; 213 } 214 215 static struct stm32_gpio_bank *stm32_gpio_get_bank(unsigned int bank_id) 216 { 217 struct stm32_gpio_bank *bank = NULL; 218 219 STAILQ_FOREACH(bank, &bank_list, link) 220 if (bank_id == bank->bank_id) 221 return bank; 222 223 panic(); 224 } 225 226 /* Save to output @cfg the current GPIO (@bank_id/@pin) configuration */ 227 static void get_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 228 { 229 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 230 231 if (clk_enable(bank->clock)) 232 panic(); 233 234 /* 235 * Save GPIO configuration bits spread over the few bank registers. 236 * 1bit fields are accessed at bit position being the pin index. 237 * 2bit fields are accessed at bit position being twice the pin index. 238 * 4bit fields are accessed at bit position being fourth the pin index 239 * but accessed from 2 32bit registers at incremental addresses. 240 */ 241 cfg->mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (pin << 1)) & 242 GPIO_MODE_MASK; 243 244 cfg->otype = (io_read32(bank->base + GPIO_OTYPER_OFFSET) >> pin) & 1; 245 246 cfg->ospeed = (io_read32(bank->base + GPIO_OSPEEDR_OFFSET) >> 247 (pin << 1)) & GPIO_OSPEED_MASK; 248 249 cfg->pupd = (io_read32(bank->base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & 250 GPIO_PUPD_PULL_MASK; 251 252 cfg->od = (io_read32(bank->base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; 253 254 if (pin < GPIO_ALT_LOWER_LIMIT) 255 cfg->af = (io_read32(bank->base + GPIO_AFRL_OFFSET) >> 256 (pin << 2)) & GPIO_ALTERNATE_MASK; 257 else 258 cfg->af = (io_read32(bank->base + GPIO_AFRH_OFFSET) >> 259 ((pin - GPIO_ALT_LOWER_LIMIT) << 2)) & 260 GPIO_ALTERNATE_MASK; 261 262 clk_disable(bank->clock); 263 } 264 265 /* Apply GPIO (@bank/@pin) configuration described by @cfg */ 266 static void set_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) 267 { 268 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 269 uint32_t exceptions = 0; 270 271 if (clk_enable(bank->clock)) 272 panic(); 273 exceptions = cpu_spin_lock_xsave(&gpio_lock); 274 275 /* Load GPIO MODE value, 2bit value shifted by twice the pin number */ 276 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 277 SHIFT_U32(GPIO_MODE_MASK, pin << 1), 278 SHIFT_U32(cfg->mode, pin << 1)); 279 280 /* Load GPIO Output TYPE value, 1bit shifted by pin number value */ 281 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, BIT(pin), 282 SHIFT_U32(cfg->otype, pin)); 283 284 /* Load GPIO Output Speed confguration, 2bit value */ 285 io_clrsetbits32(bank->base + GPIO_OSPEEDR_OFFSET, 286 SHIFT_U32(GPIO_OSPEED_MASK, pin << 1), 287 SHIFT_U32(cfg->ospeed, pin << 1)); 288 289 /* Load GPIO pull configuration, 2bit value */ 290 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, BIT(pin), 291 SHIFT_U32(cfg->pupd, pin << 1)); 292 293 /* Load pin mux Alternate Function configuration, 4bit value */ 294 if (pin < GPIO_ALT_LOWER_LIMIT) { 295 io_clrsetbits32(bank->base + GPIO_AFRL_OFFSET, 296 SHIFT_U32(GPIO_ALTERNATE_MASK, pin << 2), 297 SHIFT_U32(cfg->af, pin << 2)); 298 } else { 299 size_t shift = (pin - GPIO_ALT_LOWER_LIMIT) << 2; 300 301 io_clrsetbits32(bank->base + GPIO_AFRH_OFFSET, 302 SHIFT_U32(GPIO_ALTERNATE_MASK, shift), 303 SHIFT_U32(cfg->af, shift)); 304 } 305 306 /* Load GPIO Output direction confuguration, 1bit */ 307 io_clrsetbits32(bank->base + GPIO_ODR_OFFSET, BIT(pin), cfg->od << pin); 308 309 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 310 clk_disable(bank->clock); 311 } 312 313 void stm32_pinctrl_load_active_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 314 { 315 size_t n = 0; 316 317 for (n = 0; n < cnt; n++) 318 set_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 319 &pinctrl[n].active_cfg); 320 } 321 322 void stm32_pinctrl_load_standby_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 323 { 324 size_t n = 0; 325 326 for (n = 0; n < cnt; n++) 327 set_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 328 &pinctrl[n].standby_cfg); 329 } 330 331 void stm32_pinctrl_store_standby_cfg(struct stm32_pinctrl *pinctrl, size_t cnt) 332 { 333 size_t n = 0; 334 335 for (n = 0; n < cnt; n++) 336 get_gpio_cfg(pinctrl[n].bank, pinctrl[n].pin, 337 &pinctrl[n].standby_cfg); 338 } 339 340 /* Panic if GPIO bank information from platform do not match DTB description */ 341 static void ckeck_gpio_bank(void *fdt, uint32_t bank, int pinctrl_node) 342 { 343 int pinctrl_subnode = 0; 344 345 fdt_for_each_subnode(pinctrl_subnode, fdt, pinctrl_node) { 346 const fdt32_t *cuint = NULL; 347 348 if (fdt_getprop(fdt, pinctrl_subnode, 349 "gpio-controller", NULL) == NULL) 350 continue; 351 352 /* Check bank register offset matches platform assumptions */ 353 cuint = fdt_getprop(fdt, pinctrl_subnode, "reg", NULL); 354 if (fdt32_to_cpu(*cuint) != stm32_get_gpio_bank_offset(bank)) 355 continue; 356 357 /* Check controller is enabled */ 358 if (fdt_get_status(fdt, pinctrl_subnode) == DT_STATUS_DISABLED) 359 panic(); 360 361 return; 362 } 363 364 panic(); 365 } 366 367 /* Count pins described in the DT node and get related data if possible */ 368 static int get_pinctrl_from_fdt(void *fdt, int node, 369 struct stm32_pinctrl *pinctrl, size_t count) 370 { 371 const fdt32_t *cuint, *slewrate; 372 int len = 0; 373 int pinctrl_node = 0; 374 uint32_t i = 0; 375 uint32_t speed = GPIO_OSPEED_LOW; 376 uint32_t pull = GPIO_PUPD_NO_PULL; 377 size_t found = 0; 378 379 cuint = fdt_getprop(fdt, node, "pinmux", &len); 380 if (!cuint) 381 return -FDT_ERR_NOTFOUND; 382 383 pinctrl_node = fdt_parent_offset(fdt, fdt_parent_offset(fdt, node)); 384 if (pinctrl_node < 0) 385 return -FDT_ERR_NOTFOUND; 386 387 slewrate = fdt_getprop(fdt, node, "slew-rate", NULL); 388 if (slewrate) 389 speed = fdt32_to_cpu(*slewrate); 390 391 if (fdt_getprop(fdt, node, "bias-pull-up", NULL)) 392 pull = GPIO_PUPD_PULL_UP; 393 if (fdt_getprop(fdt, node, "bias-pull-down", NULL)) 394 pull = GPIO_PUPD_PULL_DOWN; 395 396 for (i = 0; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 397 uint32_t pincfg = 0; 398 uint32_t bank = 0; 399 uint32_t pin = 0; 400 uint32_t mode = 0; 401 uint32_t alternate = 0; 402 uint32_t odata = 0; 403 bool opendrain = false; 404 405 pincfg = fdt32_to_cpu(*cuint); 406 cuint++; 407 408 bank = (pincfg & DT_GPIO_BANK_MASK) >> DT_GPIO_BANK_SHIFT; 409 410 pin = (pincfg & DT_GPIO_PIN_MASK) >> DT_GPIO_PIN_SHIFT; 411 412 mode = pincfg & DT_GPIO_MODE_MASK; 413 414 switch (mode) { 415 case 0: 416 mode = GPIO_MODE_INPUT; 417 break; 418 case 1: 419 case 2: 420 case 3: 421 case 4: 422 case 5: 423 case 6: 424 case 7: 425 case 8: 426 case 9: 427 case 10: 428 case 11: 429 case 12: 430 case 13: 431 case 14: 432 case 15: 433 case 16: 434 alternate = mode - 1U; 435 mode = GPIO_MODE_ALTERNATE; 436 break; 437 case 17: 438 mode = GPIO_MODE_ANALOG; 439 break; 440 default: 441 mode = GPIO_MODE_OUTPUT; 442 break; 443 } 444 445 if (fdt_getprop(fdt, node, "drive-open-drain", NULL)) 446 opendrain = true; 447 448 if (fdt_getprop(fdt, node, "output-high", NULL) && 449 mode == GPIO_MODE_INPUT) { 450 mode = GPIO_MODE_OUTPUT; 451 odata = 1; 452 } 453 454 if (fdt_getprop(fdt, node, "output-low", NULL) && 455 mode == GPIO_MODE_INPUT) { 456 mode = GPIO_MODE_OUTPUT; 457 odata = 0; 458 } 459 460 /* Check GPIO bank clock/base address against platform */ 461 ckeck_gpio_bank(fdt, bank, pinctrl_node); 462 463 if (found < count) { 464 struct stm32_pinctrl *ref = &pinctrl[found]; 465 466 ref->bank = (uint8_t)bank; 467 ref->pin = (uint8_t)pin; 468 ref->active_cfg.mode = mode; 469 ref->active_cfg.otype = opendrain ? 1 : 0; 470 ref->active_cfg.ospeed = speed; 471 ref->active_cfg.pupd = pull; 472 ref->active_cfg.od = odata; 473 ref->active_cfg.af = alternate; 474 /* Default to analog mode for standby state */ 475 ref->standby_cfg.mode = GPIO_MODE_ANALOG; 476 ref->standby_cfg.pupd = GPIO_PUPD_NO_PULL; 477 } 478 479 found++; 480 } 481 482 return (int)found; 483 } 484 485 static struct gpio *stm32_gpio_get_dt(struct dt_pargs *pargs, 486 void *data, TEE_Result *res) 487 { 488 struct stm32_gpio_bank *bank = data; 489 struct gpio *gpio = NULL; 490 unsigned int shift_1b = 0; 491 unsigned int shift_2b = 0; 492 uint32_t exceptions = 0; 493 uint32_t otype = 0; 494 uint32_t pupd = 0; 495 uint32_t mode = 0; 496 497 gpio = gpio_dt_alloc_pin(pargs, res); 498 if (*res) 499 return NULL; 500 501 if (gpio->pin >= bank->ngpios) { 502 DMSG("Invalid GPIO reference"); 503 free(gpio); 504 return NULL; 505 } 506 507 shift_1b = gpio->pin; 508 shift_2b = SHIFT_U32(gpio->pin, 1); 509 510 if (gpio->dt_flags & GPIO_PULL_UP) 511 pupd = GPIO_PUPD_PULL_UP; 512 else if (gpio->dt_flags & GPIO_PULL_DOWN) 513 pupd = GPIO_PUPD_PULL_DOWN; 514 else 515 pupd = GPIO_PUPD_NO_PULL; 516 517 if (gpio->dt_flags & GPIO_LINE_OPEN_DRAIN) 518 otype = GPIO_OTYPE_OPEN_DRAIN; 519 else 520 otype = GPIO_OTYPE_PUSH_PULL; 521 522 if (clk_enable(bank->clock)) 523 panic(); 524 exceptions = cpu_spin_lock_xsave(&gpio_lock); 525 526 io_clrsetbits32(bank->base + GPIO_MODER_OFFSET, 527 SHIFT_U32(GPIO_MODE_MASK, shift_2b), 528 SHIFT_U32(mode, shift_2b)); 529 530 io_clrsetbits32(bank->base + GPIO_OTYPER_OFFSET, 531 SHIFT_U32(GPIO_OTYPE_OPEN_DRAIN, shift_1b), 532 SHIFT_U32(otype, shift_1b)); 533 534 io_clrsetbits32(bank->base + GPIO_PUPDR_OFFSET, 535 SHIFT_U32(GPIO_PUPD_PULL_MASK, shift_2b), 536 SHIFT_U32(pupd, shift_2b)); 537 538 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 539 clk_disable(bank->clock); 540 541 gpio->chip = &bank->gpio_chip; 542 543 *res = TEE_SUCCESS; 544 545 return gpio; 546 } 547 548 /* Get bank ID from bank node property st,bank-name or panic on failure */ 549 static unsigned int dt_get_bank_id(const void *fdt, int node) 550 { 551 const int dt_name_len = strlen(DT_GPIO_BANK_NAME0); 552 const fdt32_t *cuint = NULL; 553 int len = 0; 554 555 /* Parse "st,bank-name" to get its id (eg: GPIOA -> 0) */ 556 cuint = fdt_getprop(fdt, node, "st,bank-name", &len); 557 if (!cuint || (len != dt_name_len + 1)) 558 panic("Missing/wrong st,bank-name property"); 559 560 if (strncmp((const char *)cuint, DT_GPIO_BANK_NAME0, dt_name_len - 1) || 561 strcmp((const char *)cuint, DT_GPIO_BANK_NAME0) < 0) 562 panic("Wrong st,bank-name property"); 563 564 return (unsigned int)strcmp((const char *)cuint, DT_GPIO_BANK_NAME0); 565 } 566 567 /* 568 * Return whether or not the GPIO bank related to a DT node is already 569 * registered in the GPIO bank link. 570 */ 571 static bool bank_is_registered(const void *fdt, int node) 572 { 573 unsigned int bank_id = dt_get_bank_id(fdt, node); 574 struct stm32_gpio_bank *bank = NULL; 575 576 STAILQ_FOREACH(bank, &bank_list, link) 577 if (bank->bank_id == bank_id) 578 return true; 579 580 return false; 581 } 582 583 /* Get GPIO bank information from the DT */ 584 static TEE_Result dt_stm32_gpio_bank(const void *fdt, int node, 585 const void *compat_data __unused, 586 int range_offset, 587 struct stm32_gpio_bank **out_bank) 588 { 589 TEE_Result res = TEE_ERROR_GENERIC; 590 struct stm32_gpio_bank *bank = NULL; 591 const fdt32_t *cuint = NULL; 592 struct io_pa_va pa_va = { }; 593 struct clk *clk = NULL; 594 size_t blen = 0; 595 paddr_t pa = 0; 596 int len = 0; 597 int i = 0; 598 599 assert(out_bank); 600 601 /* Probe deferrable devices first */ 602 res = clk_dt_get_by_index(fdt, node, 0, &clk); 603 if (res) 604 return res; 605 606 bank = calloc(1, sizeof(*bank)); 607 if (!bank) 608 return TEE_ERROR_OUT_OF_MEMORY; 609 610 /* 611 * Do not rely *only* on the "reg" property to get the address, 612 * but consider also the "ranges" translation property 613 */ 614 pa = fdt_reg_base_address(fdt, node); 615 if (pa == DT_INFO_INVALID_REG) 616 panic("missing reg property"); 617 618 pa_va.pa = pa + range_offset; 619 620 blen = fdt_reg_size(fdt, node); 621 if (blen == DT_INFO_INVALID_REG_SIZE) 622 panic("missing reg size property"); 623 624 DMSG("Bank name %s", fdt_get_name(fdt, node, NULL)); 625 bank->base = io_pa_or_va_secure(&pa_va, blen); 626 bank->bank_id = dt_get_bank_id(fdt, node); 627 bank->clock = clk; 628 bank->gpio_chip.ops = &stm32_gpio_ops; 629 630 /* Parse gpio-ranges with its 4 parameters */ 631 cuint = fdt_getprop(fdt, node, "gpio-ranges", &len); 632 len /= sizeof(*cuint); 633 if (len % 4) 634 panic("wrong gpio-ranges syntax"); 635 636 /* Get the last defined gpio line (offset + nb of pins) */ 637 for (i = 0; i < len / 4; i++) { 638 bank->ngpios = MAX(bank->ngpios, 639 (unsigned int)(fdt32_to_cpu(*(cuint + 1)) + 640 fdt32_to_cpu(*(cuint + 3)))); 641 cuint += 4; 642 } 643 644 *out_bank = bank; 645 return TEE_SUCCESS; 646 } 647 648 /* Parse a pinctrl node to register the GPIO banks it describes */ 649 static TEE_Result dt_stm32_gpio_pinctrl(const void *fdt, int node, 650 const void *compat_data) 651 { 652 TEE_Result res = TEE_SUCCESS; 653 const fdt32_t *cuint = NULL; 654 int range_offs = 0; 655 int b_node = 0; 656 int len = 0; 657 658 /* Read the ranges property (for regs memory translation) */ 659 cuint = fdt_getprop(fdt, node, "ranges", &len); 660 if (!cuint) 661 panic("missing ranges property"); 662 663 len /= sizeof(*cuint); 664 if (len == 3) 665 range_offs = fdt32_to_cpu(*(cuint + 1)) - fdt32_to_cpu(*cuint); 666 667 fdt_for_each_subnode(b_node, fdt, node) { 668 cuint = fdt_getprop(fdt, b_node, "gpio-controller", &len); 669 if (cuint) { 670 /* 671 * We found a property "gpio-controller" in the node: 672 * the node is a GPIO bank description, add it to the 673 * bank list. 674 */ 675 struct stm32_gpio_bank *bank = NULL; 676 677 if (fdt_get_status(fdt, b_node) == DT_STATUS_DISABLED || 678 bank_is_registered(fdt, b_node)) 679 continue; 680 681 res = dt_stm32_gpio_bank(fdt, b_node, compat_data, 682 range_offs, &bank); 683 if (res) 684 return res; 685 686 /* Registering a provider should not defer probe */ 687 res = gpio_register_provider(fdt, b_node, 688 stm32_gpio_get_dt, bank); 689 if (res) 690 panic(); 691 692 STAILQ_INSERT_TAIL(&bank_list, bank, link); 693 } else { 694 if (len != -FDT_ERR_NOTFOUND) 695 panic(); 696 } 697 } 698 699 return TEE_SUCCESS; 700 } 701 702 int stm32_pinctrl_fdt_get_pinctrl(void *fdt, int device_node, 703 struct stm32_pinctrl *pinctrl, size_t count) 704 { 705 const fdt32_t *cuint = NULL; 706 int lenp = 0; 707 int i = 0; 708 size_t found = 0; 709 710 cuint = fdt_getprop(fdt, device_node, "pinctrl-0", &lenp); 711 if (!cuint) 712 return -FDT_ERR_NOTFOUND; 713 714 for (i = 0; i < (lenp / 4); i++) { 715 int node = 0; 716 int subnode = 0; 717 718 node = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 719 if (node < 0) 720 return -FDT_ERR_NOTFOUND; 721 722 fdt_for_each_subnode(subnode, fdt, node) { 723 size_t n = 0; 724 int rc = 0; 725 726 if (count > found) 727 n = count - found; 728 else 729 n = 0; 730 731 rc = get_pinctrl_from_fdt(fdt, subnode, 732 &pinctrl[found], n); 733 if (rc < 0) 734 return rc; 735 736 found += (size_t)rc; 737 } 738 739 cuint++; 740 } 741 742 return (int)found; 743 } 744 745 int stm32_get_gpio_count(void *fdt, int pinctrl_node, unsigned int bank) 746 { 747 int node = 0; 748 const fdt32_t *cuint = NULL; 749 750 fdt_for_each_subnode(node, fdt, pinctrl_node) { 751 if (!fdt_getprop(fdt, node, "gpio-controller", NULL)) 752 continue; 753 754 cuint = fdt_getprop(fdt, node, "reg", NULL); 755 if (!cuint) 756 continue; 757 758 if (fdt32_to_cpu(*cuint) != stm32_get_gpio_bank_offset(bank)) 759 continue; 760 761 cuint = fdt_getprop(fdt, node, "ngpios", NULL); 762 if (!cuint) 763 panic(); 764 765 return (int)fdt32_to_cpu(*cuint); 766 } 767 768 return -1; 769 } 770 771 void stm32_gpio_set_secure_cfg(unsigned int bank_id, unsigned int pin, 772 bool secure) 773 { 774 struct stm32_gpio_bank *bank = stm32_gpio_get_bank(bank_id); 775 uint32_t exceptions = 0; 776 777 if (clk_enable(bank->clock)) 778 panic(); 779 exceptions = cpu_spin_lock_xsave(&gpio_lock); 780 781 if (secure) 782 io_setbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 783 else 784 io_clrbits32(bank->base + GPIO_SECR_OFFSET, BIT(pin)); 785 786 cpu_spin_unlock_xrestore(&gpio_lock, exceptions); 787 clk_disable(bank->clock); 788 } 789 790 static TEE_Result stm32_pinctrl_probe(const void *fdt, int node, 791 const void *compat_data) 792 { 793 /* Register GPIO banks described in this pin control node */ 794 return dt_stm32_gpio_pinctrl(fdt, node, compat_data); 795 } 796 797 static const struct dt_device_match stm32_pinctrl_match_table[] = { 798 { .compatible = "st,stm32mp135-pinctrl" }, 799 { .compatible = "st,stm32mp157-pinctrl" }, 800 { .compatible = "st,stm32mp157-z-pinctrl" }, 801 { } 802 }; 803 804 DEFINE_DT_DRIVER(stm32_pinctrl_dt_driver) = { 805 .name = "stm32_gpio-pinctrl", 806 .type = DT_DRIVER_PINCTRL, 807 .match_table = stm32_pinctrl_match_table, 808 .probe = stm32_pinctrl_probe, 809 }; 810