1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2021-2024, STMicroelectronics 4 */ 5 6 #include <arm.h> 7 #include <config.h> 8 #include <drivers/clk.h> 9 #include <drivers/clk_dt.h> 10 #include <drivers/stm32_gpio.h> 11 #include <drivers/stm32_rif.h> 12 #include <io.h> 13 #include <kernel/boot.h> 14 #include <kernel/delay.h> 15 #include <kernel/dt.h> 16 #include <kernel/dt_driver.h> 17 #include <kernel/panic.h> 18 #include <kernel/pm.h> 19 #include <libfdt.h> 20 #include <mm/core_memprot.h> 21 #include <stdbool.h> 22 #include <stdlib.h> 23 #include <stm32_util.h> 24 #include <trace.h> 25 26 #define _FMC_CFGR U(0x020) 27 #define _FMC_SECCFGR U(0x300) 28 #define _FMC_PRIVCFGR U(0x304) 29 #define _FMC_RCFGLOCKR U(0x308) 30 #define _FMC_CIDCFGR(x) (U(0x30C) + U(0x8) * (x)) 31 #define _FMC_SEMCR(x) (U(0x310) + U(0x8) * (x)) 32 /* 33 * CFGR register bitfields 34 */ 35 #define _FMC_CFGR_CLKDIV_MASK GENMASK_32(19, 16) 36 #define _FMC_CFGR_CLKDIV_SHIFT U(16) 37 #define _FMC_CFGR_CCLKEN BIT(20) 38 #define _FMC_CFGR_ENABLE BIT(31) 39 40 /* 41 * CIDCFGR register bitfields 42 */ 43 #define _FMC_CIDCFGR_SEMWL_MASK GENMASK_32(23, 16) 44 #define _FMC_CIDCFGR_SCID_MASK GENMASK_32(6, 4) 45 #define _FMC_CIDCFGR_CONF_MASK (_CIDCFGR_CFEN | \ 46 _CIDCFGR_SEMEN | \ 47 _FMC_CIDCFGR_SCID_MASK |\ 48 _FMC_CIDCFGR_SEMWL_MASK) 49 50 /* 51 * PRIVCFGR register bitfields 52 */ 53 #define _FMC_PRIVCFGR_MASK GENMASK_32(5, 0) 54 55 /* 56 * RCFGLOCKR register bitfields 57 */ 58 #define _FMC_RCFGLOCKR_MASK GENMASK_32(5, 0) 59 60 /* 61 * SECCFGR register bitfields 62 */ 63 #define _FMC_SECCFGR_EN BIT(0) 64 #define _FMC_SECCFGR_MASK GENMASK_32(5, 0) 65 66 /* 67 * SEMCR register bitfields 68 */ 69 #define _FMC_SEMCR_SCID_MASK GENMASK_32(7, 5) 70 #define _FMC_SEMCR_SCID_SHIFT U(5) 71 72 /* 73 * Miscellaneous 74 */ 75 76 #define FMC_RIF_CONTROLLERS U(6) 77 78 #define FMC_NSEC_PER_SEC UL(1000000000) 79 80 struct fmc_pdata { 81 struct clk *fmc_clock; 82 struct pinctrl_state *pinctrl_d; 83 struct pinctrl_state *pinctrl_s; 84 struct rif_conf_data *conf_data; 85 unsigned int nb_controller; 86 vaddr_t base; 87 uint32_t clk_period_ns; 88 bool is_tdcid; 89 bool cclken; 90 }; 91 92 static struct fmc_pdata *fmc_d; 93 94 static bool fmc_controller_is_secure(uint8_t controller) 95 { 96 return io_read32(fmc_d->base + _FMC_SECCFGR) & BIT(controller); 97 } 98 99 static TEE_Result handle_available_semaphores(void) 100 { 101 TEE_Result res = TEE_ERROR_GENERIC; 102 uint32_t cidcfgr = 0; 103 unsigned int i = 0; 104 105 for (i = 0; i < FMC_RIF_CONTROLLERS; i++) { 106 if (!(BIT(i) & fmc_d->conf_data->access_mask[0])) 107 continue; 108 109 cidcfgr = io_read32(fmc_d->base + _FMC_CIDCFGR(i)); 110 111 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) 112 continue; 113 114 if (!(io_read32(fmc_d->base + _FMC_SECCFGR) & BIT(i))) { 115 res = stm32_rif_release_semaphore(fmc_d->base + 116 _FMC_SEMCR(i), 117 MAX_CID_SUPPORTED); 118 if (res) { 119 EMSG("Cannot release semaphore for resource %u", 120 i); 121 return res; 122 } 123 } else { 124 res = stm32_rif_acquire_semaphore(fmc_d->base + 125 _FMC_SEMCR(i), 126 MAX_CID_SUPPORTED); 127 if (res) { 128 EMSG("Cannot acquire semaphore for resource %u", 129 i); 130 return res; 131 } 132 } 133 } 134 135 return TEE_SUCCESS; 136 } 137 138 static TEE_Result apply_rif_config(void) 139 { 140 TEE_Result res = TEE_ERROR_ACCESS_DENIED; 141 unsigned int i = 0; 142 143 if (!fmc_d->conf_data) 144 return TEE_SUCCESS; 145 146 res = clk_enable(fmc_d->fmc_clock); 147 if (res) 148 panic("Cannot access FMC clock"); 149 150 if (fmc_d->is_tdcid) { 151 for (i = 0; i < FMC_RIF_CONTROLLERS; i++) { 152 if (!(BIT(i) & fmc_d->conf_data->access_mask[0])) 153 continue; 154 /* 155 * When TDCID, OP-TEE should be the one to set the CID 156 * filtering configuration. Clearing previous 157 * configuration prevents undesired events during the 158 * only legitimate configuration. 159 */ 160 io_clrbits32(fmc_d->base + _FMC_CIDCFGR(i), 161 _FMC_CIDCFGR_CONF_MASK); 162 } 163 } else { 164 res = handle_available_semaphores(); 165 if (res) 166 panic(); 167 } 168 169 /* Security and privilege RIF configuration */ 170 io_clrsetbits32(fmc_d->base + _FMC_PRIVCFGR, _FMC_PRIVCFGR_MASK, 171 fmc_d->conf_data->priv_conf[0]); 172 io_clrsetbits32(fmc_d->base + _FMC_SECCFGR, _FMC_SECCFGR_MASK, 173 fmc_d->conf_data->sec_conf[0]); 174 175 if (!fmc_d->is_tdcid) 176 goto out; 177 178 for (i = 0; i < FMC_RIF_CONTROLLERS; i++) { 179 if (!(BIT(i) & fmc_d->conf_data->access_mask[0])) 180 continue; 181 182 io_clrsetbits32(fmc_d->base + _FMC_CIDCFGR(i), 183 _FMC_CIDCFGR_CONF_MASK, 184 fmc_d->conf_data->cid_confs[i]); 185 } 186 187 /* 188 * Lock RIF configuration if configured. This cannot be undone until 189 * next reset. 190 */ 191 io_setbits32(fmc_d->base + _FMC_RCFGLOCKR, 192 fmc_d->conf_data->lock_conf[0]); 193 194 res = handle_available_semaphores(); 195 if (res) 196 panic(); 197 out: 198 if (IS_ENABLED(CFG_TEE_CORE_DEBUG)) { 199 /* Check that RIF config are applied, panic otherwise */ 200 if ((io_read32(fmc_d->base + _FMC_PRIVCFGR) & 201 fmc_d->conf_data->access_mask[0]) != 202 fmc_d->conf_data->priv_conf[0]) { 203 EMSG("FMC controller priv conf is incorrect"); 204 panic(); 205 } 206 207 if ((io_read32(fmc_d->base + _FMC_SECCFGR) & 208 fmc_d->conf_data->access_mask[0]) != 209 fmc_d->conf_data->sec_conf[0]) { 210 EMSG("FMC controller sec conf is incorrect"); 211 panic(); 212 } 213 } 214 215 /* Disable the clock to allow RCC RIF re-configuration on this clock */ 216 clk_disable(fmc_d->fmc_clock); 217 218 return TEE_SUCCESS; 219 } 220 221 static TEE_Result parse_dt(const void *fdt, int node) 222 { 223 TEE_Result res = TEE_ERROR_GENERIC; 224 struct dt_node_info info = { }; 225 const fdt32_t *cuint = NULL; 226 struct io_pa_va addr = { }; 227 unsigned int i = 0; 228 int ctrl_node = 0; 229 int lenp = 0; 230 231 fdt_fill_device_info(fdt, &info, node); 232 assert(info.reg != DT_INFO_INVALID_REG && 233 info.reg_size != DT_INFO_INVALID_REG_SIZE); 234 235 addr.pa = info.reg; 236 fmc_d->base = io_pa_or_va(&addr, info.reg_size); 237 238 res = clk_dt_get_by_index(fdt, node, 0, &fmc_d->fmc_clock); 239 if (res) 240 return res; 241 242 res = pinctrl_get_state_by_name(fdt, node, "default", 243 &fmc_d->pinctrl_d); 244 if (res && res != TEE_ERROR_ITEM_NOT_FOUND) 245 return res; 246 247 res = pinctrl_get_state_by_name(fdt, node, "sleep", 248 &fmc_d->pinctrl_s); 249 if (res && res != TEE_ERROR_ITEM_NOT_FOUND) 250 return res; 251 252 cuint = fdt_getprop(fdt, node, "st,protreg", &lenp); 253 if (!cuint) { 254 DMSG("No RIF configuration available"); 255 goto skip_rif; 256 } 257 258 fmc_d->conf_data = calloc(1, sizeof(*fmc_d->conf_data)); 259 if (!fmc_d->conf_data) 260 panic(); 261 262 fmc_d->nb_controller = (unsigned int)(lenp / sizeof(uint32_t)); 263 assert(fmc_d->nb_controller <= FMC_RIF_CONTROLLERS); 264 265 fmc_d->conf_data->cid_confs = calloc(FMC_RIF_CONTROLLERS, 266 sizeof(uint32_t)); 267 fmc_d->conf_data->sec_conf = calloc(1, sizeof(uint32_t)); 268 fmc_d->conf_data->priv_conf = calloc(1, sizeof(uint32_t)); 269 fmc_d->conf_data->lock_conf = calloc(1, sizeof(uint32_t)); 270 fmc_d->conf_data->access_mask = calloc(1, sizeof(uint32_t)); 271 if (!fmc_d->conf_data->cid_confs || !fmc_d->conf_data->sec_conf || 272 !fmc_d->conf_data->priv_conf || !fmc_d->conf_data->access_mask) 273 panic("Missing memory capacity for FMC RIF configuration"); 274 275 for (i = 0; i < fmc_d->nb_controller; i++) 276 stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), fmc_d->conf_data, 277 FMC_RIF_CONTROLLERS); 278 279 skip_rif: 280 fdt_for_each_subnode(ctrl_node, fdt, node) { 281 int status = fdt_get_status(fdt, ctrl_node); 282 uint32_t bank = 0; 283 284 if (status == DT_STATUS_DISABLED) 285 continue; 286 287 if (fdt_read_uint32(fdt, ctrl_node, "reg", &bank) < 0) 288 return TEE_ERROR_BAD_PARAMETERS; 289 290 if (bank != 0) 291 continue; 292 293 if (fdt_getprop(fdt, ctrl_node, 294 "st,fmc2-ebi-cs-cclk-enable", NULL)) 295 fmc_d->cclken = true; 296 297 if (!fmc_d->cclken) 298 continue; 299 300 if (fdt_read_uint32(fdt, ctrl_node, 301 "st,fmc2-ebi-cs-clk-period-ns", 302 &fmc_d->clk_period_ns) < 0) 303 return TEE_ERROR_BAD_PARAMETERS; 304 } 305 306 return TEE_SUCCESS; 307 } 308 309 static TEE_Result __maybe_unused check_fmc_rif_conf(void) 310 { 311 unsigned int i = 0; 312 TEE_Result res = TEE_ERROR_GENERIC; 313 314 res = clk_enable(fmc_d->fmc_clock); 315 if (res) 316 panic("Cannot access FMC clock"); 317 318 if (fmc_controller_is_secure(0)) { 319 res = TEE_SUCCESS; 320 goto end; 321 } 322 323 for (i = 1; i < fmc_d->nb_controller; i++) { 324 uint32_t cidcfgr = io_read32(fmc_d->base + _FMC_CIDCFGR(i)); 325 uint32_t semcr = io_read32(fmc_d->base + _FMC_SEMCR(i)); 326 327 /* Check if a controller is secure */ 328 if (fmc_controller_is_secure(i)) { 329 res = TEE_ERROR_BAD_STATE; 330 goto end; 331 } 332 333 /* 334 * Check if a controller is shared with incorrect CID 335 * (!= RIF_CID1) 336 */ 337 res = stm32_rif_check_access(cidcfgr, semcr, MAX_CID_SUPPORTED, 338 RIF_CID1); 339 if (res) 340 break; 341 } 342 343 end: 344 clk_disable(fmc_d->fmc_clock); 345 346 return res; 347 } 348 349 static void configure_fmc(void) 350 { 351 uint32_t cidcfgr = 0; 352 uint32_t semcr = 0; 353 354 if (clk_enable(fmc_d->fmc_clock)) 355 panic("Cannot access FMC clock"); 356 357 semcr = io_read32(fmc_d->base + _FMC_SEMCR(0)); 358 cidcfgr = io_read32(fmc_d->base + _FMC_CIDCFGR(0)); 359 360 /* 361 * If OP-TEE doesn't have access to the controller 0, 362 * then we don't want to try to enable the FMC. 363 */ 364 if (stm32_rif_check_access(cidcfgr, semcr, MAX_CID_SUPPORTED, RIF_CID1)) 365 goto end; 366 367 /* Check controller 0 access */ 368 if (!fmc_controller_is_secure(0)) { 369 DMSG("Controller 0 non-secure, FMC not enabled"); 370 goto end; 371 } 372 373 if (cidcfgr & _CIDCFGR_SEMEN && 374 stm32_rif_acquire_semaphore(fmc_d->base + _FMC_SEMCR(0), 375 MAX_CID_SUPPORTED)) 376 panic("Couldn't acquire controller 0 semaphore"); 377 378 if (fmc_d->pinctrl_d && pinctrl_apply_state(fmc_d->pinctrl_d)) 379 panic("Could not apply FMC pinctrl"); 380 381 if (fmc_d->cclken) { 382 unsigned long hclk = clk_get_rate(fmc_d->fmc_clock); 383 unsigned long hclkp = FMC_NSEC_PER_SEC / (hclk / 1000); 384 unsigned long timing = DIV_ROUND_UP(fmc_d->clk_period_ns * 1000, 385 hclkp); 386 uint32_t clk_div = SHIFT_U32(1, _FMC_CFGR_CLKDIV_SHIFT); 387 388 if (timing > 1) { 389 timing--; 390 if (timing > 391 _FMC_CFGR_CLKDIV_MASK >> _FMC_CFGR_CLKDIV_SHIFT) 392 clk_div = _FMC_CFGR_CLKDIV_MASK; 393 else 394 clk_div = SHIFT_U32(timing, 395 _FMC_CFGR_CLKDIV_SHIFT); 396 } 397 398 io_clrsetbits32(fmc_d->base + _FMC_CFGR, 399 _FMC_CFGR_CLKDIV_MASK | _FMC_CFGR_CCLKEN, 400 clk_div | _FMC_CFGR_CCLKEN); 401 } 402 403 /* Set the FMC enable BIT */ 404 io_setbits32(fmc_d->base + _FMC_CFGR, _FMC_CFGR_ENABLE); 405 406 end: 407 clk_disable(fmc_d->fmc_clock); 408 } 409 410 static void fmc_setup(void) 411 { 412 if (apply_rif_config()) 413 panic("Failed to apply rif_config"); 414 415 /* Sanity check for FMC RIF config */ 416 assert(!check_fmc_rif_conf()); 417 418 configure_fmc(); 419 } 420 421 static void fmc_suspend(void) 422 { 423 unsigned int i = 0; 424 425 if (clk_enable(fmc_d->fmc_clock)) 426 panic("Cannot access FMC clock"); 427 428 if (fmc_controller_is_secure(0) && fmc_d->pinctrl_s && 429 pinctrl_apply_state(fmc_d->pinctrl_s)) 430 panic(); 431 432 for (i = 0; i < FMC_RIF_CONTROLLERS; i++) 433 fmc_d->conf_data->cid_confs[i] = 434 io_read32(fmc_d->base + _FMC_CIDCFGR(i)) & 435 _FMC_CIDCFGR_CONF_MASK; 436 437 fmc_d->conf_data->priv_conf[0] = 438 io_read32(fmc_d->base + _FMC_PRIVCFGR) & _FMC_PRIVCFGR_MASK; 439 fmc_d->conf_data->sec_conf[0] = 440 io_read32(fmc_d->base + _FMC_SECCFGR) & _FMC_SECCFGR_MASK; 441 fmc_d->conf_data->lock_conf[0] = 442 io_read32(fmc_d->base + _FMC_RCFGLOCKR) & _FMC_RCFGLOCKR_MASK; 443 fmc_d->conf_data->access_mask[0] = 444 GENMASK_32(FMC_RIF_CONTROLLERS - 1, 0); 445 446 clk_disable(fmc_d->fmc_clock); 447 } 448 449 static TEE_Result fmc_pm(enum pm_op op, unsigned int pm_hint, 450 const struct pm_callback_handle *pm_handle __unused) 451 { 452 if (!PM_HINT_IS_STATE(pm_hint, CONTEXT)) 453 return TEE_SUCCESS; 454 455 if (op == PM_OP_RESUME) 456 fmc_setup(); 457 else 458 fmc_suspend(); 459 460 return TEE_SUCCESS; 461 } 462 463 static TEE_Result fmc_probe(const void *fdt, int node, 464 const void *compat_data __unused) 465 { 466 TEE_Result res = TEE_ERROR_GENERIC; 467 468 fmc_d = calloc(1, sizeof(*fmc_d)); 469 if (!fmc_d) 470 return TEE_ERROR_OUT_OF_MEMORY; 471 472 res = stm32_rifsc_check_tdcid(&fmc_d->is_tdcid); 473 if (res) { 474 free(fmc_d); 475 return res; 476 } 477 478 res = parse_dt(fdt, node); 479 if (res) 480 goto err; 481 482 fmc_setup(); 483 484 register_pm_core_service_cb(fmc_pm, NULL, "stm32-fmc"); 485 486 return TEE_SUCCESS; 487 err: 488 /* Free all allocated resources */ 489 if (fmc_d->conf_data) { 490 free(fmc_d->conf_data->access_mask); 491 free(fmc_d->conf_data->cid_confs); 492 free(fmc_d->conf_data->priv_conf); 493 free(fmc_d->conf_data->sec_conf); 494 } 495 free(fmc_d->conf_data); 496 free(fmc_d); 497 498 return res; 499 } 500 501 static const struct dt_device_match stm32_fmc_match_table[] = { 502 { .compatible = "st,stm32mp25-fmc2-ebi" }, 503 { } 504 }; 505 506 DEFINE_DT_DRIVER(stm32_fmc_dt_driver) = { 507 .name = "stm32_fmc", 508 .match_table = stm32_fmc_match_table, 509 .probe = fmc_probe, 510 }; 511