1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2021-2024, STMicroelectronics 4 */ 5 6 #include <arm.h> 7 #include <config.h> 8 #include <drivers/clk.h> 9 #include <drivers/clk_dt.h> 10 #include <drivers/stm32_gpio.h> 11 #include <drivers/stm32_rif.h> 12 #include <io.h> 13 #include <kernel/boot.h> 14 #include <kernel/delay.h> 15 #include <kernel/dt.h> 16 #include <kernel/dt_driver.h> 17 #include <kernel/panic.h> 18 #include <kernel/pm.h> 19 #include <libfdt.h> 20 #include <mm/core_memprot.h> 21 #include <stdbool.h> 22 #include <stdlib.h> 23 #include <stm32_util.h> 24 #include <trace.h> 25 26 #define _FMC_CFGR U(0x020) 27 #define _FMC_SECCFGR U(0x300) 28 #define _FMC_PRIVCFGR U(0x304) 29 #define _FMC_RCFGLOCKR U(0x308) 30 #define _FMC_CIDCFGR(x) (U(0x30C) + U(0x8) * (x)) 31 #define _FMC_SEMCR(x) (U(0x310) + U(0x8) * (x)) 32 /* 33 * CFGR register bitfields 34 */ 35 #define _FMC_CFGR_CLKDIV_MASK GENMASK_32(19, 16) 36 #define _FMC_CFGR_CLKDIV_SHIFT U(16) 37 #define _FMC_CFGR_CCLKEN BIT(20) 38 #define _FMC_CFGR_ENABLE BIT(31) 39 40 /* 41 * CIDCFGR register bitfields 42 */ 43 #define _FMC_CIDCFGR_SEMWL_MASK GENMASK_32(23, 16) 44 #define _FMC_CIDCFGR_SCID_MASK GENMASK_32(6, 4) 45 #define _FMC_CIDCFGR_CONF_MASK (_CIDCFGR_CFEN | \ 46 _CIDCFGR_SEMEN | \ 47 _FMC_CIDCFGR_SCID_MASK |\ 48 _FMC_CIDCFGR_SEMWL_MASK) 49 50 /* 51 * PRIVCFGR register bitfields 52 */ 53 #define _FMC_PRIVCFGR_MASK GENMASK_32(5, 0) 54 55 /* 56 * RCFGLOCKR register bitfields 57 */ 58 #define _FMC_RCFGLOCKR_MASK GENMASK_32(5, 0) 59 60 /* 61 * SECCFGR register bitfields 62 */ 63 #define _FMC_SECCFGR_EN BIT(0) 64 #define _FMC_SECCFGR_MASK GENMASK_32(5, 0) 65 66 /* 67 * SEMCR register bitfields 68 */ 69 #define _FMC_SEMCR_SCID_MASK GENMASK_32(7, 5) 70 #define _FMC_SEMCR_SCID_SHIFT U(5) 71 72 /* 73 * Miscellaneous 74 */ 75 76 #define FMC_RIF_CONTROLLERS U(6) 77 78 #define FMC_NB_MAX_CID_SUPPORTED U(7) 79 80 #define FMC_NSEC_PER_SEC UL(1000000000) 81 82 struct fmc_pdata { 83 struct clk *fmc_clock; 84 struct pinctrl_state *pinctrl_d; 85 struct pinctrl_state *pinctrl_s; 86 struct rif_conf_data *conf_data; 87 unsigned int nb_controller; 88 vaddr_t base; 89 uint32_t clk_period_ns; 90 bool cclken; 91 }; 92 93 static struct fmc_pdata *fmc_d; 94 95 static bool fmc_controller_is_secure(uint8_t controller) 96 { 97 return io_read32(fmc_d->base + _FMC_SECCFGR) & BIT(controller); 98 } 99 100 static TEE_Result apply_rif_config(void) 101 { 102 TEE_Result res = TEE_ERROR_ACCESS_DENIED; 103 uint32_t cidcfgr = 0; 104 unsigned int i = 0; 105 106 if (!fmc_d->conf_data) 107 return TEE_SUCCESS; 108 109 res = clk_enable(fmc_d->fmc_clock); 110 if (res) 111 panic("Cannot access FMC clock"); 112 113 for (i = 0; i < FMC_RIF_CONTROLLERS; i++) { 114 if (!(BIT(i) & fmc_d->conf_data->access_mask[0])) 115 continue; 116 117 /* 118 * Whatever the TDCID state, try to clear the configurable part 119 * of the CIDCFGR register. 120 * If TDCID, register will be cleared, if not, the clear will 121 * be ignored. 122 * When TDCID, OP-TEE should be the one to set the CID filtering 123 * configuration. Clearing previous configuration prevents 124 * undesired events during the only legitimate configuration. 125 */ 126 io_clrbits32(fmc_d->base + _FMC_CIDCFGR(i), 127 _FMC_CIDCFGR_CONF_MASK); 128 129 cidcfgr = io_read32(fmc_d->base + _FMC_CIDCFGR(i)); 130 131 /* Check if the controller is in semaphore mode */ 132 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) 133 continue; 134 135 /* If not TDCID, we want to acquire semaphores assigned to us */ 136 res = stm32_rif_acquire_semaphore(fmc_d->base + _FMC_SEMCR(i), 137 FMC_NB_MAX_CID_SUPPORTED); 138 if (res) { 139 EMSG("Couldn't acquire semaphore for controller %u", i); 140 clk_disable(fmc_d->fmc_clock); 141 return res; 142 } 143 } 144 145 /* Security and privilege RIF configuration */ 146 io_clrsetbits32(fmc_d->base + _FMC_PRIVCFGR, _FMC_PRIVCFGR_MASK, 147 fmc_d->conf_data->priv_conf[0]); 148 io_clrsetbits32(fmc_d->base + _FMC_SECCFGR, _FMC_SECCFGR_MASK, 149 fmc_d->conf_data->sec_conf[0]); 150 151 for (i = 0; i < FMC_RIF_CONTROLLERS; i++) { 152 if (!(BIT(i) & fmc_d->conf_data->access_mask[0])) 153 continue; 154 155 io_clrsetbits32(fmc_d->base + _FMC_CIDCFGR(i), 156 _FMC_CIDCFGR_CONF_MASK, 157 fmc_d->conf_data->cid_confs[i]); 158 159 cidcfgr = io_read32(fmc_d->base + _FMC_CIDCFGR(i)); 160 161 /* 162 * Take semaphore if the resource is in semaphore mode 163 * and secured 164 */ 165 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1) || 166 !(io_read32(fmc_d->base + _FMC_SECCFGR) & BIT(i))) { 167 res = 168 stm32_rif_release_semaphore(fmc_d->base + _FMC_SEMCR(i), 169 FMC_NB_MAX_CID_SUPPORTED); 170 if (res) { 171 EMSG("Couldn't release semaphore for res%u", i); 172 clk_disable(fmc_d->fmc_clock); 173 return res; 174 } 175 } else { 176 res = 177 stm32_rif_acquire_semaphore(fmc_d->base + _FMC_SEMCR(i), 178 FMC_NB_MAX_CID_SUPPORTED); 179 if (res) { 180 EMSG("Couldn't acquire semaphore for res%u", i); 181 clk_disable(fmc_d->fmc_clock); 182 return res; 183 } 184 } 185 } 186 187 /* 188 * Lock RIF configuration if configured. This cannot be undone until 189 * next reset. 190 */ 191 io_clrsetbits32(fmc_d->base + _FMC_RCFGLOCKR, _FMC_RCFGLOCKR_MASK, 192 fmc_d->conf_data->lock_conf[0]); 193 194 if (IS_ENABLED(CFG_TEE_CORE_DEBUG)) { 195 /* Check that RIF config are applied, panic otherwise */ 196 if ((io_read32(fmc_d->base + _FMC_PRIVCFGR) & 197 fmc_d->conf_data->access_mask[0]) != 198 fmc_d->conf_data->priv_conf[0]) { 199 EMSG("FMC controller priv conf is incorrect"); 200 panic(); 201 } 202 203 if ((io_read32(fmc_d->base + _FMC_SECCFGR) & 204 fmc_d->conf_data->access_mask[0]) != 205 fmc_d->conf_data->sec_conf[0]) { 206 EMSG("FMC controller sec conf is incorrect"); 207 panic(); 208 } 209 } 210 211 /* Disable the clock to allow RCC RIF re-configuration on this clock */ 212 clk_disable(fmc_d->fmc_clock); 213 214 return TEE_SUCCESS; 215 } 216 217 static TEE_Result parse_dt(const void *fdt, int node) 218 { 219 TEE_Result res = TEE_ERROR_GENERIC; 220 struct dt_node_info info = { }; 221 const fdt32_t *cuint = NULL; 222 struct io_pa_va addr = { }; 223 unsigned int i = 0; 224 int ctrl_node = 0; 225 int lenp = 0; 226 227 fdt_fill_device_info(fdt, &info, node); 228 assert(info.reg != DT_INFO_INVALID_REG && 229 info.reg_size != DT_INFO_INVALID_REG_SIZE); 230 231 addr.pa = info.reg; 232 fmc_d->base = io_pa_or_va(&addr, info.reg_size); 233 234 res = clk_dt_get_by_index(fdt, node, 0, &fmc_d->fmc_clock); 235 if (res) 236 return res; 237 238 res = pinctrl_get_state_by_name(fdt, node, "default", 239 &fmc_d->pinctrl_d); 240 if (res && res != TEE_ERROR_ITEM_NOT_FOUND) 241 return res; 242 243 res = pinctrl_get_state_by_name(fdt, node, "sleep", 244 &fmc_d->pinctrl_s); 245 if (res && res != TEE_ERROR_ITEM_NOT_FOUND) 246 return res; 247 248 cuint = fdt_getprop(fdt, node, "st,protreg", &lenp); 249 if (!cuint) { 250 DMSG("No RIF configuration available"); 251 goto skip_rif; 252 } 253 254 fmc_d->conf_data = calloc(1, sizeof(*fmc_d->conf_data)); 255 if (!fmc_d->conf_data) 256 panic(); 257 258 fmc_d->nb_controller = (unsigned int)(lenp / sizeof(uint32_t)); 259 assert(fmc_d->nb_controller <= FMC_RIF_CONTROLLERS); 260 261 fmc_d->conf_data->cid_confs = calloc(FMC_RIF_CONTROLLERS, 262 sizeof(uint32_t)); 263 fmc_d->conf_data->sec_conf = calloc(1, sizeof(uint32_t)); 264 fmc_d->conf_data->priv_conf = calloc(1, sizeof(uint32_t)); 265 fmc_d->conf_data->lock_conf = calloc(1, sizeof(uint32_t)); 266 fmc_d->conf_data->access_mask = calloc(1, sizeof(uint32_t)); 267 if (!fmc_d->conf_data->cid_confs || !fmc_d->conf_data->sec_conf || 268 !fmc_d->conf_data->priv_conf || !fmc_d->conf_data->access_mask) 269 panic("Missing memory capacity for FMC RIF configuration"); 270 271 for (i = 0; i < fmc_d->nb_controller; i++) 272 stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), fmc_d->conf_data, 273 FMC_RIF_CONTROLLERS); 274 275 skip_rif: 276 fdt_for_each_subnode(ctrl_node, fdt, node) { 277 int status = fdt_get_status(fdt, ctrl_node); 278 uint32_t bank = 0; 279 280 if (status == DT_STATUS_DISABLED) 281 continue; 282 283 if (fdt_read_uint32(fdt, ctrl_node, "reg", &bank) < 0) 284 return TEE_ERROR_BAD_PARAMETERS; 285 286 if (bank != 0) 287 continue; 288 289 if (fdt_getprop(fdt, ctrl_node, 290 "st,fmc2-ebi-cs-cclk-enable", NULL)) 291 fmc_d->cclken = true; 292 293 if (!fmc_d->cclken) 294 continue; 295 296 if (fdt_read_uint32(fdt, ctrl_node, 297 "st,fmc2-ebi-cs-clk-period-ns", 298 &fmc_d->clk_period_ns) < 0) 299 return TEE_ERROR_BAD_PARAMETERS; 300 } 301 302 return TEE_SUCCESS; 303 } 304 305 static TEE_Result __maybe_unused check_fmc_rif_conf(void) 306 { 307 unsigned int i = 0; 308 TEE_Result res = TEE_ERROR_GENERIC; 309 310 res = clk_enable(fmc_d->fmc_clock); 311 if (res) 312 panic("Cannot access FMC clock"); 313 314 if (fmc_controller_is_secure(0)) 315 goto end; 316 317 for (i = 1; i < fmc_d->nb_controller; i++) { 318 uint32_t cidcfgr = io_read32(fmc_d->base + _FMC_CIDCFGR(i)); 319 uint32_t semcr = io_read32(fmc_d->base + _FMC_SEMCR(i)); 320 321 /* Check if a controller is secure */ 322 if (fmc_controller_is_secure(i)) { 323 res = TEE_ERROR_BAD_STATE; 324 goto end; 325 } 326 327 /* 328 * Check if a controller is shared with incorrect CID 329 * (!= RIF_CID1) 330 */ 331 res = stm32_rif_check_access(cidcfgr, semcr, 332 FMC_NB_MAX_CID_SUPPORTED, 333 RIF_CID1); 334 if (res) 335 break; 336 } 337 338 end: 339 clk_disable(fmc_d->fmc_clock); 340 341 return res; 342 } 343 344 static void configure_fmc(void) 345 { 346 uint32_t cidcfgr = 0; 347 uint32_t semcr = 0; 348 349 if (clk_enable(fmc_d->fmc_clock)) 350 panic("Cannot access FMC clock"); 351 352 semcr = io_read32(fmc_d->base + _FMC_SEMCR(0)); 353 cidcfgr = io_read32(fmc_d->base + _FMC_CIDCFGR(0)); 354 355 /* 356 * If OP-TEE doesn't have access to the controller 0, 357 * then we don't want to try to enable the FMC. 358 */ 359 if (stm32_rif_check_access(cidcfgr, semcr, 360 FMC_NB_MAX_CID_SUPPORTED, RIF_CID1)) 361 goto end; 362 363 /* Check controller 0 access */ 364 if (!fmc_controller_is_secure(0)) { 365 DMSG("Controller 0 non-secure, FMC not enabled"); 366 goto end; 367 } 368 369 if (cidcfgr & _CIDCFGR_SEMEN && 370 stm32_rif_acquire_semaphore(fmc_d->base + _FMC_SEMCR(0), 371 FMC_NB_MAX_CID_SUPPORTED)) 372 panic("Couldn't acquire controller 0 semaphore"); 373 374 if (fmc_d->pinctrl_d && pinctrl_apply_state(fmc_d->pinctrl_d)) 375 panic("Could not apply FMC pinctrl"); 376 377 if (fmc_d->cclken) { 378 unsigned long hclk = clk_get_rate(fmc_d->fmc_clock); 379 unsigned long hclkp = FMC_NSEC_PER_SEC / (hclk / 1000); 380 unsigned long timing = DIV_ROUND_UP(fmc_d->clk_period_ns * 1000, 381 hclkp); 382 uint32_t clk_div = SHIFT_U32(1, _FMC_CFGR_CLKDIV_SHIFT); 383 384 if (timing > 1) { 385 timing--; 386 if (timing > 387 _FMC_CFGR_CLKDIV_MASK >> _FMC_CFGR_CLKDIV_SHIFT) 388 clk_div = _FMC_CFGR_CLKDIV_MASK; 389 else 390 clk_div = SHIFT_U32(timing, 391 _FMC_CFGR_CLKDIV_SHIFT); 392 } 393 394 io_clrsetbits32(fmc_d->base + _FMC_CFGR, 395 _FMC_CFGR_CLKDIV_MASK | _FMC_CFGR_CCLKEN, 396 clk_div | _FMC_CFGR_CCLKEN); 397 } 398 399 /* Set the FMC enable BIT */ 400 io_setbits32(fmc_d->base + _FMC_CFGR, _FMC_CFGR_ENABLE); 401 402 end: 403 clk_disable(fmc_d->fmc_clock); 404 } 405 406 static void fmc_setup(void) 407 { 408 if (apply_rif_config()) 409 panic("Failed to apply rif_config"); 410 411 /* Sanity check for FMC RIF config */ 412 assert(check_fmc_rif_conf()); 413 414 configure_fmc(); 415 } 416 417 static void fmc_suspend(void) 418 { 419 unsigned int i = 0; 420 421 if (clk_enable(fmc_d->fmc_clock)) 422 panic("Cannot access FMC clock"); 423 424 if (fmc_controller_is_secure(0) && fmc_d->pinctrl_s && 425 pinctrl_apply_state(fmc_d->pinctrl_s)) 426 panic(); 427 428 for (i = 0; i < FMC_RIF_CONTROLLERS; i++) 429 fmc_d->conf_data->cid_confs[i] = 430 io_read32(fmc_d->base + _FMC_CIDCFGR(i)) & 431 _FMC_CIDCFGR_CONF_MASK; 432 433 fmc_d->conf_data->priv_conf[0] = 434 io_read32(fmc_d->base + _FMC_PRIVCFGR) & _FMC_PRIVCFGR_MASK; 435 fmc_d->conf_data->sec_conf[0] = 436 io_read32(fmc_d->base + _FMC_SECCFGR) & _FMC_SECCFGR_MASK; 437 fmc_d->conf_data->lock_conf[0] = 438 io_read32(fmc_d->base + _FMC_RCFGLOCKR) & _FMC_RCFGLOCKR_MASK; 439 fmc_d->conf_data->access_mask[0] = 440 GENMASK_32(FMC_RIF_CONTROLLERS - 1, 0); 441 442 clk_disable(fmc_d->fmc_clock); 443 } 444 445 static TEE_Result fmc_pm(enum pm_op op, unsigned int pm_hint, 446 const struct pm_callback_handle *pm_handle __unused) 447 { 448 if (pm_hint != PM_HINT_CONTEXT_STATE) 449 return TEE_SUCCESS; 450 451 if (op == PM_OP_RESUME) 452 fmc_setup(); 453 else 454 fmc_suspend(); 455 456 return TEE_SUCCESS; 457 } 458 459 static TEE_Result fmc_probe(const void *fdt, int node, 460 const void *compat_data __unused) 461 { 462 TEE_Result res = TEE_ERROR_GENERIC; 463 464 fmc_d = calloc(1, sizeof(*fmc_d)); 465 if (!fmc_d) 466 return TEE_ERROR_OUT_OF_MEMORY; 467 468 res = parse_dt(fdt, node); 469 if (res) 470 goto err; 471 472 fmc_setup(); 473 474 register_pm_core_service_cb(fmc_pm, NULL, "stm32-fmc"); 475 476 return TEE_SUCCESS; 477 err: 478 /* Free all allocated resources */ 479 if (fmc_d->conf_data) { 480 free(fmc_d->conf_data->access_mask); 481 free(fmc_d->conf_data->cid_confs); 482 free(fmc_d->conf_data->priv_conf); 483 free(fmc_d->conf_data->sec_conf); 484 } 485 free(fmc_d->conf_data); 486 free(fmc_d); 487 488 return res; 489 } 490 491 static const struct dt_device_match stm32_fmc_match_table[] = { 492 { .compatible = "st,stm32mp25-fmc2-ebi" }, 493 { } 494 }; 495 496 DEFINE_DT_DRIVER(stm32_fmc_dt_driver) = { 497 .name = "stm32_fmc", 498 .match_table = stm32_fmc_match_table, 499 .probe = fmc_probe, 500 }; 501