1 /* 2 * Copyright (c) 2014, STMicroelectronics International N.V. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include <drivers/gic.h> 29 #include <io.h> 30 #include <kernel/tee_core_trace.h> 31 32 #include <assert.h> 33 34 /* Offsets from gic.gicc_base */ 35 #define GICC_CTLR (0x000) 36 #define GICC_IAR (0x00C) 37 #define GICC_EOIR (0x010) 38 39 #define GICC_CTLR_ENABLEGRP0 (1 << 0) 40 #define GICC_CTLR_ENABLEGRP1 (1 << 1) 41 #define GICC_CTLR_FIQEN (1 << 3) 42 43 /* Offsets from gic.gicd_base */ 44 #define GICD_CTLR (0x000) 45 #define GICD_TYPER (0x004) 46 #define GICD_IGROUPR(n) (0x080 + (n) * 4) 47 #define GICD_ISENABLER(n) (0x100 + (n) * 4) 48 #define GICD_ICENABLER(n) (0x180 + (n) * 4) 49 #define GICD_ICPENDR(n) (0x280 + (n) * 4) 50 #define GICD_IPRIORITYR(n) (0x400 + (n) * 4) 51 #define GICD_ITARGETSR(n) (0x800 + (n) * 4) 52 53 #define GICD_CTLR_ENABLEGRP0 (1 << 0) 54 #define GICD_CTLR_ENABLEGRP1 (1 << 1) 55 56 /* Maximum number of interrups a GIC can support */ 57 #define GIC_MAX_INTS 1020 58 59 60 static struct { 61 vaddr_t gicc_base; 62 vaddr_t gicd_base; 63 size_t max_it; 64 } gic; 65 66 static size_t probe_max_it(void) 67 { 68 int i; 69 uint32_t old_ctlr; 70 size_t ret = 0; 71 72 /* 73 * Probe which interrupt number is the largest. 74 */ 75 old_ctlr = read32(gic.gicc_base + GICC_CTLR); 76 write32(0, gic.gicc_base + GICC_CTLR); 77 for (i = GIC_MAX_INTS / 32; i > 0; i--) { 78 uint32_t old_reg; 79 uint32_t reg; 80 int b; 81 82 old_reg = read32(gic.gicd_base + GICD_ISENABLER(i)); 83 write32(0xffffffff, gic.gicd_base + GICD_ISENABLER(i)); 84 reg = read32(gic.gicd_base + GICD_ISENABLER(i)); 85 write32(old_reg, gic.gicd_base + GICD_ICENABLER(i)); 86 for (b = 31; b > 0; b--) { 87 if ((1 << b) & reg) { 88 ret = i * 32 + b; 89 goto out; 90 } 91 } 92 } 93 out: 94 write32(old_ctlr, gic.gicc_base + GICC_CTLR); 95 return ret; 96 } 97 98 void gic_init(vaddr_t gicc_base, vaddr_t gicd_base) 99 { 100 size_t n; 101 102 gic.gicc_base = gicc_base; 103 gic.gicd_base = gicd_base; 104 gic.max_it = probe_max_it(); 105 106 for (n = 0; n <= gic.max_it / 32; n++) { 107 /* Disable interrupts */ 108 write32(0xffffffff, gic.gicd_base + GICD_ICENABLER(n)); 109 110 /* Make interrupts non-pending */ 111 write32(0xffffffff, gic.gicd_base + GICD_ICPENDR(n)); 112 113 /* Mark interrupts non-secure */ 114 write32(0xffffffff, gic.gicd_base + GICD_IGROUPR(n)); 115 } 116 117 /* Enable GIC */ 118 write32(GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 | GICC_CTLR_FIQEN, 119 gic.gicc_base + GICC_CTLR); 120 write32(GICD_CTLR_ENABLEGRP0 | GICD_CTLR_ENABLEGRP1, 121 gic.gicd_base + GICD_CTLR); 122 } 123 124 void gic_it_add(size_t it) 125 { 126 size_t idx = it / 32; 127 uint32_t mask = 1 << (it % 32); 128 129 assert(it <= gic.max_it); /* Not too large */ 130 131 /* Disable the interrupt */ 132 write32(mask, gic.gicd_base + GICD_ICENABLER(idx)); 133 /* Make it non-pending */ 134 write32(mask, gic.gicd_base + GICD_ICPENDR(idx)); 135 /* Assign it to group0 */ 136 write32(read32(gic.gicd_base + GICD_IGROUPR(idx)) & ~mask, 137 gic.gicd_base + GICD_IGROUPR(idx)); 138 } 139 140 void gic_it_set_cpu_mask(size_t it, uint8_t cpu_mask) 141 { 142 size_t idx = it / 32; 143 uint32_t mask = 1 << (it % 32); 144 uint32_t target; 145 146 assert(it <= gic.max_it); /* Not too large */ 147 /* Assigned to group0 */ 148 assert(!(read32(gic.gicd_base + GICD_IGROUPR(idx)) & mask)); 149 150 /* Route it to selected CPUs */ 151 target = read32(gic.gicd_base + GICD_ITARGETSR(it / 4)); 152 target &= ~(0xff << ((it % 4) * 8)); 153 target |= cpu_mask << ((it % 4) * 8); 154 DMSG("cpu_mask: writing 0x%x to 0x%x\n", 155 target, gic.gicd_base + GICD_ITARGETSR(it / 4)); 156 write32(target, gic.gicd_base + GICD_ITARGETSR(it / 4)); 157 DMSG("cpu_mask: 0x%x\n", 158 read32(gic.gicd_base + GICD_ITARGETSR(it / 4))); 159 } 160 161 void gic_it_set_prio(size_t it, uint8_t prio) 162 { 163 size_t idx = it / 32; 164 uint32_t mask = 1 << (it % 32); 165 166 assert(it <= gic.max_it); /* Not too large */ 167 /* Assigned to group0 */ 168 assert(!(read32(gic.gicd_base + GICD_IGROUPR(idx)) & mask)); 169 170 /* Set prio it to selected CPUs */ 171 DMSG("prio: writing 0x%x to 0x%x\n", 172 prio, gic.gicd_base + GICD_IPRIORITYR(0) + it); 173 write8(prio, gic.gicd_base + GICD_IPRIORITYR(0) + it); 174 } 175 176 void gic_it_enable(size_t it) 177 { 178 size_t idx = it / 32; 179 uint32_t mask = 1 << (it % 32); 180 181 assert(it <= gic.max_it); /* Not too large */ 182 /* Assigned to group0 */ 183 assert(!(read32(gic.gicd_base + GICD_IGROUPR(idx)) & mask)); 184 /* Not enabled yet */ 185 assert(!(read32(gic.gicd_base + GICD_ISENABLER(idx)) & mask)); 186 187 /* Enable the interrupt */ 188 write32(mask, gic.gicd_base + GICD_ISENABLER(idx)); 189 } 190 191 void gic_it_disable(size_t it) 192 { 193 size_t idx = it / 32; 194 uint32_t mask = 1 << (it % 32); 195 196 assert(it <= gic.max_it); /* Not too large */ 197 /* Assigned to group0 */ 198 assert(!(read32(gic.gicd_base + GICD_IGROUPR(idx)) & mask)); 199 200 /* Disable the interrupt */ 201 write32(mask, gic.gicd_base + GICD_ICENABLER(idx)); 202 } 203 204 uint32_t gic_read_iar(void) 205 { 206 return read32(gic.gicc_base + GICC_IAR); 207 } 208 209 void gic_write_eoir(uint32_t eoir) 210 { 211 write32(eoir, gic.gicc_base + GICC_EOIR); 212 } 213 214