1 /* 2 * Copyright (c) 2016, Linaro Limited 3 * Copyright (c) 2014, STMicroelectronics International N.V. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <assert.h> 30 #include <drivers/gic.h> 31 #include <kernel/interrupt.h> 32 #include <kernel/panic.h> 33 #include <util.h> 34 #include <io.h> 35 #include <trace.h> 36 37 /* Offsets from gic.gicc_base */ 38 #define GICC_CTLR (0x000) 39 #define GICC_PMR (0x004) 40 #define GICC_IAR (0x00C) 41 #define GICC_EOIR (0x010) 42 43 #define GICC_CTLR_ENABLEGRP0 (1 << 0) 44 #define GICC_CTLR_ENABLEGRP1 (1 << 1) 45 #define GICC_CTLR_FIQEN (1 << 3) 46 47 /* Offsets from gic.gicd_base */ 48 #define GICD_CTLR (0x000) 49 #define GICD_TYPER (0x004) 50 #define GICD_IGROUPR(n) (0x080 + (n) * 4) 51 #define GICD_ISENABLER(n) (0x100 + (n) * 4) 52 #define GICD_ICENABLER(n) (0x180 + (n) * 4) 53 #define GICD_ICPENDR(n) (0x280 + (n) * 4) 54 #define GICD_IPRIORITYR(n) (0x400 + (n) * 4) 55 #define GICD_ITARGETSR(n) (0x800 + (n) * 4) 56 57 #define GICD_CTLR_ENABLEGRP0 (1 << 0) 58 #define GICD_CTLR_ENABLEGRP1 (1 << 1) 59 60 /* Number of Private Peripheral Interrupt */ 61 #define NUM_PPI 32 62 63 /* Number of interrupts in one register */ 64 #define NUM_INTS_PER_REG 32 65 66 /* Number of targets in one register */ 67 #define NUM_TARGETS_PER_REG 4 68 69 /* Accessors to access ITARGETSRn */ 70 #define ITARGETSR_FIELD_BITS 8 71 #define ITARGETSR_FIELD_MASK 0xff 72 73 /* Maximum number of interrups a GIC can support */ 74 #define GIC_MAX_INTS 1020 75 76 #define GIC_SPURIOUS_ID 1023 77 78 #define GICC_IAR_IT_ID_MASK 0x3ff 79 #define GICC_IAR_CPU_ID_MASK 0x7 80 #define GICC_IAR_CPU_ID_SHIFT 10 81 82 static void gic_op_add(struct itr_chip *chip, size_t it, uint32_t flags); 83 static void gic_op_enable(struct itr_chip *chip, size_t it); 84 static void gic_op_disable(struct itr_chip *chip, size_t it); 85 86 static const struct itr_ops gic_ops = { 87 .add = gic_op_add, 88 .enable = gic_op_enable, 89 .disable = gic_op_disable, 90 }; 91 92 static size_t probe_max_it(vaddr_t gicc_base, vaddr_t gicd_base) 93 { 94 int i; 95 uint32_t old_ctlr; 96 size_t ret = 0; 97 const size_t max_regs = ((GIC_MAX_INTS + NUM_INTS_PER_REG - 1) / 98 NUM_INTS_PER_REG) - 1; 99 100 /* 101 * Probe which interrupt number is the largest. 102 */ 103 old_ctlr = read32(gicc_base + GICC_CTLR); 104 write32(0, gicc_base + GICC_CTLR); 105 for (i = max_regs; i >= 0; i--) { 106 uint32_t old_reg; 107 uint32_t reg; 108 int b; 109 110 old_reg = read32(gicd_base + GICD_ISENABLER(i)); 111 write32(0xffffffff, gicd_base + GICD_ISENABLER(i)); 112 reg = read32(gicd_base + GICD_ISENABLER(i)); 113 write32(old_reg, gicd_base + GICD_ICENABLER(i)); 114 for (b = NUM_INTS_PER_REG - 1; b >= 0; b--) { 115 if (BIT32(b) & reg) { 116 ret = i * NUM_INTS_PER_REG + b; 117 goto out; 118 } 119 } 120 } 121 out: 122 write32(old_ctlr, gicc_base + GICC_CTLR); 123 return ret; 124 } 125 126 void gic_cpu_init(struct gic_data *gd) 127 { 128 /* per-CPU interrupts config: 129 * ID0-ID7(SGI) for Non-secure interrupts 130 * ID8-ID15(SGI) for Secure interrupts. 131 * All PPI config as Non-secure interrupts. 132 */ 133 write32(0xffff00ff, gd->gicd_base + GICD_IGROUPR(0)); 134 135 /* Set the priority mask to permit Non-secure interrupts, and to 136 * allow the Non-secure world to adjust the priority mask itself 137 */ 138 write32(0x80, gd->gicc_base + GICC_PMR); 139 140 /* Enable GIC */ 141 write32(GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 | GICC_CTLR_FIQEN, 142 gd->gicc_base + GICC_CTLR); 143 } 144 145 void gic_init(struct gic_data *gd, vaddr_t gicc_base, vaddr_t gicd_base) 146 { 147 size_t n; 148 149 gic_init_base_addr(gd, gicc_base, gicd_base); 150 151 for (n = 0; n <= gd->max_it / NUM_INTS_PER_REG; n++) { 152 /* Disable interrupts */ 153 write32(0xffffffff, gd->gicd_base + GICD_ICENABLER(n)); 154 155 /* Make interrupts non-pending */ 156 write32(0xffffffff, gd->gicd_base + GICD_ICPENDR(n)); 157 158 /* Mark interrupts non-secure */ 159 if (n == 0) { 160 /* per-CPU inerrupts config: 161 * ID0-ID7(SGI) for Non-secure interrupts 162 * ID8-ID15(SGI) for Secure interrupts. 163 * All PPI config as Non-secure interrupts. 164 */ 165 write32(0xffff00ff, gd->gicd_base + GICD_IGROUPR(n)); 166 } else { 167 write32(0xffffffff, gd->gicd_base + GICD_IGROUPR(n)); 168 } 169 } 170 171 /* Set the priority mask to permit Non-secure interrupts, and to 172 * allow the Non-secure world to adjust the priority mask itself 173 */ 174 write32(0x80, gd->gicc_base + GICC_PMR); 175 176 /* Enable GIC */ 177 write32(GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 | GICC_CTLR_FIQEN, 178 gd->gicc_base + GICC_CTLR); 179 write32(GICD_CTLR_ENABLEGRP0 | GICD_CTLR_ENABLEGRP1, 180 gd->gicd_base + GICD_CTLR); 181 } 182 183 void gic_init_base_addr(struct gic_data *gd, vaddr_t gicc_base, 184 vaddr_t gicd_base) 185 { 186 gd->gicc_base = gicc_base; 187 gd->gicd_base = gicd_base; 188 gd->max_it = probe_max_it(gicc_base, gicd_base); 189 gd->chip.ops = &gic_ops; 190 } 191 192 static void gic_it_add(struct gic_data *gd, size_t it) 193 { 194 size_t idx = it / NUM_INTS_PER_REG; 195 uint32_t mask = 1 << (it % NUM_INTS_PER_REG); 196 197 /* Disable the interrupt */ 198 write32(mask, gd->gicd_base + GICD_ICENABLER(idx)); 199 /* Make it non-pending */ 200 write32(mask, gd->gicd_base + GICD_ICPENDR(idx)); 201 /* Assign it to group0 */ 202 write32(read32(gd->gicd_base + GICD_IGROUPR(idx)) & ~mask, 203 gd->gicd_base + GICD_IGROUPR(idx)); 204 } 205 206 static void gic_it_set_cpu_mask(struct gic_data *gd, size_t it, 207 uint8_t cpu_mask) 208 { 209 size_t idx __maybe_unused = it / NUM_INTS_PER_REG; 210 uint32_t mask __maybe_unused = 1 << (it % NUM_INTS_PER_REG); 211 uint32_t target, target_shift; 212 213 /* Assigned to group0 */ 214 assert(!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask)); 215 216 /* Route it to selected CPUs */ 217 target = read32(gd->gicd_base + 218 GICD_ITARGETSR(it / NUM_TARGETS_PER_REG)); 219 target_shift = (it % NUM_TARGETS_PER_REG) * ITARGETSR_FIELD_BITS; 220 target &= ~(ITARGETSR_FIELD_MASK << target_shift); 221 target |= cpu_mask << target_shift; 222 DMSG("cpu_mask: writing 0x%x to 0x%" PRIxVA, 223 target, gd->gicd_base + GICD_ITARGETSR(it / NUM_TARGETS_PER_REG)); 224 write32(target, 225 gd->gicd_base + GICD_ITARGETSR(it / NUM_TARGETS_PER_REG)); 226 DMSG("cpu_mask: 0x%x\n", 227 read32(gd->gicd_base + GICD_ITARGETSR(it / NUM_TARGETS_PER_REG))); 228 } 229 230 static void gic_it_set_prio(struct gic_data *gd, size_t it, uint8_t prio) 231 { 232 size_t idx __maybe_unused = it / NUM_INTS_PER_REG; 233 uint32_t mask __maybe_unused = 1 << (it % NUM_INTS_PER_REG); 234 235 /* Assigned to group0 */ 236 assert(!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask)); 237 238 /* Set prio it to selected CPUs */ 239 DMSG("prio: writing 0x%x to 0x%" PRIxVA, 240 prio, gd->gicd_base + GICD_IPRIORITYR(0) + it); 241 write8(prio, gd->gicd_base + GICD_IPRIORITYR(0) + it); 242 } 243 244 static void gic_it_enable(struct gic_data *gd, size_t it) 245 { 246 size_t idx = it / NUM_INTS_PER_REG; 247 uint32_t mask = 1 << (it % NUM_INTS_PER_REG); 248 249 /* Assigned to group0 */ 250 assert(!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask)); 251 /* Not enabled yet */ 252 assert(!(read32(gd->gicd_base + GICD_ISENABLER(idx)) & mask)); 253 254 /* Enable the interrupt */ 255 write32(mask, gd->gicd_base + GICD_ISENABLER(idx)); 256 } 257 258 static void gic_it_disable(struct gic_data *gd, size_t it) 259 { 260 size_t idx = it / NUM_INTS_PER_REG; 261 uint32_t mask = 1 << (it % NUM_INTS_PER_REG); 262 263 /* Assigned to group0 */ 264 assert(!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask)); 265 266 /* Disable the interrupt */ 267 write32(mask, gd->gicd_base + GICD_ICENABLER(idx)); 268 } 269 270 static uint32_t gic_read_iar(struct gic_data *gd) 271 { 272 return read32(gd->gicc_base + GICC_IAR); 273 } 274 275 static void gic_write_eoir(struct gic_data *gd, uint32_t eoir) 276 { 277 write32(eoir, gd->gicc_base + GICC_EOIR); 278 } 279 280 static bool gic_it_is_enabled(struct gic_data *gd, size_t it) 281 { 282 size_t idx = it / NUM_INTS_PER_REG; 283 uint32_t mask = 1 << (it % NUM_INTS_PER_REG); 284 return !!(read32(gd->gicd_base + GICD_ISENABLER(idx)) & mask); 285 } 286 287 static bool __maybe_unused gic_it_get_group(struct gic_data *gd, size_t it) 288 { 289 size_t idx = it / NUM_INTS_PER_REG; 290 uint32_t mask = 1 << (it % NUM_INTS_PER_REG); 291 return !!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask); 292 } 293 294 static uint32_t __maybe_unused gic_it_get_target(struct gic_data *gd, size_t it) 295 { 296 size_t reg_idx = it / NUM_TARGETS_PER_REG; 297 uint32_t target_shift = (it % NUM_TARGETS_PER_REG) * 298 ITARGETSR_FIELD_BITS; 299 uint32_t target_mask = ITARGETSR_FIELD_MASK << target_shift; 300 uint32_t target = 301 read32(gd->gicd_base + GICD_ITARGETSR(reg_idx)) & target_mask; 302 303 target = target >> target_shift; 304 return target; 305 } 306 307 void gic_dump_state(struct gic_data *gd) 308 { 309 int i; 310 311 DMSG("GICC_CTLR: 0x%x", read32(gd->gicc_base + GICC_CTLR)); 312 DMSG("GICD_CTLR: 0x%x", read32(gd->gicd_base + GICD_CTLR)); 313 314 for (i = 0; i < (int)gd->max_it; i++) { 315 if (gic_it_is_enabled(gd, i)) { 316 DMSG("irq%d: enabled, group:%d, target:%x", i, 317 gic_it_get_group(gd, i), gic_it_get_target(gd, i)); 318 } 319 } 320 } 321 322 void gic_it_handle(struct gic_data *gd) 323 { 324 uint32_t iar; 325 uint32_t id; 326 327 iar = gic_read_iar(gd); 328 id = iar & GICC_IAR_IT_ID_MASK; 329 330 if (id == GIC_SPURIOUS_ID) 331 DMSG("ignoring spurious interrupt"); 332 else 333 itr_handle(id); 334 335 gic_write_eoir(gd, iar); 336 } 337 338 static void gic_op_add(struct itr_chip *chip, size_t it, 339 uint32_t flags __unused) 340 { 341 struct gic_data *gd = container_of(chip, struct gic_data, chip); 342 343 if (it >= gd->max_it) 344 panic(); 345 346 gic_it_add(gd, it); 347 /* Set the CPU mask to deliver interrupts to any online core */ 348 gic_it_set_cpu_mask(gd, it, 0xff); 349 gic_it_set_prio(gd, it, 0x1); 350 } 351 352 static void gic_op_enable(struct itr_chip *chip, size_t it) 353 { 354 struct gic_data *gd = container_of(chip, struct gic_data, chip); 355 356 if (it >= gd->max_it) 357 panic(); 358 359 gic_it_enable(gd, it); 360 } 361 362 static void gic_op_disable(struct itr_chip *chip, size_t it) 363 { 364 struct gic_data *gd = container_of(chip, struct gic_data, chip); 365 366 if (it >= gd->max_it) 367 panic(); 368 369 gic_it_disable(gd, it); 370 } 371