1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2016-2017, Linaro Limited 4 * Copyright (c) 2014, STMicroelectronics International N.V. 5 */ 6 7 #include <arm.h> 8 #include <assert.h> 9 #include <drivers/gic.h> 10 #include <keep.h> 11 #include <kernel/interrupt.h> 12 #include <kernel/panic.h> 13 #include <util.h> 14 #include <io.h> 15 #include <trace.h> 16 17 /* Offsets from gic.gicc_base */ 18 #define GICC_CTLR (0x000) 19 #define GICC_PMR (0x004) 20 #define GICC_IAR (0x00C) 21 #define GICC_EOIR (0x010) 22 23 #define GICC_CTLR_ENABLEGRP0 (1 << 0) 24 #define GICC_CTLR_ENABLEGRP1 (1 << 1) 25 #define GICC_CTLR_FIQEN (1 << 3) 26 27 /* Offsets from gic.gicd_base */ 28 #define GICD_CTLR (0x000) 29 #define GICD_TYPER (0x004) 30 #define GICD_IGROUPR(n) (0x080 + (n) * 4) 31 #define GICD_ISENABLER(n) (0x100 + (n) * 4) 32 #define GICD_ICENABLER(n) (0x180 + (n) * 4) 33 #define GICD_ISPENDR(n) (0x200 + (n) * 4) 34 #define GICD_ICPENDR(n) (0x280 + (n) * 4) 35 #define GICD_IPRIORITYR(n) (0x400 + (n) * 4) 36 #define GICD_ITARGETSR(n) (0x800 + (n) * 4) 37 #define GICD_SGIR (0xF00) 38 39 #define GICD_CTLR_ENABLEGRP0 (1 << 0) 40 #define GICD_CTLR_ENABLEGRP1 (1 << 1) 41 42 /* Number of Private Peripheral Interrupt */ 43 #define NUM_PPI 32 44 45 /* Number of Software Generated Interrupt */ 46 #define NUM_SGI 16 47 48 /* Number of Non-secure Software Generated Interrupt */ 49 #define NUM_NS_SGI 8 50 51 /* Number of interrupts in one register */ 52 #define NUM_INTS_PER_REG 32 53 54 /* Number of targets in one register */ 55 #define NUM_TARGETS_PER_REG 4 56 57 /* Accessors to access ITARGETSRn */ 58 #define ITARGETSR_FIELD_BITS 8 59 #define ITARGETSR_FIELD_MASK 0xff 60 61 /* Maximum number of interrups a GIC can support */ 62 #define GIC_MAX_INTS 1020 63 64 #define GICC_IAR_IT_ID_MASK 0x3ff 65 #define GICC_IAR_CPU_ID_MASK 0x7 66 #define GICC_IAR_CPU_ID_SHIFT 10 67 68 static void gic_op_add(struct itr_chip *chip, size_t it, uint32_t flags); 69 static void gic_op_enable(struct itr_chip *chip, size_t it); 70 static void gic_op_disable(struct itr_chip *chip, size_t it); 71 static void gic_op_raise_pi(struct itr_chip *chip, size_t it); 72 static void gic_op_raise_sgi(struct itr_chip *chip, size_t it, 73 uint8_t cpu_mask); 74 static void gic_op_set_affinity(struct itr_chip *chip, size_t it, 75 uint8_t cpu_mask); 76 77 static const struct itr_ops gic_ops = { 78 .add = gic_op_add, 79 .enable = gic_op_enable, 80 .disable = gic_op_disable, 81 .raise_pi = gic_op_raise_pi, 82 .raise_sgi = gic_op_raise_sgi, 83 .set_affinity = gic_op_set_affinity, 84 }; 85 KEEP_PAGER(gic_ops); 86 87 static size_t probe_max_it(vaddr_t gicc_base __maybe_unused, vaddr_t gicd_base) 88 { 89 int i; 90 uint32_t old_ctlr; 91 size_t ret = 0; 92 const size_t max_regs = ((GIC_MAX_INTS + NUM_INTS_PER_REG - 1) / 93 NUM_INTS_PER_REG) - 1; 94 95 /* 96 * Probe which interrupt number is the largest. 97 */ 98 #if defined(CFG_ARM_GICV3) 99 old_ctlr = read_icc_ctlr(); 100 write_icc_ctlr(0); 101 #else 102 old_ctlr = read32(gicc_base + GICC_CTLR); 103 write32(0, gicc_base + GICC_CTLR); 104 #endif 105 for (i = max_regs; i >= 0; i--) { 106 uint32_t old_reg; 107 uint32_t reg; 108 int b; 109 110 old_reg = read32(gicd_base + GICD_ISENABLER(i)); 111 write32(0xffffffff, gicd_base + GICD_ISENABLER(i)); 112 reg = read32(gicd_base + GICD_ISENABLER(i)); 113 write32(old_reg, gicd_base + GICD_ICENABLER(i)); 114 for (b = NUM_INTS_PER_REG - 1; b >= 0; b--) { 115 if (BIT32(b) & reg) { 116 ret = i * NUM_INTS_PER_REG + b; 117 goto out; 118 } 119 } 120 } 121 out: 122 #if defined(CFG_ARM_GICV3) 123 write_icc_ctlr(old_ctlr); 124 #else 125 write32(old_ctlr, gicc_base + GICC_CTLR); 126 #endif 127 return ret; 128 } 129 130 void gic_cpu_init(struct gic_data *gd) 131 { 132 #if defined(CFG_ARM_GICV3) 133 assert(gd->gicd_base); 134 #else 135 assert(gd->gicd_base && gd->gicc_base); 136 #endif 137 138 /* per-CPU interrupts config: 139 * ID0-ID7(SGI) for Non-secure interrupts 140 * ID8-ID15(SGI) for Secure interrupts. 141 * All PPI config as Non-secure interrupts. 142 */ 143 write32(0xffff00ff, gd->gicd_base + GICD_IGROUPR(0)); 144 145 /* Set the priority mask to permit Non-secure interrupts, and to 146 * allow the Non-secure world to adjust the priority mask itself 147 */ 148 #if defined(CFG_ARM_GICV3) 149 write_icc_pmr(0x80); 150 write_icc_ctlr(GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 | 151 GICC_CTLR_FIQEN); 152 #else 153 write32(0x80, gd->gicc_base + GICC_PMR); 154 155 /* Enable GIC */ 156 write32(GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 | GICC_CTLR_FIQEN, 157 gd->gicc_base + GICC_CTLR); 158 #endif 159 } 160 161 void gic_init(struct gic_data *gd, vaddr_t gicc_base __maybe_unused, 162 vaddr_t gicd_base) 163 { 164 size_t n; 165 166 gic_init_base_addr(gd, gicc_base, gicd_base); 167 168 for (n = 0; n <= gd->max_it / NUM_INTS_PER_REG; n++) { 169 /* Disable interrupts */ 170 write32(0xffffffff, gd->gicd_base + GICD_ICENABLER(n)); 171 172 /* Make interrupts non-pending */ 173 write32(0xffffffff, gd->gicd_base + GICD_ICPENDR(n)); 174 175 /* Mark interrupts non-secure */ 176 if (n == 0) { 177 /* per-CPU inerrupts config: 178 * ID0-ID7(SGI) for Non-secure interrupts 179 * ID8-ID15(SGI) for Secure interrupts. 180 * All PPI config as Non-secure interrupts. 181 */ 182 write32(0xffff00ff, gd->gicd_base + GICD_IGROUPR(n)); 183 } else { 184 write32(0xffffffff, gd->gicd_base + GICD_IGROUPR(n)); 185 } 186 } 187 188 /* Set the priority mask to permit Non-secure interrupts, and to 189 * allow the Non-secure world to adjust the priority mask itself 190 */ 191 #if defined(CFG_ARM_GICV3) 192 write_icc_pmr(0x80); 193 write_icc_ctlr(GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 | 194 GICC_CTLR_FIQEN); 195 #else 196 write32(0x80, gd->gicc_base + GICC_PMR); 197 198 /* Enable GIC */ 199 write32(GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1 | GICC_CTLR_FIQEN, 200 gd->gicc_base + GICC_CTLR); 201 #endif 202 write32(read32(gd->gicd_base + GICD_CTLR) | GICD_CTLR_ENABLEGRP0 | 203 GICD_CTLR_ENABLEGRP1, gd->gicd_base + GICD_CTLR); 204 } 205 206 void gic_init_base_addr(struct gic_data *gd, vaddr_t gicc_base __maybe_unused, 207 vaddr_t gicd_base) 208 { 209 gd->gicc_base = gicc_base; 210 gd->gicd_base = gicd_base; 211 gd->max_it = probe_max_it(gicc_base, gicd_base); 212 gd->chip.ops = &gic_ops; 213 } 214 215 static void gic_it_add(struct gic_data *gd, size_t it) 216 { 217 size_t idx = it / NUM_INTS_PER_REG; 218 uint32_t mask = 1 << (it % NUM_INTS_PER_REG); 219 220 /* Disable the interrupt */ 221 write32(mask, gd->gicd_base + GICD_ICENABLER(idx)); 222 /* Make it non-pending */ 223 write32(mask, gd->gicd_base + GICD_ICPENDR(idx)); 224 /* Assign it to group0 */ 225 write32(read32(gd->gicd_base + GICD_IGROUPR(idx)) & ~mask, 226 gd->gicd_base + GICD_IGROUPR(idx)); 227 } 228 229 static void gic_it_set_cpu_mask(struct gic_data *gd, size_t it, 230 uint8_t cpu_mask) 231 { 232 size_t idx __maybe_unused = it / NUM_INTS_PER_REG; 233 uint32_t mask __maybe_unused = 1 << (it % NUM_INTS_PER_REG); 234 uint32_t target, target_shift; 235 236 /* Assigned to group0 */ 237 assert(!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask)); 238 239 /* Route it to selected CPUs */ 240 target = read32(gd->gicd_base + 241 GICD_ITARGETSR(it / NUM_TARGETS_PER_REG)); 242 target_shift = (it % NUM_TARGETS_PER_REG) * ITARGETSR_FIELD_BITS; 243 target &= ~(ITARGETSR_FIELD_MASK << target_shift); 244 target |= cpu_mask << target_shift; 245 DMSG("cpu_mask: writing 0x%x to 0x%" PRIxVA, 246 target, gd->gicd_base + GICD_ITARGETSR(it / NUM_TARGETS_PER_REG)); 247 write32(target, 248 gd->gicd_base + GICD_ITARGETSR(it / NUM_TARGETS_PER_REG)); 249 DMSG("cpu_mask: 0x%x\n", 250 read32(gd->gicd_base + GICD_ITARGETSR(it / NUM_TARGETS_PER_REG))); 251 } 252 253 static void gic_it_set_prio(struct gic_data *gd, size_t it, uint8_t prio) 254 { 255 size_t idx __maybe_unused = it / NUM_INTS_PER_REG; 256 uint32_t mask __maybe_unused = 1 << (it % NUM_INTS_PER_REG); 257 258 /* Assigned to group0 */ 259 assert(!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask)); 260 261 /* Set prio it to selected CPUs */ 262 DMSG("prio: writing 0x%x to 0x%" PRIxVA, 263 prio, gd->gicd_base + GICD_IPRIORITYR(0) + it); 264 write8(prio, gd->gicd_base + GICD_IPRIORITYR(0) + it); 265 } 266 267 static void gic_it_enable(struct gic_data *gd, size_t it) 268 { 269 size_t idx = it / NUM_INTS_PER_REG; 270 uint32_t mask = 1 << (it % NUM_INTS_PER_REG); 271 272 /* Assigned to group0 */ 273 assert(!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask)); 274 if (it >= NUM_SGI) { 275 /* 276 * Not enabled yet, except Software Generated Interrupt 277 * which is implementation defined 278 */ 279 assert(!(read32(gd->gicd_base + GICD_ISENABLER(idx)) & mask)); 280 } 281 282 /* Enable the interrupt */ 283 write32(mask, gd->gicd_base + GICD_ISENABLER(idx)); 284 } 285 286 static void gic_it_disable(struct gic_data *gd, size_t it) 287 { 288 size_t idx = it / NUM_INTS_PER_REG; 289 uint32_t mask = 1 << (it % NUM_INTS_PER_REG); 290 291 /* Assigned to group0 */ 292 assert(!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask)); 293 294 /* Disable the interrupt */ 295 write32(mask, gd->gicd_base + GICD_ICENABLER(idx)); 296 } 297 298 static void gic_it_set_pending(struct gic_data *gd, size_t it) 299 { 300 size_t idx = it / NUM_INTS_PER_REG; 301 uint32_t mask = BIT32(it % NUM_INTS_PER_REG); 302 303 /* Should be Peripheral Interrupt */ 304 assert(it >= NUM_SGI); 305 /* Assigned to group0 */ 306 assert(!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask)); 307 308 /* Raise the interrupt */ 309 write32(mask, gd->gicd_base + GICD_ISPENDR(idx)); 310 } 311 312 static void gic_it_raise_sgi(struct gic_data *gd, size_t it, 313 uint8_t cpu_mask, uint8_t group) 314 { 315 uint32_t mask_id = it & 0xf; 316 uint32_t mask_group = group & 0x1; 317 uint32_t mask_cpu = cpu_mask & 0xff; 318 uint32_t mask = (mask_id | SHIFT_U32(mask_group, 15) | 319 SHIFT_U32(mask_cpu, 16)); 320 321 /* Should be Software Generated Interrupt */ 322 assert(it < NUM_SGI); 323 324 /* Raise the interrupt */ 325 write32(mask, gd->gicd_base + GICD_SGIR); 326 } 327 328 static uint32_t gic_read_iar(struct gic_data *gd __maybe_unused) 329 { 330 #if defined(CFG_ARM_GICV3) 331 return read_icc_iar1(); 332 #else 333 return read32(gd->gicc_base + GICC_IAR); 334 #endif 335 } 336 337 static void gic_write_eoir(struct gic_data *gd __maybe_unused, uint32_t eoir) 338 { 339 #if defined(CFG_ARM_GICV3) 340 write_icc_eoir1(eoir); 341 #else 342 write32(eoir, gd->gicc_base + GICC_EOIR); 343 #endif 344 } 345 346 static bool gic_it_is_enabled(struct gic_data *gd, size_t it) 347 { 348 size_t idx = it / NUM_INTS_PER_REG; 349 uint32_t mask = 1 << (it % NUM_INTS_PER_REG); 350 return !!(read32(gd->gicd_base + GICD_ISENABLER(idx)) & mask); 351 } 352 353 static bool __maybe_unused gic_it_get_group(struct gic_data *gd, size_t it) 354 { 355 size_t idx = it / NUM_INTS_PER_REG; 356 uint32_t mask = 1 << (it % NUM_INTS_PER_REG); 357 return !!(read32(gd->gicd_base + GICD_IGROUPR(idx)) & mask); 358 } 359 360 static uint32_t __maybe_unused gic_it_get_target(struct gic_data *gd, size_t it) 361 { 362 size_t reg_idx = it / NUM_TARGETS_PER_REG; 363 uint32_t target_shift = (it % NUM_TARGETS_PER_REG) * 364 ITARGETSR_FIELD_BITS; 365 uint32_t target_mask = ITARGETSR_FIELD_MASK << target_shift; 366 uint32_t target = 367 read32(gd->gicd_base + GICD_ITARGETSR(reg_idx)) & target_mask; 368 369 target = target >> target_shift; 370 return target; 371 } 372 373 void gic_dump_state(struct gic_data *gd) 374 { 375 int i; 376 377 #if defined(CFG_ARM_GICV3) 378 DMSG("GICC_CTLR: 0x%x", read_icc_ctlr()); 379 #else 380 DMSG("GICC_CTLR: 0x%x", read32(gd->gicc_base + GICC_CTLR)); 381 #endif 382 DMSG("GICD_CTLR: 0x%x", read32(gd->gicd_base + GICD_CTLR)); 383 384 for (i = 0; i < (int)gd->max_it; i++) { 385 if (gic_it_is_enabled(gd, i)) { 386 DMSG("irq%d: enabled, group:%d, target:%x", i, 387 gic_it_get_group(gd, i), gic_it_get_target(gd, i)); 388 } 389 } 390 } 391 392 void gic_it_handle(struct gic_data *gd) 393 { 394 uint32_t iar; 395 uint32_t id; 396 397 iar = gic_read_iar(gd); 398 id = iar & GICC_IAR_IT_ID_MASK; 399 400 if (id < gd->max_it) 401 itr_handle(id); 402 else 403 DMSG("ignoring interrupt %" PRIu32, id); 404 405 gic_write_eoir(gd, iar); 406 } 407 408 static void gic_op_add(struct itr_chip *chip, size_t it, 409 uint32_t flags __unused) 410 { 411 struct gic_data *gd = container_of(chip, struct gic_data, chip); 412 413 if (it >= gd->max_it) 414 panic(); 415 416 gic_it_add(gd, it); 417 /* Set the CPU mask to deliver interrupts to any online core */ 418 gic_it_set_cpu_mask(gd, it, 0xff); 419 gic_it_set_prio(gd, it, 0x1); 420 } 421 422 static void gic_op_enable(struct itr_chip *chip, size_t it) 423 { 424 struct gic_data *gd = container_of(chip, struct gic_data, chip); 425 426 if (it >= gd->max_it) 427 panic(); 428 429 gic_it_enable(gd, it); 430 } 431 432 static void gic_op_disable(struct itr_chip *chip, size_t it) 433 { 434 struct gic_data *gd = container_of(chip, struct gic_data, chip); 435 436 if (it >= gd->max_it) 437 panic(); 438 439 gic_it_disable(gd, it); 440 } 441 442 static void gic_op_raise_pi(struct itr_chip *chip, size_t it) 443 { 444 struct gic_data *gd = container_of(chip, struct gic_data, chip); 445 446 if (it >= gd->max_it) 447 panic(); 448 449 gic_it_set_pending(gd, it); 450 } 451 452 static void gic_op_raise_sgi(struct itr_chip *chip, size_t it, 453 uint8_t cpu_mask) 454 { 455 struct gic_data *gd = container_of(chip, struct gic_data, chip); 456 457 if (it >= gd->max_it) 458 panic(); 459 460 if (it < NUM_NS_SGI) 461 gic_it_raise_sgi(gd, it, cpu_mask, 1); 462 else 463 gic_it_raise_sgi(gd, it, cpu_mask, 0); 464 } 465 static void gic_op_set_affinity(struct itr_chip *chip, size_t it, 466 uint8_t cpu_mask) 467 { 468 struct gic_data *gd = container_of(chip, struct gic_data, chip); 469 470 if (it >= gd->max_it) 471 panic(); 472 473 gic_it_set_cpu_mask(gd, it, cpu_mask); 474 } 475