xref: /optee_os/core/drivers/crypto/hisilicon/hpre_main.h (revision b6a44cc5a792f1ca0c8f4fc0a9ae33f1017c1e2f)
1 /* SPDX-License-Identifier: BSD-2-Clause */
2 /*
3  * Copyright (c) 2024 HiSilicon Limited.
4  */
5 #ifndef _HPRE_MAIN_H
6 #define _HPRE_MAIN_H
7 
8 #include "hisi_qm.h"
9 
10 #define HPRE_BAR_BASE		0x150000000
11 #define HPRE_BAR_SIZE		0x400000
12 #define HPRE_SQE_SIZE		64
13 #define HPRE_SQE_LOG2_SIZE	6
14 #define HPRE_SQE_SM2_KSEL_SHIFT	1
15 #define HPRE_SQE_BD_RSV2_SHIFT	7
16 #define HPRE_HW_TASK_INIT	0x1
17 #define HPRE_HW_TASK_DONE	0x3
18 #define TASK_LENGTH(len)	((len) / 8 - 1)
19 #define BITS_TO_BYTES(len)	(((len) + 7) / 8)
20 #define BYTES_TO_BITS(len)	((len) * 8)
21 
22 #define HPRE_ETYPE_SHIFT	5
23 #define HPRE_ETYPE_MASK		0x7ff
24 #define HPRE_ETYPE1_SHIFT	16
25 #define HPRE_ETYPE1_MASK	0x3fff
26 #define HPRE_DONE_SHIFT		30
27 #define HPRE_DONE_MASK		0x3
28 #define HPRE_TASK_ETYPE(w0)	(((w0) >> HPRE_ETYPE_SHIFT) & HPRE_ETYPE_MASK)
29 #define HPRE_TASK_ETYPE1(w0)	(((w0) >> HPRE_ETYPE1_SHIFT) & HPRE_ETYPE1_MASK)
30 #define HPRE_TASK_DONE(w0)	(((w0) >> HPRE_DONE_SHIFT) & HPRE_DONE_MASK)
31 
32 struct hpre_sqe {
33 	/*
34 	 * alg : 5
35 	 * etype : 11
36 	 * etype1 : 14
37 	 * done : 2
38 	 */
39 	uint32_t w0;
40 
41 	uint8_t task_len1;
42 	uint8_t task_len2;
43 	uint8_t mrttest_num;
44 	/*
45 	 * uwkey_enb : 1
46 	 * sm2_ksel : 1
47 	 * sva_bypass : 1
48 	 * sva_status : 4
49 	 * bd_rsv2 : 1
50 	 */
51 	uint8_t ext1;
52 
53 	uint64_t key;
54 	uint64_t in;
55 	uint64_t out;
56 	uint64_t tag;
57 
58 	uint16_t sm2enc_klen;
59 	/*
60 	 * uwkey_sel : 4
61 	 * uwkey_wrap_num : 3
62 	 * rsvd2 : 9
63 	 */
64 	uint16_t ext2;
65 
66 	uint64_t kek_key;
67 	uint32_t rsv[3];
68 };
69 
70 enum hpre_alg_type {
71 	HPRE_ALG_NC_NCRT = 0x0,
72 	HPRE_ALG_NC_CRT = 0x1,
73 	HPRE_ALG_KG_STD = 0x2,
74 	HPRE_ALG_KG_CRT = 0x3,
75 	HPRE_ALG_DH_G2 = 0x4,
76 	HPRE_ALG_DH = 0x5,
77 	HPRE_ALG_ECDH_MULTIPLY = 0xD,
78 	HPRE_ALG_ECDSA_SIGN = 0xE,
79 	HPRE_ALG_ECDSA_VERF = 0xF,
80 	HPRE_ALG_X_DH_MULTIPLY = 0x10,
81 	HPRE_ALG_SM2_KEY_GEN = 0x11,
82 	HPRE_ALG_SM2_SIGN = 0x12,
83 	HPRE_ALG_SM2_VERF = 0x13,
84 	HPRE_ALG_SM2_ENC = 0x14,
85 	HPRE_ALG_SM2_DEC = 0x15
86 };
87 
88 uint32_t hpre_init(void);
89 struct hisi_qp *hpre_create_qp(uint8_t sq_type);
90 enum hisi_drv_status hpre_bin_from_crypto_bin(uint8_t *dst, const uint8_t *src,
91 					      uint32_t bsize, uint32_t dsize);
92 enum hisi_drv_status hpre_bin_to_crypto_bin(uint8_t *dst, const uint8_t *src,
93 					    uint32_t bsize, uint32_t dsize);
94 
95 #endif
96