xref: /optee_os/core/drivers/clk/sam/at91_clk.h (revision 750c544ca5b1d498d11b2a16fdfe30411f6ea6ce)
1 /* SPDX-License-Identifier: GPL-2.0+ or BSD-3-Clause */
2 /*
3  * include/linux/clk/at91_pmc.h
4  *
5  * Copyright (C) 2005 Ivan Kokshaysky
6  * Copyright (C) SAN People
7  * Copyright (C) 2021 Microchip
8  *
9  * Power Management Controller (PMC) - System peripherals registers.
10  * Based on AT91RM9200 datasheet revision E.
11  */
12 
13 #ifndef AT91_CLK_H
14 #define AT91_CLK_H
15 
16 #include <drivers/clk.h>
17 #include <drivers/clk_dt.h>
18 
19 #include "at91_pmc.h"
20 
21 #define ffs(x)	__builtin_ffs(x)
22 
23 #define field_get(_mask, _reg) \
24 	({ \
25 		typeof(_mask) __mask = _mask; \
26 		\
27 		(((_reg) & (__mask)) >> (ffs(__mask) - 1)); \
28 	})
29 #define field_prep(_mask, _val)  \
30 	({ \
31 		typeof(_mask) __mask = _mask; \
32 		\
33 		(((_val) << (ffs(__mask) - 1)) & (__mask)); \
34 	})
35 
36 struct clk_range {
37 	unsigned long min;
38 	unsigned long max;
39 };
40 
41 #define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,}
42 
43 struct pmc_clk {
44 	struct clk *clk;
45 	uint8_t id;
46 };
47 
48 struct pmc_data {
49 	vaddr_t base;
50 	unsigned int ncore;
51 	struct pmc_clk *chws;
52 	unsigned int nsystem;
53 	struct pmc_clk *shws;
54 	unsigned int nperiph;
55 	struct pmc_clk *phws;
56 	unsigned int ngck;
57 	struct pmc_clk *ghws;
58 	unsigned int npck;
59 	struct pmc_clk *pchws;
60 
61 	struct pmc_clk hwtable[];
62 };
63 
64 /* PLL */
65 struct clk_pll_layout {
66 	uint32_t pllr_mask;
67 	uint32_t mul_mask;
68 	uint32_t frac_mask;
69 	uint32_t div_mask;
70 	uint32_t endiv_mask;
71 	uint8_t mul_shift;
72 	uint8_t frac_shift;
73 	uint8_t div_shift;
74 	uint8_t endiv_shift;
75 };
76 
77 struct clk_pcr_layout {
78 	uint32_t offset;
79 	uint32_t cmd;
80 	uint32_t div_mask;
81 	uint32_t gckcss_mask;
82 	uint32_t pid_mask;
83 };
84 
85 struct clk_pll_charac {
86 	struct clk_range input;
87 	int num_output;
88 	const struct clk_range *output;
89 	uint16_t *icpll;
90 	uint8_t *out;
91 	uint8_t upll : 1;
92 };
93 
94 extern const struct clk_pll_layout sama5d3_pll_layout;
95 
96 /* Master */
97 struct clk_master_charac {
98 	struct clk_range output;
99 	uint32_t divisors[5];
100 	uint8_t have_div3_pres;
101 };
102 
103 struct clk_master_layout {
104 	uint32_t offset;
105 	uint32_t mask;
106 	uint8_t pres_shift;
107 };
108 
109 struct clk_programmable_layout {
110 	uint8_t pres_mask;
111 	uint8_t pres_shift;
112 	uint8_t css_mask;
113 	uint8_t have_slck_mck;
114 	uint8_t is_pres_direct;
115 };
116 
117 extern const struct clk_master_layout at91sam9x5_master_layout;
118 
119 vaddr_t at91_pmc_get_base(void);
120 
121 TEE_Result at91_pmc_clk_get(unsigned int type, unsigned int idx,
122 			    struct clk **clk);
123 
124 TEE_Result pmc_clk_get(struct pmc_data *pmc, unsigned int type,
125 		       unsigned int idx, struct clk **clk);
126 
127 struct clk *at91_sckc_clk_get(void);
128 
129 struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem,
130 				   unsigned int nperiph, unsigned int ngck,
131 				   unsigned int npck);
132 
133 struct clk *clk_dt_pmc_get(struct dt_driver_phandle_args *args, void *data,
134 			   TEE_Result *res);
135 
136 struct clk *pmc_clk_get_by_name(struct pmc_clk *clks, unsigned int nclk,
137 				const char *name);
138 
139 /* Main clock */
140 struct clk *pmc_register_main_rc_osc(struct pmc_data *pmc, const char *name,
141 				     unsigned long freq);
142 
143 struct clk *pmc_register_main_osc(struct pmc_data *pmc, const char *name,
144 				  struct clk *parent, bool bypass);
145 
146 struct clk *at91_clk_register_sam9x5_main(struct pmc_data *pmc,
147 					  const char *name,
148 					  struct clk **parent_clocks,
149 					  unsigned int num_parents);
150 
151 /* PLL */
152 struct clk *
153 at91_clk_register_pll(struct pmc_data *pmc, const char *name,
154 		      struct clk *parent, uint8_t id,
155 		      const struct clk_pll_layout *layout,
156 		      const struct clk_pll_charac *charac);
157 
158 struct clk *
159 at91_clk_register_plldiv(struct pmc_data *pmc, const char *name,
160 			 struct clk *parent);
161 
162 /* UTMI */
163 struct clk *
164 at91_clk_register_utmi(struct pmc_data *pmc, const char *name,
165 		       struct clk *parent);
166 
167 /* Master */
168 struct clk *
169 at91_clk_register_master_pres(struct pmc_data *pmc,
170 			      const char *name, int num_parents,
171 			      struct clk **parents,
172 			      const struct clk_master_layout *layout,
173 			      const struct clk_master_charac *charac,
174 			      int chg_pid);
175 
176 struct clk *
177 at91_clk_register_master_div(struct pmc_data *pmc,
178 			     const char *name, struct clk *parent,
179 			     const struct clk_master_layout *layout,
180 			     const struct clk_master_charac *charac);
181 
182 /* H32MX */
183 struct clk *
184 at91_clk_register_h32mx(struct pmc_data *pmc, const char *name,
185 			struct clk *parent);
186 
187 /* USB */
188 struct clk *
189 at91sam9x5_clk_register_usb(struct pmc_data *pmc, const char *name,
190 			    struct clk **parents, uint8_t num_parents);
191 
192 /* Programmable */
193 struct clk *
194 at91_clk_register_programmable(struct pmc_data *pmc,
195 			       const char *name, struct clk **parents,
196 			       uint8_t num_parents, uint8_t id,
197 			       const struct clk_programmable_layout *layout);
198 
199 struct clk *
200 at91_clk_register_system(struct pmc_data *pmc, const char *name,
201 			 struct clk *parent, uint8_t id);
202 
203 struct clk *
204 at91_clk_register_sam9x5_periph(struct pmc_data *pmc,
205 				const struct clk_pcr_layout *layout,
206 				const char *name, struct clk *parent,
207 				uint32_t id, const struct clk_range *range);
208 
209 struct clk *
210 at91_clk_register_generated(struct pmc_data *pmc,
211 			    const struct clk_pcr_layout *layout,
212 			    const char *name, struct clk **parents,
213 			    uint8_t num_parents, uint8_t id,
214 			    const struct clk_range *range,
215 			    int chg_pid);
216 
217 struct clk *
218 at91_clk_i2s_mux_register(const char *name, struct clk **parents,
219 			  unsigned int num_parents, uint8_t bus_id);
220 
221 /* Audio PLL */
222 struct clk *
223 at91_clk_register_audio_pll_frac(struct pmc_data *pmc, const char *name,
224 				 struct clk *parent);
225 
226 struct clk *
227 at91_clk_register_audio_pll_pad(struct pmc_data *pmc, const char *name,
228 				struct clk *parent);
229 
230 struct clk *
231 at91_clk_register_audio_pll_pmc(struct pmc_data *pmc, const char *name,
232 				struct clk *parent);
233 
234 #ifdef CFG_PM_ARM32
235 void pmc_register_id(uint8_t id);
236 void pmc_register_pck(uint8_t pck);
237 void pmc_register_pm(void);
238 #else
239 static inline void pmc_register_id(uint8_t id __unused) {}
240 static inline void pmc_register_pck(uint8_t pck __unused) {}
241 static inline void pmc_register_pm(void) {}
242 #endif
243 
244 #endif
245