1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2024, STMicroelectronics 4 */ 5 6 #include <assert.h> 7 #include <config.h> 8 #include <drivers/clk_dt.h> 9 #include <drivers/stm32_shared_io.h> 10 #include <drivers/stm32mp25_rcc.h> 11 #include <drivers/stm32mp_dt_bindings.h> 12 #include <io.h> 13 #include <kernel/dt.h> 14 #include <kernel/panic.h> 15 #include <libfdt.h> 16 #include <stdbool.h> 17 #include <stdio.h> 18 #include <stm32_sysconf.h> 19 #include <stm32_util.h> 20 #include <trace.h> 21 #include <util.h> 22 23 #include "clk-stm32-core.h" 24 25 #define MAX_OPP CFG_STM32MP_OPP_COUNT 26 27 #define TIMEOUT_US_100MS U(100000) 28 #define TIMEOUT_US_200MS U(200000) 29 #define TIMEOUT_US_1S U(1000000) 30 31 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 32 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 33 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 34 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 35 36 /* PLL minimal frequencies for clock sources */ 37 #define PLL_REFCLK_MIN UL(5000000) 38 #define PLL_FRAC_REFCLK_MIN UL(10000000) 39 40 /* Parameters from XBAR_CFG in st,cksrc field */ 41 #define XBAR_CKSRC_CHANNEL GENMASK_32(5, 0) 42 #define XBAR_CKSRC_SRC GENMASK_32(9, 6) 43 #define XBAR_CKSRC_SRC_OFFSET U(6) 44 #define XBAR_CKSRC_PREDIV GENMASK_32(19, 10) 45 #define XBAR_CKSRC_PREDIV_OFFSET U(10) 46 #define XBAR_CKSRC_FINDIV GENMASK_32(25, 20) 47 #define XBAR_CKSRC_FINDIV_OFFSET U(20) 48 49 #define XBAR_CHANNEL_NB U(64) 50 #define XBAR_ROOT_CHANNEL_NB U(7) 51 52 #define FLEX_STGEN U(33) 53 54 #define RCC_0_MHZ UL(0) 55 #define RCC_4_MHZ UL(4000000) 56 #define RCC_16_MHZ UL(16000000) 57 58 enum pll_cfg { 59 FBDIV, 60 REFDIV, 61 POSTDIV1, 62 POSTDIV2, 63 PLLCFG_NB 64 }; 65 66 enum pll_csg { 67 DIVVAL, 68 SPREAD, 69 DOWNSPREAD, 70 PLLCSG_NB 71 }; 72 73 struct stm32_pll_dt_cfg { 74 bool enabled; 75 uint32_t cfg[PLLCFG_NB]; 76 uint32_t csg[PLLCSG_NB]; 77 uint32_t frac; 78 bool csg_enabled; 79 uint32_t src; 80 }; 81 82 struct stm32_osci_dt_cfg { 83 unsigned long freq; 84 bool bypass; 85 bool digbyp; 86 bool css; 87 uint32_t drive; 88 }; 89 90 struct stm32_clk_opp_cfg { 91 uint32_t frq; 92 uint32_t src; 93 struct stm32_pll_dt_cfg pll_cfg; 94 }; 95 96 struct stm32_clk_opp_dt_cfg { 97 struct stm32_clk_opp_cfg cpu1_opp[MAX_OPP]; 98 }; 99 100 struct stm32_clk_platdata { 101 uintptr_t rcc_base; 102 uint32_t nosci; 103 struct stm32_osci_dt_cfg *osci; 104 uint32_t npll; 105 struct stm32_pll_dt_cfg *pll; 106 struct stm32_clk_opp_dt_cfg *opp; 107 uint32_t nbusclk; 108 uint32_t *busclk; 109 uint32_t nkernelclk; 110 uint32_t *kernelclk; 111 uint32_t nflexgen; 112 uint32_t *flexgen; 113 uint32_t c1msrd; 114 bool safe_rst; 115 }; 116 117 /* 118 * GATE CONFIG 119 */ 120 121 /* WARNING GATE_XXX_RDY MUST FOLLOW GATE_XXX */ 122 123 enum enum_gate_cfg { 124 GATE_HSI, 125 GATE_HSI_RDY, 126 GATE_HSE, 127 GATE_HSE_RDY, 128 GATE_LSE, 129 GATE_LSE_RDY, 130 GATE_LSI, 131 GATE_LSI_RDY, 132 GATE_MSI, 133 GATE_MSI_RDY, 134 GATE_PLL1, 135 GATE_PLL1_RDY, 136 GATE_PLL2, 137 GATE_PLL2_RDY, 138 GATE_PLL3, 139 GATE_PLL3_RDY, 140 GATE_PLL4, 141 GATE_PLL4_RDY, 142 GATE_PLL5, 143 GATE_PLL5_RDY, 144 GATE_PLL6, 145 GATE_PLL6_RDY, 146 GATE_PLL7, 147 GATE_PLL7_RDY, 148 GATE_PLL8, 149 GATE_PLL8_RDY, 150 GATE_PLL4_CKREFST, 151 GATE_PLL5_CKREFST, 152 GATE_PLL6_CKREFST, 153 GATE_PLL7_CKREFST, 154 GATE_PLL8_CKREFST, 155 GATE_HSEDIV2, 156 GATE_APB1DIV_RDY, 157 GATE_APB2DIV_RDY, 158 GATE_APB3DIV_RDY, 159 GATE_APB4DIV_RDY, 160 GATE_APBDBGDIV_RDY, 161 GATE_TIMG1PRE_RDY, 162 GATE_TIMG2PRE_RDY, 163 GATE_LSMCUDIV_RDY, 164 GATE_RTCCK, 165 GATE_C3, 166 GATE_LPTIM3C3, 167 GATE_LPTIM4C3, 168 GATE_LPTIM5C3, 169 GATE_SPI8C3, 170 GATE_LPUART1C3, 171 GATE_I2C8C3, 172 GATE_ADF1C3, 173 GATE_GPIOZC3, 174 GATE_LPDMAC3, 175 GATE_RTCC3, 176 GATE_I3C4C3, 177 GATE_MCO1, 178 GATE_MCO2, 179 GATE_DDRCP, 180 GATE_DDRCAPB, 181 GATE_DDRPHYCAPB, 182 GATE_DDRPHYC, 183 GATE_DDRCFG, 184 GATE_SYSRAM, 185 GATE_VDERAM, 186 GATE_SRAM1, 187 GATE_SRAM2, 188 GATE_RETRAM, 189 GATE_BKPSRAM, 190 GATE_LPSRAM1, 191 GATE_LPSRAM2, 192 GATE_LPSRAM3, 193 GATE_OSPI1, 194 GATE_OSPI2, 195 GATE_FMC, 196 GATE_DBG, 197 GATE_TRACE, 198 GATE_STM, 199 GATE_ETR, 200 GATE_GPIOA, 201 GATE_GPIOB, 202 GATE_GPIOC, 203 GATE_GPIOD, 204 GATE_GPIOE, 205 GATE_GPIOF, 206 GATE_GPIOG, 207 GATE_GPIOH, 208 GATE_GPIOI, 209 GATE_GPIOJ, 210 GATE_GPIOK, 211 GATE_GPIOZ, 212 GATE_HPDMA1, 213 GATE_HPDMA2, 214 GATE_HPDMA3, 215 GATE_LPDMA, 216 GATE_HSEM, 217 GATE_IPCC1, 218 GATE_IPCC2, 219 GATE_RTC, 220 GATE_SYSCPU1, 221 GATE_BSEC, 222 GATE_IS2M, 223 GATE_HSIMON, 224 GATE_TIM1, 225 GATE_TIM2, 226 GATE_TIM3, 227 GATE_TIM4, 228 GATE_TIM5, 229 GATE_TIM6, 230 GATE_TIM7, 231 GATE_TIM8, 232 GATE_TIM10, 233 GATE_TIM11, 234 GATE_TIM12, 235 GATE_TIM13, 236 GATE_TIM14, 237 GATE_TIM15, 238 GATE_TIM16, 239 GATE_TIM17, 240 GATE_TIM20, 241 GATE_LPTIM1, 242 GATE_LPTIM2, 243 GATE_LPTIM3, 244 GATE_LPTIM4, 245 GATE_LPTIM5, 246 GATE_SPI1, 247 GATE_SPI2, 248 GATE_SPI3, 249 GATE_SPI4, 250 GATE_SPI5, 251 GATE_SPI6, 252 GATE_SPI7, 253 GATE_SPI8, 254 GATE_SPDIFRX, 255 GATE_USART1, 256 GATE_USART2, 257 GATE_USART3, 258 GATE_UART4, 259 GATE_UART5, 260 GATE_USART6, 261 GATE_UART7, 262 GATE_UART8, 263 GATE_UART9, 264 GATE_LPUART1, 265 GATE_I2C1, 266 GATE_I2C2, 267 GATE_I2C3, 268 GATE_I2C4, 269 GATE_I2C5, 270 GATE_I2C6, 271 GATE_I2C7, 272 GATE_I2C8, 273 GATE_SAI1, 274 GATE_SAI2, 275 GATE_SAI3, 276 GATE_SAI4, 277 GATE_MDF1, 278 GATE_ADF1, 279 GATE_FDCAN, 280 GATE_HDP, 281 GATE_ADC12, 282 GATE_ADC3, 283 GATE_ETH1MAC, 284 GATE_ETH1, 285 GATE_ETH1TX, 286 GATE_ETH1RX, 287 GATE_ETH1STP, 288 GATE_ETH2MAC, 289 GATE_ETH2, 290 GATE_ETH2STP, 291 GATE_ETH2TX, 292 GATE_ETH2RX, 293 GATE_USB2, 294 GATE_USB2PHY1, 295 GATE_USB2PHY2, 296 GATE_USB3DR, 297 GATE_USB3PCIEPHY, 298 GATE_PCIE, 299 GATE_USBTC, 300 GATE_ETHSWMAC, 301 GATE_ETHSW, 302 GATE_ETHSWREF, 303 GATE_STGEN, 304 GATE_SDMMC1, 305 GATE_SDMMC2, 306 GATE_SDMMC3, 307 GATE_GPU, 308 GATE_LTDC, 309 GATE_DSI, 310 GATE_LVDS, 311 GATE_CSI, 312 GATE_DCMIPP, 313 GATE_CCI, 314 GATE_VDEC, 315 GATE_VENC, 316 GATE_RNG, 317 GATE_PKA, 318 GATE_SAES, 319 GATE_HASH, 320 GATE_CRYP1, 321 GATE_CRYP2, 322 GATE_IWDG1, 323 GATE_IWDG2, 324 GATE_IWDG3, 325 GATE_IWDG4, 326 GATE_IWDG5, 327 GATE_WWDG1, 328 GATE_WWDG2, 329 GATE_VREF, 330 GATE_DTS, 331 GATE_CRC, 332 GATE_SERC, 333 GATE_OSPIIOM, 334 GATE_GICV2M, 335 GATE_I3C1, 336 GATE_I3C2, 337 GATE_I3C3, 338 GATE_I3C4, 339 GATE_NB 340 }; 341 342 #define GATE_CFG(_id, _offset, _bit_idx, _offset_clr)\ 343 [(_id)] = {\ 344 .offset = (_offset),\ 345 .bit_idx = (_bit_idx),\ 346 .set_clr = (_offset_clr),\ 347 } 348 349 static const struct gate_cfg gates_mp25[GATE_NB] = { 350 GATE_CFG(GATE_LSE, RCC_BDCR, 0, 0), 351 GATE_CFG(GATE_LSE_RDY, RCC_BDCR, 2, 0), 352 GATE_CFG(GATE_LSI, RCC_BDCR, 9, 0), 353 GATE_CFG(GATE_LSI_RDY, RCC_BDCR, 10, 0), 354 GATE_CFG(GATE_RTCCK, RCC_BDCR, 20, 0), 355 GATE_CFG(GATE_MSI, RCC_D3DCR, 0, 0), 356 GATE_CFG(GATE_MSI_RDY, RCC_D3DCR, 2, 0), 357 GATE_CFG(GATE_PLL1, RCC_PLL2CFGR1, 8, 0), 358 GATE_CFG(GATE_PLL1_RDY, RCC_PLL2CFGR1, 24, 0), 359 GATE_CFG(GATE_PLL2, RCC_PLL2CFGR1, 8, 0), 360 GATE_CFG(GATE_PLL2_RDY, RCC_PLL2CFGR1, 24, 0), 361 GATE_CFG(GATE_PLL3, RCC_PLL3CFGR1, 8, 0), 362 GATE_CFG(GATE_PLL3_RDY, RCC_PLL3CFGR1, 24, 0), 363 GATE_CFG(GATE_PLL4, RCC_PLL4CFGR1, 8, 0), 364 GATE_CFG(GATE_PLL4_RDY, RCC_PLL4CFGR1, 24, 0), 365 GATE_CFG(GATE_PLL5, RCC_PLL5CFGR1, 8, 0), 366 GATE_CFG(GATE_PLL5_RDY, RCC_PLL5CFGR1, 24, 0), 367 GATE_CFG(GATE_PLL6, RCC_PLL6CFGR1, 8, 0), 368 GATE_CFG(GATE_PLL6_RDY, RCC_PLL6CFGR1, 24, 0), 369 GATE_CFG(GATE_PLL7, RCC_PLL7CFGR1, 8, 0), 370 GATE_CFG(GATE_PLL7_RDY, RCC_PLL7CFGR1, 24, 0), 371 GATE_CFG(GATE_PLL8, RCC_PLL8CFGR1, 8, 0), 372 GATE_CFG(GATE_PLL8_RDY, RCC_PLL8CFGR1, 24, 0), 373 GATE_CFG(GATE_PLL4_CKREFST, RCC_PLL4CFGR1, 28, 0), 374 GATE_CFG(GATE_PLL5_CKREFST, RCC_PLL5CFGR1, 28, 0), 375 GATE_CFG(GATE_PLL6_CKREFST, RCC_PLL6CFGR1, 28, 0), 376 GATE_CFG(GATE_PLL7_CKREFST, RCC_PLL7CFGR1, 28, 0), 377 GATE_CFG(GATE_PLL8_CKREFST, RCC_PLL8CFGR1, 28, 0), 378 GATE_CFG(GATE_C3, RCC_C3CFGR, 1, 0), 379 GATE_CFG(GATE_LPTIM3C3, RCC_C3CFGR, 16, 0), 380 GATE_CFG(GATE_LPTIM4C3, RCC_C3CFGR, 17, 0), 381 GATE_CFG(GATE_LPTIM5C3, RCC_C3CFGR, 18, 0), 382 GATE_CFG(GATE_SPI8C3, RCC_C3CFGR, 19, 0), 383 GATE_CFG(GATE_LPUART1C3, RCC_C3CFGR, 20, 0), 384 GATE_CFG(GATE_I2C8C3, RCC_C3CFGR, 21, 0), 385 GATE_CFG(GATE_ADF1C3, RCC_C3CFGR, 23, 0), 386 GATE_CFG(GATE_GPIOZC3, RCC_C3CFGR, 24, 0), 387 GATE_CFG(GATE_LPDMAC3, RCC_C3CFGR, 25, 0), 388 GATE_CFG(GATE_RTCC3, RCC_C3CFGR, 26, 0), 389 GATE_CFG(GATE_I3C4C3, RCC_C3CFGR, 27, 0), 390 GATE_CFG(GATE_MCO1, RCC_MCO1CFGR, 8, 0), 391 GATE_CFG(GATE_MCO2, RCC_MCO2CFGR, 8, 0), 392 GATE_CFG(GATE_HSI, RCC_OCENSETR, 0, 1), 393 GATE_CFG(GATE_HSEDIV2, RCC_OCENSETR, 5, 1), 394 GATE_CFG(GATE_HSE, RCC_OCENSETR, 8, 1), 395 GATE_CFG(GATE_HSI_RDY, RCC_OCRDYR, 0, 0), 396 GATE_CFG(GATE_HSE_RDY, RCC_OCRDYR, 8, 0), 397 GATE_CFG(GATE_APB1DIV_RDY, RCC_APB1DIVR, 31, 0), 398 GATE_CFG(GATE_APB2DIV_RDY, RCC_APB2DIVR, 31, 0), 399 GATE_CFG(GATE_APB3DIV_RDY, RCC_APB3DIVR, 31, 0), 400 GATE_CFG(GATE_APB4DIV_RDY, RCC_APB4DIVR, 31, 0), 401 GATE_CFG(GATE_APBDBGDIV_RDY, RCC_APBDBGDIVR, 31, 0), 402 GATE_CFG(GATE_TIMG1PRE_RDY, RCC_TIMG1PRER, 31, 0), 403 GATE_CFG(GATE_TIMG2PRE_RDY, RCC_TIMG2PRER, 31, 0), 404 GATE_CFG(GATE_LSMCUDIV_RDY, RCC_LSMCUDIVR, 31, 0), 405 GATE_CFG(GATE_DDRCP, RCC_DDRCPCFGR, 1, 0), 406 GATE_CFG(GATE_DDRCAPB, RCC_DDRCAPBCFGR, 1, 0), 407 GATE_CFG(GATE_DDRPHYCAPB, RCC_DDRPHYCAPBCFGR, 1, 0), 408 GATE_CFG(GATE_DDRPHYC, RCC_DDRPHYCCFGR, 1, 0), 409 GATE_CFG(GATE_DDRCFG, RCC_DDRCFGR, 1, 0), 410 GATE_CFG(GATE_SYSRAM, RCC_SYSRAMCFGR, 1, 0), 411 GATE_CFG(GATE_VDERAM, RCC_VDERAMCFGR, 1, 0), 412 GATE_CFG(GATE_SRAM1, RCC_SRAM1CFGR, 1, 0), 413 GATE_CFG(GATE_SRAM2, RCC_SRAM2CFGR, 1, 0), 414 GATE_CFG(GATE_RETRAM, RCC_RETRAMCFGR, 1, 0), 415 GATE_CFG(GATE_BKPSRAM, RCC_BKPSRAMCFGR, 1, 0), 416 GATE_CFG(GATE_LPSRAM1, RCC_LPSRAM1CFGR, 1, 0), 417 GATE_CFG(GATE_LPSRAM2, RCC_LPSRAM2CFGR, 1, 0), 418 GATE_CFG(GATE_LPSRAM3, RCC_LPSRAM3CFGR, 1, 0), 419 GATE_CFG(GATE_OSPI1, RCC_OSPI1CFGR, 1, 0), 420 GATE_CFG(GATE_OSPI2, RCC_OSPI2CFGR, 1, 0), 421 GATE_CFG(GATE_FMC, RCC_FMCCFGR, 1, 0), 422 GATE_CFG(GATE_DBG, RCC_DBGCFGR, 8, 0), 423 GATE_CFG(GATE_TRACE, RCC_DBGCFGR, 9, 0), 424 GATE_CFG(GATE_STM, RCC_STMCFGR, 1, 0), 425 GATE_CFG(GATE_ETR, RCC_ETRCFGR, 1, 0), 426 GATE_CFG(GATE_GPIOA, RCC_GPIOACFGR, 1, 0), 427 GATE_CFG(GATE_GPIOB, RCC_GPIOBCFGR, 1, 0), 428 GATE_CFG(GATE_GPIOC, RCC_GPIOCCFGR, 1, 0), 429 GATE_CFG(GATE_GPIOD, RCC_GPIODCFGR, 1, 0), 430 GATE_CFG(GATE_GPIOE, RCC_GPIOECFGR, 1, 0), 431 GATE_CFG(GATE_GPIOF, RCC_GPIOFCFGR, 1, 0), 432 GATE_CFG(GATE_GPIOG, RCC_GPIOGCFGR, 1, 0), 433 GATE_CFG(GATE_GPIOH, RCC_GPIOHCFGR, 1, 0), 434 GATE_CFG(GATE_GPIOI, RCC_GPIOICFGR, 1, 0), 435 GATE_CFG(GATE_GPIOJ, RCC_GPIOJCFGR, 1, 0), 436 GATE_CFG(GATE_GPIOK, RCC_GPIOKCFGR, 1, 0), 437 GATE_CFG(GATE_GPIOZ, RCC_GPIOZCFGR, 1, 0), 438 GATE_CFG(GATE_HPDMA1, RCC_HPDMA1CFGR, 1, 0), 439 GATE_CFG(GATE_HPDMA2, RCC_HPDMA2CFGR, 1, 0), 440 GATE_CFG(GATE_HPDMA3, RCC_HPDMA3CFGR, 1, 0), 441 GATE_CFG(GATE_LPDMA, RCC_LPDMACFGR, 1, 0), 442 GATE_CFG(GATE_HSEM, RCC_HSEMCFGR, 1, 0), 443 GATE_CFG(GATE_IPCC1, RCC_IPCC1CFGR, 1, 0), 444 GATE_CFG(GATE_IPCC2, RCC_IPCC2CFGR, 1, 0), 445 GATE_CFG(GATE_RTC, RCC_RTCCFGR, 1, 0), 446 GATE_CFG(GATE_SYSCPU1, RCC_SYSCPU1CFGR, 1, 0), 447 GATE_CFG(GATE_BSEC, RCC_BSECCFGR, 1, 0), 448 GATE_CFG(GATE_IS2M, RCC_IS2MCFGR, 1, 0), 449 GATE_CFG(GATE_HSIMON, RCC_HSIFMONCR, 15, 0), 450 GATE_CFG(GATE_TIM1, RCC_TIM1CFGR, 1, 0), 451 GATE_CFG(GATE_TIM2, RCC_TIM2CFGR, 1, 0), 452 GATE_CFG(GATE_TIM3, RCC_TIM3CFGR, 1, 0), 453 GATE_CFG(GATE_TIM4, RCC_TIM4CFGR, 1, 0), 454 GATE_CFG(GATE_TIM5, RCC_TIM5CFGR, 1, 0), 455 GATE_CFG(GATE_TIM6, RCC_TIM6CFGR, 1, 0), 456 GATE_CFG(GATE_TIM7, RCC_TIM7CFGR, 1, 0), 457 GATE_CFG(GATE_TIM8, RCC_TIM8CFGR, 1, 0), 458 GATE_CFG(GATE_TIM10, RCC_TIM10CFGR, 1, 0), 459 GATE_CFG(GATE_TIM11, RCC_TIM11CFGR, 1, 0), 460 GATE_CFG(GATE_TIM12, RCC_TIM12CFGR, 1, 0), 461 GATE_CFG(GATE_TIM13, RCC_TIM13CFGR, 1, 0), 462 GATE_CFG(GATE_TIM14, RCC_TIM14CFGR, 1, 0), 463 GATE_CFG(GATE_TIM15, RCC_TIM15CFGR, 1, 0), 464 GATE_CFG(GATE_TIM16, RCC_TIM16CFGR, 1, 0), 465 GATE_CFG(GATE_TIM17, RCC_TIM17CFGR, 1, 0), 466 GATE_CFG(GATE_TIM20, RCC_TIM20CFGR, 1, 0), 467 GATE_CFG(GATE_LPTIM1, RCC_LPTIM1CFGR, 1, 0), 468 GATE_CFG(GATE_LPTIM2, RCC_LPTIM2CFGR, 1, 0), 469 GATE_CFG(GATE_LPTIM3, RCC_LPTIM3CFGR, 1, 0), 470 GATE_CFG(GATE_LPTIM4, RCC_LPTIM4CFGR, 1, 0), 471 GATE_CFG(GATE_LPTIM5, RCC_LPTIM5CFGR, 1, 0), 472 GATE_CFG(GATE_SPI1, RCC_SPI1CFGR, 1, 0), 473 GATE_CFG(GATE_SPI2, RCC_SPI2CFGR, 1, 0), 474 GATE_CFG(GATE_SPI3, RCC_SPI3CFGR, 1, 0), 475 GATE_CFG(GATE_SPI4, RCC_SPI4CFGR, 1, 0), 476 GATE_CFG(GATE_SPI5, RCC_SPI5CFGR, 1, 0), 477 GATE_CFG(GATE_SPI6, RCC_SPI6CFGR, 1, 0), 478 GATE_CFG(GATE_SPI7, RCC_SPI7CFGR, 1, 0), 479 GATE_CFG(GATE_SPI8, RCC_SPI8CFGR, 1, 0), 480 GATE_CFG(GATE_SPDIFRX, RCC_SPDIFRXCFGR, 1, 0), 481 GATE_CFG(GATE_USART1, RCC_USART1CFGR, 1, 0), 482 GATE_CFG(GATE_USART2, RCC_USART2CFGR, 1, 0), 483 GATE_CFG(GATE_USART3, RCC_USART3CFGR, 1, 0), 484 GATE_CFG(GATE_UART4, RCC_UART4CFGR, 1, 0), 485 GATE_CFG(GATE_UART5, RCC_UART5CFGR, 1, 0), 486 GATE_CFG(GATE_USART6, RCC_USART6CFGR, 1, 0), 487 GATE_CFG(GATE_UART7, RCC_UART7CFGR, 1, 0), 488 GATE_CFG(GATE_UART8, RCC_UART8CFGR, 1, 0), 489 GATE_CFG(GATE_UART9, RCC_UART9CFGR, 1, 0), 490 GATE_CFG(GATE_LPUART1, RCC_LPUART1CFGR, 1, 0), 491 GATE_CFG(GATE_I2C1, RCC_I2C1CFGR, 1, 0), 492 GATE_CFG(GATE_I2C2, RCC_I2C2CFGR, 1, 0), 493 GATE_CFG(GATE_I2C3, RCC_I2C3CFGR, 1, 0), 494 GATE_CFG(GATE_I2C4, RCC_I2C4CFGR, 1, 0), 495 GATE_CFG(GATE_I2C5, RCC_I2C5CFGR, 1, 0), 496 GATE_CFG(GATE_I2C6, RCC_I2C6CFGR, 1, 0), 497 GATE_CFG(GATE_I2C7, RCC_I2C7CFGR, 1, 0), 498 GATE_CFG(GATE_I2C8, RCC_I2C8CFGR, 1, 0), 499 GATE_CFG(GATE_SAI1, RCC_SAI1CFGR, 1, 0), 500 GATE_CFG(GATE_SAI2, RCC_SAI2CFGR, 1, 0), 501 GATE_CFG(GATE_SAI3, RCC_SAI3CFGR, 1, 0), 502 GATE_CFG(GATE_SAI4, RCC_SAI4CFGR, 1, 0), 503 GATE_CFG(GATE_MDF1, RCC_MDF1CFGR, 1, 0), 504 GATE_CFG(GATE_ADF1, RCC_ADF1CFGR, 1, 0), 505 GATE_CFG(GATE_FDCAN, RCC_FDCANCFGR, 1, 0), 506 GATE_CFG(GATE_HDP, RCC_HDPCFGR, 1, 0), 507 GATE_CFG(GATE_ADC12, RCC_ADC12CFGR, 1, 0), 508 GATE_CFG(GATE_ADC3, RCC_ADC3CFGR, 1, 0), 509 GATE_CFG(GATE_ETH1MAC, RCC_ETH1CFGR, 1, 0), 510 GATE_CFG(GATE_ETH1STP, RCC_ETH1CFGR, 4, 0), 511 GATE_CFG(GATE_ETH1, RCC_ETH1CFGR, 5, 0), 512 GATE_CFG(GATE_ETH1TX, RCC_ETH1CFGR, 8, 0), 513 GATE_CFG(GATE_ETH1RX, RCC_ETH1CFGR, 10, 0), 514 GATE_CFG(GATE_ETH2MAC, RCC_ETH2CFGR, 1, 0), 515 GATE_CFG(GATE_ETH2STP, RCC_ETH2CFGR, 4, 0), 516 GATE_CFG(GATE_ETH2, RCC_ETH2CFGR, 5, 0), 517 GATE_CFG(GATE_ETH2TX, RCC_ETH2CFGR, 8, 0), 518 GATE_CFG(GATE_ETH2RX, RCC_ETH2CFGR, 10, 0), 519 GATE_CFG(GATE_USB2, RCC_USB2CFGR, 1, 0), 520 GATE_CFG(GATE_USB2PHY1, RCC_USB2PHY1CFGR, 1, 0), 521 GATE_CFG(GATE_USB2PHY2, RCC_USB2PHY2CFGR, 1, 0), 522 GATE_CFG(GATE_USB3DR, RCC_USB3DRCFGR, 1, 0), 523 GATE_CFG(GATE_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 1, 0), 524 GATE_CFG(GATE_PCIE, RCC_PCIECFGR, 1, 0), 525 GATE_CFG(GATE_USBTC, RCC_USBTCCFGR, 1, 0), 526 GATE_CFG(GATE_ETHSWMAC, RCC_ETHSWCFGR, 1, 0), 527 GATE_CFG(GATE_ETHSW, RCC_ETHSWCFGR, 5, 0), 528 GATE_CFG(GATE_ETHSWREF, RCC_ETHSWCFGR, 21, 0), 529 GATE_CFG(GATE_STGEN, RCC_STGENCFGR, 1, 0), 530 GATE_CFG(GATE_SDMMC1, RCC_SDMMC1CFGR, 1, 0), 531 GATE_CFG(GATE_SDMMC2, RCC_SDMMC2CFGR, 1, 0), 532 GATE_CFG(GATE_SDMMC3, RCC_SDMMC3CFGR, 1, 0), 533 GATE_CFG(GATE_GPU, RCC_GPUCFGR, 1, 0), 534 GATE_CFG(GATE_LTDC, RCC_LTDCCFGR, 1, 0), 535 GATE_CFG(GATE_DSI, RCC_DSICFGR, 1, 0), 536 GATE_CFG(GATE_LVDS, RCC_LVDSCFGR, 1, 0), 537 GATE_CFG(GATE_CSI, RCC_CSICFGR, 1, 0), 538 GATE_CFG(GATE_DCMIPP, RCC_DCMIPPCFGR, 1, 0), 539 GATE_CFG(GATE_CCI, RCC_CCICFGR, 1, 0), 540 GATE_CFG(GATE_VDEC, RCC_VDECCFGR, 1, 0), 541 GATE_CFG(GATE_VENC, RCC_VENCCFGR, 1, 0), 542 GATE_CFG(GATE_RNG, RCC_RNGCFGR, 1, 0), 543 GATE_CFG(GATE_PKA, RCC_PKACFGR, 1, 0), 544 GATE_CFG(GATE_SAES, RCC_SAESCFGR, 1, 0), 545 GATE_CFG(GATE_HASH, RCC_HASHCFGR, 1, 0), 546 GATE_CFG(GATE_CRYP1, RCC_CRYP1CFGR, 1, 0), 547 GATE_CFG(GATE_CRYP2, RCC_CRYP2CFGR, 1, 0), 548 GATE_CFG(GATE_IWDG1, RCC_IWDG1CFGR, 1, 0), 549 GATE_CFG(GATE_IWDG2, RCC_IWDG2CFGR, 1, 0), 550 GATE_CFG(GATE_IWDG3, RCC_IWDG3CFGR, 1, 0), 551 GATE_CFG(GATE_IWDG4, RCC_IWDG4CFGR, 1, 0), 552 GATE_CFG(GATE_IWDG5, RCC_IWDG5CFGR, 1, 0), 553 GATE_CFG(GATE_WWDG1, RCC_WWDG1CFGR, 1, 0), 554 GATE_CFG(GATE_WWDG2, RCC_WWDG2CFGR, 1, 0), 555 GATE_CFG(GATE_VREF, RCC_VREFCFGR, 1, 0), 556 GATE_CFG(GATE_DTS, RCC_DTSCFGR, 1, 0), 557 GATE_CFG(GATE_CRC, RCC_CRCCFGR, 1, 0), 558 GATE_CFG(GATE_SERC, RCC_SERCCFGR, 1, 0), 559 GATE_CFG(GATE_OSPIIOM, RCC_OSPIIOMCFGR, 1, 0), 560 GATE_CFG(GATE_GICV2M, RCC_GICV2MCFGR, 1, 0), 561 GATE_CFG(GATE_I3C1, RCC_I3C1CFGR, 1, 0), 562 GATE_CFG(GATE_I3C2, RCC_I3C2CFGR, 1, 0), 563 GATE_CFG(GATE_I3C3, RCC_I3C3CFGR, 1, 0), 564 GATE_CFG(GATE_I3C4, RCC_I3C4CFGR, 1, 0), 565 }; 566 567 /* 568 * MUX CONFIG 569 */ 570 571 #define _MUX_CFG(_id, _offset, _shift, _width, _rdy)\ 572 [(_id)] = {\ 573 .offset = (_offset),\ 574 .shift = (_shift),\ 575 .width = (_width),\ 576 .ready = (_rdy),\ 577 } 578 579 static const struct mux_cfg parent_mp25[MUX_NB] = { 580 _MUX_CFG(MUX_MUXSEL0, RCC_MUXSELCFGR, 0, 2, GATE_PLL4_CKREFST), 581 _MUX_CFG(MUX_MUXSEL1, RCC_MUXSELCFGR, 4, 2, GATE_PLL5_CKREFST), 582 _MUX_CFG(MUX_MUXSEL2, RCC_MUXSELCFGR, 8, 2, GATE_PLL6_CKREFST), 583 _MUX_CFG(MUX_MUXSEL3, RCC_MUXSELCFGR, 12, 2, GATE_PLL7_CKREFST), 584 _MUX_CFG(MUX_MUXSEL4, RCC_MUXSELCFGR, 16, 2, GATE_PLL8_CKREFST), 585 _MUX_CFG(MUX_MUXSEL5, RCC_MUXSELCFGR, 20, 2, MUX_NO_RDY), 586 _MUX_CFG(MUX_MUXSEL6, RCC_MUXSELCFGR, 24, 2, MUX_NO_RDY), 587 _MUX_CFG(MUX_MUXSEL7, RCC_MUXSELCFGR, 28, 2, MUX_NO_RDY), 588 _MUX_CFG(MUX_XBARSEL, RCC_XBAR0CFGR, 0, 4, MUX_NO_RDY), 589 _MUX_CFG(MUX_RTC, RCC_BDCR, 16, 2, MUX_NO_RDY), 590 _MUX_CFG(MUX_D3PER, RCC_D3DCR, 16, 2, MUX_NO_RDY), 591 _MUX_CFG(MUX_MCO1, RCC_MCO1CFGR, 0, 1, MUX_NO_RDY), 592 _MUX_CFG(MUX_MCO2, RCC_MCO2CFGR, 0, 1, MUX_NO_RDY), 593 _MUX_CFG(MUX_ADC12, RCC_ADC12CFGR, 12, 1, MUX_NO_RDY), 594 _MUX_CFG(MUX_ADC3, RCC_ADC3CFGR, 12, 2, MUX_NO_RDY), 595 _MUX_CFG(MUX_USB2PHY1, RCC_USB2PHY1CFGR, 15, 1, MUX_NO_RDY), 596 _MUX_CFG(MUX_USB2PHY2, RCC_USB2PHY2CFGR, 15, 1, MUX_NO_RDY), 597 _MUX_CFG(MUX_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 15, 1, MUX_NO_RDY), 598 _MUX_CFG(MUX_DSIBLANE, RCC_DSICFGR, 12, 1, MUX_NO_RDY), 599 _MUX_CFG(MUX_DSIPHY, RCC_DSICFGR, 15, 1, MUX_NO_RDY), 600 _MUX_CFG(MUX_LVDSPHY, RCC_LVDSCFGR, 15, 1, MUX_NO_RDY), 601 _MUX_CFG(MUX_DTS, RCC_DTSCFGR, 12, 2, MUX_NO_RDY), 602 }; 603 604 /* 605 * DIV CONFIG 606 */ 607 608 static const struct div_table_cfg apb_div_table[] = { 609 { .val = 0, .div = 1 }, 610 { .val = 1, .div = 2 }, 611 { .val = 2, .div = 4 }, 612 { .val = 3, .div = 8 }, 613 { .val = 4, .div = 16 }, 614 { .val = 5, .div = 16 }, 615 { .val = 6, .div = 16 }, 616 { .val = 7, .div = 16 }, 617 /* .div = 0 termination cell */ 618 { } 619 }; 620 621 #define _DIV_CFG(_id, _offset, _shift, _width, _flags, _table, _ready)\ 622 [(_id)] = {\ 623 .offset = (_offset),\ 624 .shift = (_shift),\ 625 .width = (_width),\ 626 .flags = (_flags),\ 627 .table = (_table),\ 628 .ready = (_ready),\ 629 } 630 631 static const struct div_cfg dividers_mp25[DIV_NB] = { 632 _DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, DIV_NO_RDY), 633 _DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 0, apb_div_table, 634 GATE_APB1DIV_RDY), 635 _DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 0, apb_div_table, 636 GATE_APB2DIV_RDY), 637 _DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 0, apb_div_table, 638 GATE_APB3DIV_RDY), 639 _DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 0, apb_div_table, 640 GATE_APB4DIV_RDY), 641 _DIV_CFG(DIV_APBDBG, RCC_APBDBGDIVR, 0, 3, 0, apb_div_table, 642 GATE_APBDBGDIV_RDY), 643 _DIV_CFG(DIV_LSMCU, RCC_LSMCUDIVR, 0, 1, 0, NULL, GATE_LSMCUDIV_RDY), 644 }; 645 646 enum stm32_osc { 647 OSC_HSI, 648 OSC_HSE, 649 OSC_MSI, 650 OSC_LSI, 651 OSC_LSE, 652 NB_OSCILLATOR 653 }; 654 655 struct clk_stm32_bypass { 656 uint16_t offset; 657 uint8_t bit_byp; 658 uint8_t bit_digbyp; 659 }; 660 661 struct clk_stm32_css { 662 uint16_t offset; 663 uint8_t bit_css; 664 }; 665 666 struct clk_stm32_drive { 667 uint16_t offset; 668 uint8_t drv_shift; 669 uint8_t drv_width; 670 uint8_t drv_default; 671 }; 672 673 struct clk_oscillator_data { 674 const char *name; 675 unsigned long frequency; 676 uint16_t gate_id; 677 struct clk_stm32_bypass *bypass; 678 struct clk_stm32_css *css; 679 struct clk_stm32_drive *drive; 680 }; 681 682 #define BYPASS(_offset, _bit_byp, _bit_digbyp) \ 683 (&(struct clk_stm32_bypass){\ 684 .offset = (_offset),\ 685 .bit_byp = (_bit_byp),\ 686 .bit_digbyp = (_bit_digbyp),\ 687 }) 688 689 #define CSS(_offset, _bit_css) \ 690 (&(struct clk_stm32_css){\ 691 .offset = (_offset),\ 692 .bit_css = (_bit_css),\ 693 }) 694 695 #define DRIVE(_offset, _shift, _width, _default) \ 696 (&(struct clk_stm32_drive){\ 697 .offset = (_offset),\ 698 .drv_shift = (_shift),\ 699 .drv_width = (_width),\ 700 .drv_default = (_default),\ 701 }) 702 703 #define OSCILLATOR(idx_osc, _name, _gate_id, _bypass, _css, _drive) \ 704 [(idx_osc)] = (struct clk_oscillator_data){\ 705 .name = (_name),\ 706 .gate_id = (_gate_id),\ 707 .bypass = (_bypass),\ 708 .css = (_css),\ 709 .drive = (_drive),\ 710 } 711 712 static struct clk_oscillator_data stm32mp25_osc_data[NB_OSCILLATOR] = { 713 OSCILLATOR(OSC_HSI, "clk-hsi", GATE_HSI, 714 NULL, NULL, NULL), 715 716 OSCILLATOR(OSC_LSI, "clk-lsi", GATE_LSI, 717 NULL, NULL, NULL), 718 719 OSCILLATOR(OSC_MSI, "clk-msi", GATE_MSI, 720 NULL, NULL, NULL), 721 722 OSCILLATOR(OSC_LSE, "clk-lse", GATE_LSE, 723 BYPASS(RCC_BDCR, RCC_BDCR_LSEBYP_BIT, 724 RCC_BDCR_LSEDIGBYP_BIT), 725 CSS(RCC_BDCR, RCC_BDCR_LSECSSON_BIT), 726 DRIVE(RCC_BDCR, RCC_BDCR_LSEDRV_SHIFT, 727 RCC_BDCR_LSEDRV_WIDTH, LSEDRV_MEDIUM_HIGH)), 728 729 OSCILLATOR(OSC_HSE, "clk-hse", GATE_HSE, 730 BYPASS(RCC_OCENSETR, RCC_OCENSETR_HSEBYP_BIT, 731 RCC_OCENSETR_HSEDIGBYP_BIT), 732 CSS(RCC_OCENSETR, RCC_OCENSETR_HSECSSON_BIT), 733 NULL), 734 }; 735 736 static struct clk_oscillator_data *clk_oscillator_get_data(unsigned int osc_id) 737 { 738 assert(osc_id < ARRAY_SIZE(stm32mp25_osc_data)); 739 740 return &stm32mp25_osc_data[osc_id]; 741 } 742 743 static unsigned long clk_stm32_get_rate_oscillator(unsigned int osc_id) 744 { 745 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 746 struct stm32_clk_platdata *pdata = priv->pdata; 747 struct stm32_osci_dt_cfg *osci = &pdata->osci[osc_id]; 748 749 return osci->freq; 750 } 751 752 static unsigned long clk_stm32_pll_get_oscillator_rate(unsigned int sel) 753 { 754 unsigned int osc[] = { OSC_HSI, OSC_HSE, OSC_MSI }; 755 756 assert(sel < ARRAY_SIZE(osc)); 757 758 return clk_stm32_get_rate_oscillator(osc[sel]); 759 } 760 761 static void clk_oscillator_set_bypass(struct clk_stm32_priv *priv, 762 struct clk_oscillator_data *osc_data, 763 bool digbyp, bool bypass) 764 { 765 struct clk_stm32_bypass *bypass_data = osc_data->bypass; 766 uintptr_t address = 0; 767 768 if (!bypass_data) 769 return; 770 771 address = priv->base + bypass_data->offset; 772 773 if (digbyp) 774 io_setbits32(address, BIT(bypass_data->bit_digbyp)); 775 776 if (bypass || digbyp) 777 io_setbits32(address, BIT(bypass_data->bit_byp)); 778 } 779 780 static void clk_oscillator_set_css(struct clk_stm32_priv *priv, 781 struct clk_oscillator_data *osc_data, 782 bool css) 783 { 784 struct clk_stm32_css *css_data = osc_data->css; 785 786 if (css_data && css) 787 io_setbits32(priv->base + css_data->offset, 788 BIT(css_data->bit_css)); 789 } 790 791 static void clk_oscillator_set_drive(struct clk_stm32_priv *priv, 792 struct clk_oscillator_data *osc_data, 793 uint8_t lsedrv) 794 { 795 struct clk_stm32_drive *drive_data = osc_data->drive; 796 uintptr_t address = 0; 797 uint32_t mask = 0; 798 uint32_t value = 0; 799 800 if (!drive_data) 801 return; 802 803 address = priv->base + drive_data->offset; 804 805 mask = SHIFT_U32(BIT(drive_data->drv_width) - 1, drive_data->drv_shift); 806 807 /* 808 * Warning: not recommended to switch directly from "high drive" 809 * to "medium low drive", and vice-versa. 810 */ 811 value = (io_read32(address) & mask) >> drive_data->drv_shift; 812 813 while (value != lsedrv) { 814 if (value > lsedrv) 815 value--; 816 else 817 value++; 818 819 io_clrsetbits32(address, mask, 820 SHIFT_U32(value, drive_data->drv_shift)); 821 } 822 } 823 824 static void stm32_enable_oscillator_hse(struct clk_stm32_priv *priv, 825 struct stm32_clk_platdata *pdata) 826 { 827 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_HSE); 828 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_HSE]; 829 830 if (!osci->freq) 831 return; 832 833 clk_oscillator_set_bypass(priv, osc_data, osci->digbyp, osci->bypass); 834 835 /* Enable clock and wait ready bit */ 836 if (stm32_gate_rdy_enable(osc_data->gate_id)) 837 panic("timeout to enable hse clock"); 838 839 clk_oscillator_set_css(priv, osc_data, osci->css); 840 } 841 842 static void stm32_enable_oscillator_lse(struct clk_stm32_priv *priv, 843 struct stm32_clk_platdata *pdata) 844 { 845 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_LSE); 846 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE]; 847 848 if (!osci->freq) 849 return; 850 851 if (stm32_gate_is_enabled(osc_data->gate_id)) 852 return; 853 854 clk_oscillator_set_bypass(priv, osc_data, osci->digbyp, osci->bypass); 855 856 clk_oscillator_set_drive(priv, osc_data, osci->drive); 857 858 /* Enable LSE clock, but don't wait ready bit */ 859 stm32_gate_enable(osc_data->gate_id); 860 } 861 862 static void stm32_enable_oscillator_lsi(struct clk_stm32_priv *priv __unused, 863 struct stm32_clk_platdata *pdata) 864 { 865 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_LSI); 866 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSI]; 867 868 if (!osci->freq) 869 return; 870 871 /* Enable clock and wait ready bit */ 872 if (stm32_gate_rdy_enable(osc_data->gate_id)) 873 panic("timeout to enable lsi clock"); 874 } 875 876 static TEE_Result clk_stm32_osc_msi_set_rate(struct clk_stm32_priv *priv, 877 unsigned long rate) 878 { 879 uintptr_t address = priv->base + RCC_BDCR; 880 uint32_t mask = RCC_BDCR_MSIFREQSEL; 881 882 switch (rate) { 883 case RCC_4_MHZ: 884 io_clrbits32_stm32shregs(address, mask); 885 break; 886 case RCC_16_MHZ: 887 io_setbits32_stm32shregs(address, mask); 888 break; 889 default: 890 return TEE_ERROR_GENERIC; 891 } 892 893 return TEE_SUCCESS; 894 } 895 896 static void stm32_enable_oscillator_msi(struct clk_stm32_priv *priv, 897 struct stm32_clk_platdata *pdata) 898 { 899 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_MSI); 900 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_MSI]; 901 902 if (!osci->freq) 903 return; 904 905 if (clk_stm32_osc_msi_set_rate(priv, osci->freq) != TEE_SUCCESS) { 906 EMSG("invalid rate %ld Hz for MSI ! (4000000 or 16000000 only)", 907 osci->freq); 908 panic(); 909 } 910 911 /* Enable clock and wait ready bit */ 912 if (stm32_gate_rdy_enable(osc_data->gate_id)) 913 panic("timeout to enable msi clock"); 914 } 915 916 static void stm32_clk_oscillators_lse_set_css(struct clk_stm32_priv *priv, 917 struct stm32_clk_platdata *pdata) 918 919 { 920 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_LSE); 921 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE]; 922 923 clk_oscillator_set_css(priv, osc_data, osci->css); 924 } 925 926 static int 927 stm32_clk_oscillators_wait_lse_ready(struct clk_stm32_priv *priv __unused, 928 struct stm32_clk_platdata *pdata) 929 { 930 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_LSE); 931 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE]; 932 int ret = 0; 933 934 if (osci->freq && stm32_gate_wait_ready(osc_data->gate_id, true)) 935 ret = -1; 936 937 return ret; 938 } 939 940 static void stm32_clk_oscillators_enable(struct clk_stm32_priv *priv, 941 struct stm32_clk_platdata *pdata) 942 { 943 stm32_enable_oscillator_hse(priv, pdata); 944 stm32_enable_oscillator_lse(priv, pdata); 945 stm32_enable_oscillator_lsi(priv, pdata); 946 stm32_enable_oscillator_msi(priv, pdata); 947 } 948 949 enum stm32_pll_id { 950 PLL1_ID, 951 PLL2_ID, 952 PLL3_ID, 953 PLL4_ID, 954 PLL5_ID, 955 PLL6_ID, 956 PLL7_ID, 957 PLL8_ID, 958 PLL_NB 959 }; 960 961 /* PLL configuration registers offsets from RCC_PLLxCFGR1 */ 962 #define RCC_OFFSET_PLLXCFGR1 0x00 963 #define RCC_OFFSET_PLLXCFGR2 0x04 964 #define RCC_OFFSET_PLLXCFGR3 0x08 965 #define RCC_OFFSET_PLLXCFGR4 0x0C 966 #define RCC_OFFSET_PLLXCFGR5 0x10 967 #define RCC_OFFSET_PLLXCFGR6 0x18 968 #define RCC_OFFSET_PLLXCFGR7 0x1C 969 970 struct stm32_clk_pll { 971 uint16_t gate_id; 972 uint16_t mux_id; 973 uint16_t reg_pllxcfgr1; 974 }; 975 976 #define CLK_PLL_CFG(_idx, _gate_id, _mux_id, _reg)\ 977 [(_idx)] = {\ 978 .gate_id = (_gate_id),\ 979 .mux_id = (_mux_id),\ 980 .reg_pllxcfgr1 = (_reg),\ 981 } 982 983 static const struct stm32_clk_pll stm32mp25_clk_pll[PLL_NB] = { 984 CLK_PLL_CFG(PLL1_ID, GATE_PLL1, MUX_MUXSEL5, 0), 985 CLK_PLL_CFG(PLL2_ID, GATE_PLL2, MUX_MUXSEL6, RCC_PLL2CFGR1), 986 CLK_PLL_CFG(PLL3_ID, GATE_PLL3, MUX_MUXSEL7, RCC_PLL3CFGR1), 987 CLK_PLL_CFG(PLL4_ID, GATE_PLL4, MUX_MUXSEL0, RCC_PLL4CFGR1), 988 CLK_PLL_CFG(PLL5_ID, GATE_PLL5, MUX_MUXSEL1, RCC_PLL5CFGR1), 989 CLK_PLL_CFG(PLL6_ID, GATE_PLL6, MUX_MUXSEL2, RCC_PLL6CFGR1), 990 CLK_PLL_CFG(PLL7_ID, GATE_PLL7, MUX_MUXSEL3, RCC_PLL7CFGR1), 991 CLK_PLL_CFG(PLL8_ID, GATE_PLL8, MUX_MUXSEL4, RCC_PLL8CFGR1), 992 }; 993 994 static const struct stm32_clk_pll *clk_stm32_pll_data(unsigned int idx) 995 { 996 assert(idx < ARRAY_SIZE(stm32mp25_clk_pll)); 997 998 return &stm32mp25_clk_pll[idx]; 999 } 1000 1001 static int stm32_clk_parse_oscillator_fdt(const void *fdt, int node, 1002 const char *name, 1003 struct stm32_osci_dt_cfg *osci) 1004 { 1005 int subnode = 0; 1006 1007 /* default value when oscillator is not found */ 1008 osci->freq = 0; 1009 1010 fdt_for_each_subnode(subnode, fdt, node) { 1011 const char *cchar = NULL; 1012 const fdt32_t *cuint = NULL; 1013 int ret = 0; 1014 1015 cchar = fdt_get_name(fdt, subnode, &ret); 1016 if (!cchar) 1017 return ret; 1018 1019 if (strncmp(cchar, name, (size_t)ret) || 1020 fdt_get_status(fdt, subnode) == DT_STATUS_DISABLED) 1021 continue; 1022 1023 cuint = fdt_getprop(fdt, subnode, "clock-frequency", &ret); 1024 if (!cuint) 1025 return ret; 1026 1027 osci->freq = fdt32_to_cpu(*cuint); 1028 1029 if (fdt_getprop(fdt, subnode, "st,bypass", NULL)) 1030 osci->bypass = true; 1031 1032 if (fdt_getprop(fdt, subnode, "st,digbypass", NULL)) 1033 osci->digbyp = true; 1034 1035 if (fdt_getprop(fdt, subnode, "st,css", NULL)) 1036 osci->css = true; 1037 1038 osci->drive = fdt_read_uint32_default(fdt, subnode, "st,drive", 1039 LSEDRV_MEDIUM_HIGH); 1040 1041 return 0; 1042 } 1043 1044 return 0; 1045 } 1046 1047 static const char *stm32_clk_get_oscillator_name(enum stm32_osc id) 1048 { 1049 if (id < NB_OSCILLATOR) 1050 return stm32mp25_osc_data[id].name; 1051 1052 return NULL; 1053 } 1054 1055 static int stm32_clk_parse_fdt_all_oscillator(const void *fdt, 1056 int node __unused, 1057 struct stm32_clk_platdata *pdata) 1058 { 1059 int fdt_err = 0; 1060 size_t i = 0; 1061 int osc_node = 0; 1062 1063 osc_node = fdt_path_offset(fdt, "/clocks"); 1064 if (osc_node < 0) 1065 return -FDT_ERR_NOTFOUND; 1066 1067 for (i = 0; i < pdata->nosci; i++) { 1068 const char *name = NULL; 1069 1070 name = stm32_clk_get_oscillator_name((enum stm32_osc)i); 1071 if (!name) 1072 continue; 1073 1074 fdt_err = stm32_clk_parse_oscillator_fdt(fdt, osc_node, name, 1075 &pdata->osci[i]); 1076 if (fdt_err < 0) 1077 panic(); 1078 } 1079 1080 return 0; 1081 } 1082 1083 static int clk_stm32_parse_pll_fdt(const void *fdt, int subnode, 1084 struct stm32_pll_dt_cfg *pll) 1085 { 1086 const fdt32_t *cuint = NULL; 1087 int subnode_pll = 0; 1088 int err = 0; 1089 1090 cuint = fdt_getprop(fdt, subnode, "st,pll", NULL); 1091 if (!cuint) 1092 return 0; 1093 1094 subnode_pll = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 1095 if (subnode_pll < 0) 1096 return -FDT_ERR_NOTFOUND; 1097 1098 if (fdt_read_uint32_array(fdt, subnode_pll, "cfg", pll->cfg, 1099 PLLCFG_NB) != 0) 1100 panic("cfg property is mandatory"); 1101 1102 err = fdt_read_uint32_array(fdt, subnode_pll, "csg", pll->csg, 1103 PLLCSG_NB); 1104 1105 pll->csg_enabled = (err == 0); 1106 1107 if (err == -FDT_ERR_NOTFOUND) 1108 err = 0; 1109 1110 if (err != 0) 1111 return err; 1112 1113 pll->enabled = true; 1114 1115 pll->frac = fdt_read_uint32_default(fdt, subnode_pll, "frac", 0); 1116 1117 if (fdt_read_uint32(fdt, subnode_pll, "src", &pll->src)) 1118 panic("src property is mandatory"); 1119 1120 return 0; 1121 } 1122 1123 #define RCC_PLL_NAME_SIZE 20 1124 1125 static int stm32_clk_parse_fdt_all_pll(const void *fdt, int node, 1126 struct stm32_clk_platdata *pdata) 1127 { 1128 unsigned int i = 0; 1129 1130 for (i = 0; i < pdata->npll; i++) { 1131 struct stm32_pll_dt_cfg *pll = pdata->pll + i; 1132 char name[RCC_PLL_NAME_SIZE] = { }; 1133 int subnode = 0; 1134 1135 snprintf(name, sizeof(name), "st,pll-%u", i + 1); 1136 1137 subnode = fdt_subnode_offset(fdt, node, name); 1138 if (subnode < 0) 1139 continue; 1140 1141 if (clk_stm32_parse_pll_fdt(fdt, subnode, pll)) 1142 panic(); 1143 } 1144 1145 return 0; 1146 } 1147 1148 static int stm32_clk_parse_fdt_opp(const void *fdt, int node, 1149 const char *opp_name, 1150 struct stm32_clk_opp_cfg *opp_cfg) 1151 { 1152 int subnode = 0; 1153 int nb_opp = 0; 1154 int ret = 0; 1155 1156 node = fdt_subnode_offset(fdt, node, opp_name); 1157 if (node == -FDT_ERR_NOTFOUND) 1158 return 0; 1159 1160 if (node < 0) 1161 return node; 1162 1163 fdt_for_each_subnode(subnode, fdt, node) { 1164 assert(nb_opp <= MAX_OPP); 1165 1166 if (fdt_read_uint32(fdt, subnode, "hz", &opp_cfg->frq)) 1167 panic("hz property is mandatory"); 1168 1169 if (fdt_read_uint32(fdt, subnode, "st,clksrc", &opp_cfg->src)) 1170 panic("st,clksrc property is mandatory"); 1171 1172 ret = clk_stm32_parse_pll_fdt(fdt, subnode, &opp_cfg->pll_cfg); 1173 if (ret < 0) 1174 return ret; 1175 1176 opp_cfg++; 1177 nb_opp++; 1178 } 1179 1180 return 0; 1181 } 1182 1183 static int stm32_clk_parse_fdt_all_opp(const void *fdt, int node, 1184 struct stm32_clk_platdata *pdata) 1185 { 1186 struct stm32_clk_opp_dt_cfg *opp = pdata->opp; 1187 1188 node = fdt_subnode_offset(fdt, node, "st,clk_opp"); 1189 if (node == -FDT_ERR_NOTFOUND) 1190 return 0; 1191 1192 if (node < 0) 1193 return node; 1194 1195 return stm32_clk_parse_fdt_opp(fdt, node, "st,ck_cpu1", opp->cpu1_opp); 1196 } 1197 1198 static int stm32_clk_parse_fdt(const void *fdt, int node, 1199 struct stm32_clk_platdata *pdata) 1200 { 1201 int err = 0; 1202 1203 err = stm32_clk_parse_fdt_all_oscillator(fdt, node, pdata); 1204 if (err != 0) 1205 return err; 1206 1207 err = stm32_clk_parse_fdt_all_pll(fdt, node, pdata); 1208 if (err != 0) 1209 return err; 1210 1211 err = stm32_clk_parse_fdt_all_opp(fdt, node, pdata); 1212 if (err != 0) 1213 return err; 1214 1215 err = clk_stm32_parse_fdt_by_name(fdt, node, "st,busclk", 1216 pdata->busclk, 1217 &pdata->nbusclk); 1218 if (err != 0) 1219 return err; 1220 1221 err = clk_stm32_parse_fdt_by_name(fdt, node, "st,flexgen", 1222 pdata->flexgen, 1223 &pdata->nflexgen); 1224 if (err != 0) 1225 return err; 1226 1227 err = clk_stm32_parse_fdt_by_name(fdt, node, "st,kerclk", 1228 pdata->kernelclk, 1229 &pdata->nkernelclk); 1230 if (err != 0) 1231 return err; 1232 1233 pdata->c1msrd = fdt_read_uint32_default(fdt, node, "st,c1msrd", 0); 1234 1235 if (fdt_getprop(fdt, node, "st,safe_rst", NULL)) 1236 pdata->safe_rst = true; 1237 1238 pdata->rcc_base = stm32_rcc_base(); 1239 1240 return 0; 1241 } 1242 1243 static void stm32mp2_a35_ss_on_hsi(void) 1244 { 1245 uint64_t timeout = 0; 1246 1247 /* Nothing to do if clock source is already set on bypass clock */ 1248 if (stm32mp_syscfg_read(A35SS_SSC_CHGCLKREQ) & 1249 A35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK) 1250 return; 1251 1252 stm32mp_syscfg_write(A35SS_SSC_CHGCLKREQ, 1253 A35SS_SSC_CHGCLKREQ_ARM_CHGCLKREQ_EN, 1254 A35SS_SSC_CHGCLKREQ_ARM_CHGCLKREQ_MASK); 1255 1256 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1257 while (!timeout_elapsed(timeout)) 1258 if (stm32mp_syscfg_read(A35SS_SSC_CHGCLKREQ) & 1259 A35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK) 1260 break; 1261 1262 if (!(stm32mp_syscfg_read(A35SS_SSC_CHGCLKREQ) & 1263 A35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK)) 1264 panic("Cannot switch A35 to bypass clock"); 1265 1266 stm32mp_syscfg_write(A35SS_SSC_PLL_EN, 1267 0, 1268 A35SS_SSC_PLL_ENABLE_NRESET_SWPLL_FF_MASK); 1269 } 1270 1271 static void stm32mp2_clk_xbar_on_hsi(struct clk_stm32_priv *priv) 1272 { 1273 uintptr_t xbar0cfgr = priv->base + RCC_XBAR0CFGR; 1274 uint32_t i = 0; 1275 1276 for (i = 0; i < XBAR_ROOT_CHANNEL_NB; i++) 1277 io_clrsetbits32(xbar0cfgr + (0x4 * i), 1278 RCC_XBAR0CFGR_XBAR0SEL_MASK, XBAR_SRC_HSI); 1279 } 1280 1281 static int stm32mp2_a35_pll1_start(void) 1282 { 1283 uint64_t timeout = 0; 1284 1285 stm32mp_syscfg_write(A35SS_SSC_PLL_EN, 1286 A35SS_SSC_PLL_ENABLE_PD_EN, 1287 A35SS_SSC_PLL_ENABLE_PD_EN); 1288 1289 /* Wait PLL lock */ 1290 timeout = timeout_init_us(PLLRDY_TIMEOUT); 1291 while (!timeout_elapsed(timeout)) 1292 if (stm32mp_syscfg_read(A35SS_SSC_PLL_EN) & 1293 A35SS_SSC_PLL_ENABLE_LOCKP_MASK) 1294 break; 1295 1296 if (!(stm32mp_syscfg_read(A35SS_SSC_PLL_EN) & 1297 A35SS_SSC_PLL_ENABLE_LOCKP_MASK)) { 1298 EMSG("PLL1 not locked"); 1299 return -1; 1300 } 1301 1302 /* De-assert reset on PLL output clock path */ 1303 stm32mp_syscfg_write(A35SS_SSC_PLL_EN, 1304 A35SS_SSC_PLL_ENABLE_NRESET_SWPLL_FF_EN, 1305 A35SS_SSC_PLL_ENABLE_NRESET_SWPLL_FF_MASK); 1306 1307 /* Switch CPU clock to PLL clock */ 1308 stm32mp_syscfg_write(A35SS_SSC_CHGCLKREQ, 1309 0, 1310 A35SS_SSC_CHGCLKREQ_ARM_CHGCLKREQ_MASK); 1311 1312 /* Wait for clock change acknowledge */ 1313 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1314 while (!timeout_elapsed(timeout)) 1315 if (!(stm32mp_syscfg_read(A35SS_SSC_CHGCLKREQ) & 1316 A35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK)) 1317 break; 1318 1319 if (stm32mp_syscfg_read(A35SS_SSC_CHGCLKREQ) & 1320 A35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK) { 1321 EMSG("A35 switch to PLL1 failed"); 1322 return -1; 1323 } 1324 1325 return 0; 1326 } 1327 1328 static void stm32mp2_a35_pll1_config(uint32_t fbdiv, uint32_t refdiv, 1329 uint32_t postdiv1, uint32_t postdiv2) 1330 { 1331 stm32mp_syscfg_write(A35SS_SSC_PLL_FREQ1, 1332 SHIFT_U32(refdiv, 1333 A35SS_SSC_PLL_FREQ1_REFDIV_SHIFT) | 1334 SHIFT_U32(fbdiv, A35SS_SSC_PLL_FREQ1_FBDIV_SHIFT), 1335 A35SS_SSC_PLL_FREQ1_MASK); 1336 1337 stm32mp_syscfg_write(A35SS_SSC_PLL_FREQ2, 1338 SHIFT_U32(postdiv1, 1339 A35SS_SSC_PLL_FREQ2_POSTDIV1_SHIFT) | 1340 SHIFT_U32(postdiv2, 1341 A35SS_SSC_PLL_FREQ2_POSTDIV2_SHIFT), 1342 A35SS_SSC_PLL_FREQ2_MASK); 1343 } 1344 1345 static void clk_stm32_pll_config_output(struct clk_stm32_priv *priv, 1346 const struct stm32_clk_pll *pll, 1347 uint32_t pllsrc, 1348 uint32_t *pllcfg, 1349 uint32_t fracv) 1350 { 1351 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 1352 uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2; 1353 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3; 1354 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4; 1355 uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6; 1356 uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7; 1357 int sel = (pllsrc & MUX_SEL_MASK) >> MUX_SEL_SHIFT; 1358 unsigned long refclk = clk_stm32_pll_get_oscillator_rate(sel); 1359 1360 if (fracv == 0) { 1361 /* PLL in integer mode */ 1362 1363 /* 1364 * No need to check max clock, as oscillator reference clocks 1365 * will always be less than 1.2GHz 1366 */ 1367 if (refclk < PLL_REFCLK_MIN) 1368 panic(); 1369 1370 io_clrbits32(pllxcfgr3, RCC_PLLxCFGR3_FRACIN_MASK); 1371 io_clrbits32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN); 1372 io_clrbits32(pllxcfgr3, RCC_PLLxCFGR3_DACEN); 1373 io_setbits32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS); 1374 io_setbits32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST); 1375 } else { 1376 /* PLL in frac mode */ 1377 1378 /* 1379 * No need to check max clock, as oscillator reference clocks 1380 * will always be less than 1.2GHz 1381 */ 1382 if (refclk < PLL_FRAC_REFCLK_MIN) 1383 panic(); 1384 1385 io_clrsetbits32(pllxcfgr3, RCC_PLLxCFGR3_FRACIN_MASK, 1386 fracv & RCC_PLLxCFGR3_FRACIN_MASK); 1387 io_setbits32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS); 1388 io_setbits32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN); 1389 } 1390 1391 assert(pllcfg[REFDIV]); 1392 1393 io_clrsetbits32(pllxcfgr2, RCC_PLLxCFGR2_FBDIV_MASK, 1394 SHIFT_U32(pllcfg[FBDIV], RCC_PLLxCFGR2_FBDIV_SHIFT) & 1395 RCC_PLLxCFGR2_FBDIV_MASK); 1396 io_clrsetbits32(pllxcfgr2, RCC_PLLxCFGR2_FREFDIV_MASK, 1397 pllcfg[REFDIV] & RCC_PLLxCFGR2_FREFDIV_MASK); 1398 io_clrsetbits32(pllxcfgr6, RCC_PLLxCFGR6_POSTDIV1_MASK, 1399 pllcfg[POSTDIV1] & RCC_PLLxCFGR6_POSTDIV1_MASK); 1400 io_clrsetbits32(pllxcfgr7, RCC_PLLxCFGR7_POSTDIV2_MASK, 1401 pllcfg[POSTDIV2] & RCC_PLLxCFGR7_POSTDIV2_MASK); 1402 1403 if (pllcfg[POSTDIV1] == 0 || pllcfg[POSTDIV2] == 0) { 1404 /* Bypass mode */ 1405 io_setbits32(pllxcfgr4, RCC_PLLxCFGR4_BYPASS); 1406 io_clrbits32(pllxcfgr4, RCC_PLLxCFGR4_FOUTPOSTDIVEN); 1407 } else { 1408 io_clrbits32(pllxcfgr4, RCC_PLLxCFGR4_BYPASS); 1409 io_setbits32(pllxcfgr4, RCC_PLLxCFGR4_FOUTPOSTDIVEN); 1410 } 1411 } 1412 1413 static void clk_stm32_pll_config_csg(struct clk_stm32_priv *priv, 1414 const struct stm32_clk_pll *pll, 1415 uint32_t *csg) 1416 { 1417 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 1418 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3; 1419 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4; 1420 uintptr_t pllxcfgr5 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR5; 1421 1422 io_clrsetbits32(pllxcfgr5, RCC_PLLxCFGR5_DIVVAL_MASK, 1423 csg[DIVVAL] & RCC_PLLxCFGR5_DIVVAL_MASK); 1424 io_clrsetbits32(pllxcfgr5, RCC_PLLxCFGR5_SPREAD_MASK, 1425 SHIFT_U32(csg[SPREAD], RCC_PLLxCFGR5_SPREAD_SHIFT) & 1426 RCC_PLLxCFGR5_SPREAD_MASK); 1427 1428 if (csg[DOWNSPREAD] != 0) 1429 io_setbits32(pllxcfgr3, RCC_PLLxCFGR3_DOWNSPREAD); 1430 else 1431 io_clrbits32(pllxcfgr3, RCC_PLLxCFGR3_DOWNSPREAD); 1432 1433 io_clrbits32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS); 1434 1435 io_clrbits32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN); 1436 udelay(1); 1437 1438 io_setbits32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN); 1439 io_setbits32(pllxcfgr3, RCC_PLLxCFGR3_DACEN); 1440 } 1441 1442 static struct stm32_pll_dt_cfg *clk_stm32_pll_get_pdata(unsigned int pll_idx) 1443 { 1444 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 1445 struct stm32_clk_platdata *pdata = priv->pdata; 1446 1447 assert(pll_idx < pdata->npll); 1448 1449 return &pdata->pll[pll_idx]; 1450 } 1451 1452 static int clk_stm32_pll_set_mux(struct clk_stm32_priv *priv __unused, 1453 uint32_t src) 1454 { 1455 int mux = (src & MUX_ID_MASK) >> MUX_ID_SHIFT; 1456 int sel = (src & MUX_SEL_MASK) >> MUX_SEL_SHIFT; 1457 1458 if (stm32_mux_set_parent(mux, sel)) 1459 return -1; 1460 else 1461 return 0; 1462 1463 } 1464 1465 static void clk_stm32_pll1_init(struct clk_stm32_priv *priv, 1466 int pll_idx __unused, 1467 struct stm32_pll_dt_cfg *pll_conf) 1468 { 1469 int sel = (pll_conf->src & MUX_SEL_MASK) >> MUX_SEL_SHIFT; 1470 unsigned long refclk = 0; 1471 1472 /* 1473 * TODO: check if pll has already good parameters or if we could make 1474 * a configuration on the fly. 1475 */ 1476 1477 stm32mp2_a35_ss_on_hsi(); 1478 1479 if (clk_stm32_pll_set_mux(priv, pll_conf->src)) 1480 panic(); 1481 1482 refclk = clk_stm32_pll_get_oscillator_rate(sel); 1483 1484 /* 1485 * No need to check max clock, as oscillator reference clocks will 1486 * always be less than 1.2GHz 1487 */ 1488 if (refclk < PLL_REFCLK_MIN) 1489 panic(); 1490 1491 stm32mp2_a35_pll1_config(pll_conf->cfg[FBDIV], 1492 pll_conf->cfg[REFDIV], 1493 pll_conf->cfg[POSTDIV1], 1494 pll_conf->cfg[POSTDIV2]); 1495 1496 if (stm32mp2_a35_pll1_start()) 1497 panic(); 1498 } 1499 1500 static void clk_stm32_pll_init(struct clk_stm32_priv *priv, int pll_idx, 1501 struct stm32_pll_dt_cfg *pll_conf) 1502 { 1503 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_idx); 1504 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 1505 bool spread_spectrum = false; 1506 1507 /* 1508 * TODO: check if pll has already good parameters or if we could make 1509 * a configuration on the fly. 1510 */ 1511 1512 if (stm32_gate_rdy_disable(pll->gate_id)) 1513 panic(); 1514 1515 if (clk_stm32_pll_set_mux(priv, pll_conf->src)) 1516 panic(); 1517 1518 clk_stm32_pll_config_output(priv, pll, pll_conf->src, 1519 pll_conf->cfg, pll_conf->frac); 1520 1521 if (pll_conf->csg_enabled) { 1522 clk_stm32_pll_config_csg(priv, pll, pll_conf->csg); 1523 spread_spectrum = true; 1524 } 1525 1526 if (stm32_gate_rdy_enable(pll->gate_id)) 1527 panic(); 1528 1529 if (spread_spectrum) 1530 io_clrbits32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST); 1531 } 1532 1533 static int stm32_clk_pll_configure(struct clk_stm32_priv *priv) 1534 { 1535 struct stm32_pll_dt_cfg *pll_conf = NULL; 1536 size_t i = 0; 1537 1538 for (i = 0; i < PLL_NB; i++) { 1539 pll_conf = clk_stm32_pll_get_pdata(i); 1540 1541 if (pll_conf->enabled) { 1542 /* Skip the pll3 (need GPU regulator to configure) */ 1543 if (i == PLL3_ID) 1544 continue; 1545 1546 /* Skip the pll2 (reserved to DDR) */ 1547 if (i == PLL2_ID) 1548 continue; 1549 1550 if (i == PLL1_ID) 1551 clk_stm32_pll1_init(priv, i, pll_conf); 1552 else 1553 clk_stm32_pll_init(priv, i, pll_conf); 1554 } 1555 } 1556 1557 return 0; 1558 } 1559 1560 #define __WORD_BIT 32 1561 1562 static int wait_predivsr(uint16_t channel) 1563 { 1564 uintptr_t rcc_base = stm32_rcc_base(); 1565 uintptr_t previvsr = 0; 1566 uint32_t channel_bit = 0; 1567 uint32_t value = 0; 1568 1569 if (channel < __WORD_BIT) { 1570 previvsr = rcc_base + RCC_PREDIVSR1; 1571 channel_bit = BIT(channel); 1572 } else { 1573 previvsr = rcc_base + RCC_PREDIVSR2; 1574 channel_bit = BIT(channel - __WORD_BIT); 1575 } 1576 1577 if (IO_READ32_POLL_TIMEOUT(previvsr, value, !(value & channel_bit), 0, 1578 CLKDIV_TIMEOUT)) { 1579 EMSG("Pre divider status: %#"PRIx32, io_read32(previvsr)); 1580 return -1; 1581 } 1582 1583 return 0; 1584 } 1585 1586 static int wait_findivsr(uint16_t channel) 1587 { 1588 uintptr_t rcc_base = stm32_rcc_base(); 1589 uintptr_t finvivsr = 0; 1590 uint32_t channel_bit = 0; 1591 uint32_t value = 0; 1592 1593 if (channel < __WORD_BIT) { 1594 finvivsr = rcc_base + RCC_FINDIVSR1; 1595 channel_bit = BIT(channel); 1596 } else { 1597 finvivsr = rcc_base + RCC_FINDIVSR2; 1598 channel_bit = BIT(channel - __WORD_BIT); 1599 } 1600 1601 if (IO_READ32_POLL_TIMEOUT(finvivsr, value, !(value & channel_bit), 0, 1602 CLKDIV_TIMEOUT)) { 1603 EMSG("Final divider status: %#"PRIx32, io_read32(finvivsr)); 1604 return -1; 1605 } 1606 1607 return 0; 1608 } 1609 1610 static int wait_xbar_sts(uint16_t channel) 1611 { 1612 uintptr_t rcc_base = stm32_rcc_base(); 1613 uintptr_t xbar_cfgr = rcc_base + RCC_XBAR0CFGR + (0x4 * channel); 1614 uint32_t value = 0; 1615 1616 if (IO_READ32_POLL_TIMEOUT(xbar_cfgr, value, 1617 !(value & RCC_XBAR0CFGR_XBAR0STS), 0, 1618 CLKDIV_TIMEOUT)) { 1619 EMSG("XBAR%"PRIu16"CFGR: %#"PRIx32, channel, 1620 io_read32(xbar_cfgr)); 1621 return -1; 1622 } 1623 1624 return 0; 1625 } 1626 1627 static void flexclkgen_config_channel(uint16_t channel, unsigned int clk_src, 1628 unsigned int prediv, unsigned int findiv) 1629 { 1630 uintptr_t rcc_base = stm32_rcc_base(); 1631 1632 if (wait_predivsr(channel) != 0) 1633 panic(); 1634 1635 io_clrsetbits32(rcc_base + RCC_PREDIV0CFGR + (0x4 * channel), 1636 RCC_PREDIV0CFGR_PREDIV0_MASK, prediv); 1637 1638 if (wait_predivsr(channel) != 0) 1639 panic(); 1640 1641 if (wait_findivsr(channel) != 0) 1642 panic(); 1643 1644 io_clrsetbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel), 1645 RCC_FINDIV0CFGR_FINDIV0_MASK, 1646 findiv); 1647 1648 if (wait_findivsr(channel) != 0) 1649 panic(); 1650 1651 if (wait_xbar_sts(channel) != 0) 1652 panic(); 1653 1654 io_clrsetbits32(rcc_base + RCC_XBAR0CFGR + (0x4 * channel), 1655 RCC_XBAR0CFGR_XBAR0SEL_MASK, 1656 clk_src); 1657 1658 io_setbits32(rcc_base + RCC_XBAR0CFGR + (0x4 * channel), 1659 RCC_XBAR0CFGR_XBAR0EN); 1660 1661 if (wait_xbar_sts(channel) != 0) 1662 panic(); 1663 } 1664 1665 static int stm32mp2_clk_flexgen_configure(struct clk_stm32_priv *priv) 1666 { 1667 struct stm32_clk_platdata *pdata = priv->pdata; 1668 uint32_t i = 0; 1669 1670 for (i = 0; i < pdata->nflexgen; i++) { 1671 uint32_t val = pdata->flexgen[i]; 1672 uint32_t cmd = 0; 1673 uint32_t cmd_data = 0; 1674 unsigned int channel = 0; 1675 unsigned int clk_src = 0; 1676 unsigned int pdiv = 0; 1677 unsigned int fdiv = 0; 1678 1679 cmd = (val & CMD_MASK) >> CMD_SHIFT; 1680 cmd_data = val & ~CMD_MASK; 1681 1682 if (cmd != CMD_FLEXGEN) 1683 continue; 1684 1685 channel = (cmd_data & FLEX_ID_MASK) >> FLEX_ID_SHIFT; 1686 1687 /* 1688 * Skip ck_ker_stgen configuration, will be done by 1689 * stgen driver. 1690 */ 1691 if (channel == FLEX_STGEN) 1692 continue; 1693 1694 clk_src = (cmd_data & FLEX_SEL_MASK) >> FLEX_SEL_SHIFT; 1695 pdiv = (cmd_data & FLEX_PDIV_MASK) >> FLEX_PDIV_SHIFT; 1696 fdiv = (cmd_data & FLEX_FDIV_MASK) >> FLEX_FDIV_SHIFT; 1697 1698 flexclkgen_config_channel(channel, clk_src, pdiv, fdiv); 1699 } 1700 1701 return 0; 1702 } 1703 1704 static int stm32_clk_configure_div(struct clk_stm32_priv *priv __unused, 1705 uint32_t data) 1706 { 1707 uint32_t div_id = 0; 1708 uint32_t div_n = 0; 1709 1710 div_id = (data & DIV_ID_MASK) >> DIV_ID_SHIFT; 1711 div_n = (data & DIV_DIVN_MASK) >> DIV_DIVN_SHIFT; 1712 1713 return stm32_div_set_value(div_id, div_n); 1714 } 1715 1716 static int stm32_clk_configure_mux(struct clk_stm32_priv *priv __unused, 1717 uint32_t data) 1718 { 1719 int mux = (data & MUX_ID_MASK) >> MUX_ID_SHIFT; 1720 int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT; 1721 1722 if (stm32_mux_set_parent(mux, sel)) 1723 return -1; 1724 else 1725 return 0; 1726 } 1727 1728 static int stm32_clk_configure_by_addr_val(struct clk_stm32_priv *priv, 1729 uint32_t data) 1730 { 1731 uint32_t addr = data >> CLK_ADDR_SHIFT; 1732 uint32_t val = data & CLK_ADDR_VAL_MASK; 1733 1734 io_setbits32(priv->base + addr, val); 1735 1736 return 0; 1737 } 1738 1739 static void stm32_clk_configure_obs(struct clk_stm32_priv *priv, 1740 uint32_t data) 1741 { 1742 uint32_t id = (data & OBS_ID_MASK) >> OBS_ID_SHIFT; 1743 uint32_t status = (data & OBS_STATUS_MASK) >> OBS_STATUS_SHIFT; 1744 uint32_t int_ext = (data & OBS_INTEXT_MASK) >> OBS_INTEXT_SHIFT; 1745 uint32_t div = (data & OBS_DIV_MASK) >> OBS_DIV_SHIFT; 1746 uint32_t inv = (data & OBS_INV_MASK) >> OBS_INV_SHIFT; 1747 uint32_t sel = (data & OBS_SEL_MASK) >> OBS_SEL_SHIFT; 1748 uint32_t reg = 0; 1749 uint32_t val = 0; 1750 1751 if (!id) 1752 reg = RCC_FCALCOBS0CFGR; 1753 else 1754 reg = RCC_FCALCOBS1CFGR; 1755 1756 if (status) 1757 val |= RCC_FCALCOBS0CFGR_CKOBSEN; 1758 1759 if (int_ext == OBS_EXT) { 1760 val |= RCC_FCALCOBS0CFGR_CKOBSEXTSEL; 1761 val |= SHIFT_U32(sel, RCC_FCALCOBS0CFGR_CKEXTSEL_SHIFT); 1762 } else { 1763 val |= SHIFT_U32(sel, RCC_FCALCOBS0CFGR_CKINTSEL_SHIFT); 1764 } 1765 1766 if (inv) 1767 val |= RCC_FCALCOBS0CFGR_CKOBSINV; 1768 1769 val |= SHIFT_U32(div, RCC_FCALCOBS0CFGR_CKOBSDIV_SHIFT); 1770 1771 io_write32(priv->base + reg, val); 1772 } 1773 1774 static int stm32_clk_configure(struct clk_stm32_priv *priv, uint32_t val) 1775 { 1776 uint32_t cmd_data = 0; 1777 uint32_t cmd = 0; 1778 int ret = 0; 1779 1780 if (val & CMD_ADDR_BIT) { 1781 cmd_data = val & ~CMD_ADDR_BIT; 1782 1783 return stm32_clk_configure_by_addr_val(priv, cmd_data); 1784 } 1785 1786 cmd = (val & CMD_MASK) >> CMD_SHIFT; 1787 cmd_data = val & ~CMD_MASK; 1788 1789 switch (cmd) { 1790 case CMD_DIV: 1791 ret = stm32_clk_configure_div(priv, cmd_data); 1792 break; 1793 1794 case CMD_MUX: 1795 ret = stm32_clk_configure_mux(priv, cmd_data); 1796 break; 1797 1798 case CMD_OBS: 1799 stm32_clk_configure_obs(priv, cmd_data); 1800 break; 1801 1802 default: 1803 EMSG("cmd unknown ! : %#"PRIx32, val); 1804 ret = -1; 1805 } 1806 1807 return ret; 1808 } 1809 1810 static int stm32_clk_bus_configure(struct clk_stm32_priv *priv) 1811 { 1812 struct stm32_clk_platdata *pdata = priv->pdata; 1813 uint32_t i = 0; 1814 1815 for (i = 0; i < pdata->nbusclk; i++) { 1816 int ret = 0; 1817 1818 ret = stm32_clk_configure(priv, pdata->busclk[i]); 1819 if (ret != 0) 1820 return ret; 1821 } 1822 1823 return 0; 1824 } 1825 1826 static int stm32_clk_kernel_configure(struct clk_stm32_priv *priv) 1827 { 1828 struct stm32_clk_platdata *pdata = priv->pdata; 1829 uint32_t i = 0; 1830 1831 for (i = 0; i < pdata->nkernelclk; i++) { 1832 int ret = 0; 1833 1834 ret = stm32_clk_configure(priv, pdata->kernelclk[i]); 1835 if (ret != 0) 1836 return ret; 1837 } 1838 1839 return 0; 1840 } 1841 1842 static void stm32mp2_init_clock_tree(struct clk_stm32_priv *priv, 1843 struct stm32_clk_platdata *pdata) 1844 { 1845 stm32_clk_oscillators_enable(priv, pdata); 1846 1847 /* Come back to HSI for flexgen */ 1848 stm32mp2_clk_xbar_on_hsi(priv); 1849 1850 if (stm32_clk_pll_configure(priv)) 1851 panic("Cannot configure plls"); 1852 1853 /* Wait LSE ready before to use it */ 1854 if (stm32_clk_oscillators_wait_lse_ready(priv, pdata)) 1855 panic("Timeout: to enable LSE"); 1856 1857 if (stm32mp2_clk_flexgen_configure(priv)) 1858 panic("Cannot configure flexgen"); 1859 1860 if (stm32_clk_bus_configure(priv)) 1861 panic("Cannot config bus clocks"); 1862 1863 if (stm32_clk_kernel_configure(priv)) 1864 panic("Cannot configure kernel clocks"); 1865 1866 /* Configure LSE css after RTC source configuration */ 1867 stm32_clk_oscillators_lse_set_css(priv, pdata); 1868 } 1869 1870 static TEE_Result clk_stm32_osc_enable(struct clk *clk) 1871 { 1872 return clk_stm32_gate_ready_ops.enable(clk); 1873 } 1874 1875 static void clk_stm32_osc_disable(struct clk *clk) 1876 { 1877 clk_stm32_gate_ready_ops.disable(clk); 1878 } 1879 1880 static const struct clk_ops clk_stm32_osc_ops = { 1881 .enable = clk_stm32_osc_enable, 1882 .disable = clk_stm32_osc_disable, 1883 }; 1884 1885 static unsigned long clk_stm32_msi_get_rate(struct clk *clk __unused, 1886 unsigned long prate __unused) 1887 { 1888 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 1889 uintptr_t address = priv->base + RCC_BDCR; 1890 1891 if ((io_read32(address) & RCC_BDCR_MSIFREQSEL)) 1892 return RCC_16_MHZ; 1893 1894 return RCC_4_MHZ; 1895 } 1896 1897 static TEE_Result clk_stm32_msi_set_rate(struct clk *clk __unused, 1898 unsigned long rate, 1899 unsigned long prate __unused) 1900 { 1901 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 1902 1903 return clk_stm32_osc_msi_set_rate(priv, rate); 1904 } 1905 1906 static const struct clk_ops clk_stm32_oscillator_msi_ops = { 1907 .enable = clk_stm32_osc_enable, 1908 .disable = clk_stm32_osc_disable, 1909 .get_rate = clk_stm32_msi_get_rate, 1910 .set_rate = clk_stm32_msi_set_rate, 1911 }; 1912 1913 static TEE_Result clk_stm32_hse_div_set_rate(struct clk *clk, 1914 unsigned long rate, 1915 unsigned long parent_rate) 1916 { 1917 return clk_stm32_divider_set_rate(clk, rate, parent_rate); 1918 } 1919 1920 static const struct clk_ops clk_stm32_hse_div_ops = { 1921 .get_rate = clk_stm32_divider_get_rate, 1922 .set_rate = clk_stm32_hse_div_set_rate, 1923 }; 1924 1925 static TEE_Result clk_stm32_hsediv2_enable(struct clk *clk) 1926 { 1927 return clk_stm32_gate_ops.enable(clk); 1928 } 1929 1930 static void clk_stm32_hsediv2_disable(struct clk *clk) 1931 { 1932 clk_stm32_gate_ops.disable(clk); 1933 } 1934 1935 static unsigned long clk_stm32_hsediv2_get_rate(struct clk *clk __unused, 1936 unsigned long prate) 1937 { 1938 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 1939 uintptr_t addr = priv->base + RCC_OCENSETR; 1940 1941 if (io_read32(addr) & RCC_OCENSETR_HSEDIV2BYP) 1942 return prate; 1943 1944 return prate / 2; 1945 } 1946 1947 static const struct clk_ops clk_hsediv2_ops = { 1948 .enable = clk_stm32_hsediv2_enable, 1949 .disable = clk_stm32_hsediv2_disable, 1950 .get_rate = clk_stm32_hsediv2_get_rate, 1951 }; 1952 1953 struct clk_stm32_pll_cfg { 1954 uint32_t pll_offset; 1955 int gate_id; 1956 int mux_id; 1957 }; 1958 1959 static unsigned long clk_get_pll1_fvco_rate(unsigned long refclk) 1960 { 1961 uint32_t reg = stm32mp_syscfg_read(A35SS_SSC_PLL_FREQ1); 1962 uint32_t fbdiv = 0; 1963 uint32_t refdiv = 0; 1964 unsigned long freq = 0; 1965 1966 fbdiv = (reg & A35SS_SSC_PLL_FREQ1_FBDIV_MASK) >> 1967 A35SS_SSC_PLL_FREQ1_FBDIV_SHIFT; 1968 1969 refdiv = (reg & A35SS_SSC_PLL_FREQ1_REFDIV_MASK) >> 1970 A35SS_SSC_PLL_FREQ1_REFDIV_SHIFT; 1971 1972 if (!refdiv || MUL_OVERFLOW(refclk, fbdiv, &freq)) 1973 panic(); 1974 1975 return freq / refdiv; 1976 } 1977 1978 static unsigned long clk_stm32_pll1_get_rate(struct clk *clk __unused, 1979 unsigned long prate) 1980 { 1981 uint32_t reg = stm32mp_syscfg_read(A35SS_SSC_PLL_FREQ2); 1982 unsigned long dfout = 0; 1983 uint32_t postdiv1 = 0; 1984 uint32_t postdiv2 = 0; 1985 1986 postdiv1 = (reg & A35SS_SSC_PLL_FREQ2_POSTDIV1_MASK) >> 1987 A35SS_SSC_PLL_FREQ2_POSTDIV1_SHIFT; 1988 1989 postdiv2 = (reg & A35SS_SSC_PLL_FREQ2_POSTDIV2_MASK) >> 1990 A35SS_SSC_PLL_FREQ2_POSTDIV2_SHIFT; 1991 1992 if (postdiv1 == 0 || postdiv2 == 0) 1993 dfout = prate; 1994 else 1995 dfout = clk_get_pll1_fvco_rate(prate) / (postdiv1 * postdiv2); 1996 1997 return dfout; 1998 } 1999 2000 static struct stm32_clk_opp_cfg * 2001 clk_stm32_get_opp_config(struct stm32_clk_opp_cfg *opp_cfg, unsigned long rate) 2002 { 2003 unsigned int i = 0; 2004 2005 for (i = 0; i < MAX_OPP && opp_cfg->frq; i++, opp_cfg++) 2006 if (opp_cfg->frq == rate) 2007 return opp_cfg; 2008 2009 return NULL; 2010 } 2011 2012 static TEE_Result clk_stm32_pll1_set_rate(struct clk *clk __unused, 2013 unsigned long rate, 2014 unsigned long parent_rate __unused) 2015 { 2016 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 2017 struct stm32_clk_platdata *pdata = priv->pdata; 2018 struct stm32_pll_dt_cfg *pll_conf = NULL; 2019 struct stm32_clk_opp_cfg *opp = NULL; 2020 2021 opp = clk_stm32_get_opp_config(pdata->opp->cpu1_opp, rate); 2022 if (!opp) 2023 return TEE_ERROR_GENERIC; 2024 2025 pll_conf = &opp->pll_cfg; 2026 2027 clk_stm32_pll1_init(priv, PLL1_ID, pll_conf); 2028 2029 return TEE_SUCCESS; 2030 } 2031 2032 static size_t clk_stm32_pll_get_parent(struct clk *clk) 2033 { 2034 struct clk_stm32_pll_cfg *cfg = clk->priv; 2035 2036 return stm32_mux_get_parent(cfg->mux_id); 2037 } 2038 2039 static const struct clk_ops clk_stm32_pll1_ops = { 2040 .get_parent = clk_stm32_pll_get_parent, 2041 .get_rate = clk_stm32_pll1_get_rate, 2042 .set_rate = clk_stm32_pll1_set_rate, 2043 }; 2044 2045 static unsigned long clk_get_pll_fvco(uint32_t offset_base, 2046 unsigned long prate) 2047 { 2048 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 2049 uintptr_t pllxcfgr1 = priv->base + offset_base; 2050 uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2; 2051 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3; 2052 unsigned long fvco = 0; 2053 uint32_t fracin = 0; 2054 uint32_t fbdiv = 0; 2055 uint32_t refdiv = 0; 2056 2057 fracin = io_read32(pllxcfgr3) & RCC_PLLxCFGR3_FRACIN_MASK; 2058 fbdiv = (io_read32(pllxcfgr2) & RCC_PLLxCFGR2_FBDIV_MASK) >> 2059 RCC_PLLxCFGR2_FBDIV_SHIFT; 2060 2061 refdiv = io_read32(pllxcfgr2) & RCC_PLLxCFGR2_FREFDIV_MASK; 2062 2063 assert(refdiv); 2064 2065 if (fracin) { 2066 unsigned long long numerator = 0; 2067 unsigned long long denominator = 0; 2068 2069 numerator = SHIFT_U64(fbdiv, 24) + fracin; 2070 numerator = prate * numerator; 2071 denominator = SHIFT_U64(refdiv, 24); 2072 fvco = (unsigned long)(numerator / denominator); 2073 } else { 2074 fvco = (unsigned long)(prate * fbdiv / refdiv); 2075 } 2076 2077 return fvco; 2078 } 2079 2080 static unsigned long clk_stm32_pll_get_rate(struct clk *clk __unused, 2081 unsigned long prate) 2082 { 2083 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 2084 struct clk_stm32_pll_cfg *cfg = clk->priv; 2085 uintptr_t pllxcfgr1 = priv->base + cfg->pll_offset; 2086 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4; 2087 uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6; 2088 uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7; 2089 unsigned long dfout = 0; 2090 uint32_t postdiv1 = 0; 2091 uint32_t postdiv2 = 0; 2092 2093 postdiv1 = io_read32(pllxcfgr6) & RCC_PLLxCFGR6_POSTDIV1_MASK; 2094 postdiv2 = io_read32(pllxcfgr7) & RCC_PLLxCFGR7_POSTDIV2_MASK; 2095 2096 if ((io_read32(pllxcfgr4) & RCC_PLLxCFGR4_BYPASS) || 2097 !postdiv1 || !postdiv2) 2098 dfout = prate; 2099 else 2100 dfout = clk_get_pll_fvco(cfg->pll_offset, 2101 prate) / (postdiv1 * postdiv2); 2102 2103 return dfout; 2104 } 2105 2106 static TEE_Result clk_stm32_pll_enable(struct clk *clk) 2107 { 2108 struct clk_stm32_pll_cfg *cfg = clk->priv; 2109 2110 if (stm32_gate_rdy_enable(cfg->gate_id)) { 2111 EMSG("%s timeout", clk_get_name(clk)); 2112 return TEE_ERROR_TIMEOUT; 2113 } 2114 2115 return TEE_SUCCESS; 2116 } 2117 2118 static void clk_stm32_pll_disable(struct clk *clk) 2119 { 2120 struct clk_stm32_pll_cfg *cfg = clk->priv; 2121 2122 if (stm32_gate_rdy_disable(cfg->gate_id)) { 2123 EMSG("%s timeout", clk_get_name(clk)); 2124 panic(); 2125 } 2126 } 2127 2128 static const struct clk_ops clk_stm32_pll_ops = { 2129 .get_parent = clk_stm32_pll_get_parent, 2130 .get_rate = clk_stm32_pll_get_rate, 2131 .enable = clk_stm32_pll_enable, 2132 .disable = clk_stm32_pll_disable, 2133 }; 2134 2135 static TEE_Result clk_stm32_pll3_enable(struct clk *clk) 2136 { 2137 struct clk_stm32_pll_cfg *cfg = clk->priv; 2138 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 2139 struct stm32_pll_dt_cfg *pll_conf = clk_stm32_pll_get_pdata(PLL3_ID); 2140 struct clk *parent = NULL; 2141 size_t pidx = 0; 2142 2143 /* ck_icn_p_gpu activate */ 2144 stm32_gate_enable(GATE_GPU); 2145 2146 clk_stm32_pll_init(priv, PLL3_ID, pll_conf); 2147 2148 if (stm32_gate_rdy_enable(cfg->gate_id)) { 2149 EMSG("%s timeout", clk_get_name(clk)); 2150 return TEE_ERROR_TIMEOUT; 2151 } 2152 2153 /* Update parent */ 2154 pidx = clk_stm32_pll_get_parent(clk); 2155 parent = clk_get_parent_by_index(clk, pidx); 2156 2157 clk->parent = parent; 2158 2159 return TEE_SUCCESS; 2160 } 2161 2162 static void clk_stm32_pll3_disable(struct clk *clk) 2163 { 2164 clk_stm32_pll_disable(clk); 2165 stm32_gate_disable(GATE_GPU); 2166 } 2167 2168 static const struct clk_ops clk_stm32_pll3_ops = { 2169 .get_parent = clk_stm32_pll_get_parent, 2170 .get_rate = clk_stm32_pll_get_rate, 2171 .enable = clk_stm32_pll3_enable, 2172 .disable = clk_stm32_pll3_disable, 2173 }; 2174 2175 struct clk_stm32_flexgen_cfg { 2176 int flex_id; 2177 }; 2178 2179 static size_t clk_stm32_flexgen_get_parent(struct clk *clk) 2180 { 2181 struct clk_stm32_flexgen_cfg *cfg = clk->priv; 2182 uintptr_t rcc_base = clk_stm32_get_rcc_base(); 2183 uint32_t address = 0; 2184 2185 address = rcc_base + RCC_XBAR0CFGR + (cfg->flex_id * 4); 2186 2187 return io_read32(address) & RCC_XBAR0CFGR_XBAR0SEL_MASK; 2188 } 2189 2190 static TEE_Result clk_stm32_flexgen_set_parent(struct clk *clk, size_t pidx) 2191 { 2192 uintptr_t rcc_base = clk_stm32_get_rcc_base(); 2193 struct clk_stm32_flexgen_cfg *cfg = clk->priv; 2194 uint16_t channel = cfg->flex_id * 4; 2195 2196 io_clrsetbits32(rcc_base + RCC_XBAR0CFGR + (channel), 2197 RCC_XBAR0CFGR_XBAR0SEL_MASK, pidx); 2198 2199 if (wait_xbar_sts(channel)) 2200 return TEE_ERROR_GENERIC; 2201 2202 return TEE_SUCCESS; 2203 } 2204 2205 static unsigned long clk_stm32_flexgen_get_rate(struct clk *clk __unused, 2206 unsigned long prate) 2207 { 2208 struct clk_stm32_flexgen_cfg *cfg = clk->priv; 2209 uintptr_t rcc_base = clk_stm32_get_rcc_base(); 2210 uint32_t prediv = 0; 2211 uint32_t findiv = 0; 2212 uint8_t channel = cfg->flex_id; 2213 unsigned long freq = prate; 2214 2215 prediv = io_read32(rcc_base + RCC_PREDIV0CFGR + (0x4 * channel)) & 2216 RCC_PREDIV0CFGR_PREDIV0_MASK; 2217 findiv = io_read32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel)) & 2218 RCC_FINDIV0CFGR_FINDIV0_MASK; 2219 2220 if (freq == 0) 2221 return 0; 2222 2223 switch (prediv) { 2224 case 0x0: 2225 break; 2226 2227 case 0x1: 2228 freq /= 2; 2229 break; 2230 2231 case 0x3: 2232 freq /= 4; 2233 break; 2234 2235 case 0x3FF: 2236 freq /= 1024; 2237 break; 2238 2239 default: 2240 EMSG("Unsupported PREDIV value (%#"PRIx32")", prediv); 2241 panic(); 2242 break; 2243 } 2244 2245 freq /= findiv + 1; 2246 2247 return freq; 2248 } 2249 2250 static unsigned long clk_stm32_flexgen_get_round_rate(unsigned long rate, 2251 unsigned long prate, 2252 unsigned int *prediv, 2253 unsigned int *findiv) 2254 { 2255 unsigned int pre_val[] = { 0x0, 0x1, 0x3, 0x3FF }; 2256 unsigned int pre_div[] = { 1, 2, 4, 1024 }; 2257 long best_diff = LONG_MAX; 2258 unsigned int i = 0; 2259 2260 *prediv = 0; 2261 *findiv = 0; 2262 2263 for (i = 0; i < ARRAY_SIZE(pre_div); i++) { 2264 unsigned long freq = 0; 2265 unsigned long ratio = 0; 2266 long diff = 0L; 2267 2268 freq = UDIV_ROUND_NEAREST((uint64_t)prate, pre_div[i]); 2269 ratio = UDIV_ROUND_NEAREST((uint64_t)freq, rate); 2270 2271 if (ratio == 0) 2272 ratio = 1; 2273 else if (ratio > 64) 2274 ratio = 64; 2275 2276 freq = UDIV_ROUND_NEAREST((uint64_t)freq, ratio); 2277 if (freq < rate) 2278 diff = rate - freq; 2279 else 2280 diff = freq - rate; 2281 2282 if (diff < best_diff) { 2283 best_diff = diff; 2284 *prediv = pre_val[i]; 2285 *findiv = ratio - 1; 2286 2287 if (diff == 0) 2288 break; 2289 } 2290 } 2291 2292 return (prate / (*prediv + 1)) / (*findiv + 1); 2293 } 2294 2295 static TEE_Result clk_stm32_flexgen_set_rate(struct clk *clk, 2296 unsigned long rate, 2297 unsigned long parent_rate) 2298 { 2299 struct clk_stm32_flexgen_cfg *cfg = clk->priv; 2300 uint8_t channel = cfg->flex_id; 2301 uintptr_t rcc_base = stm32_rcc_base(); 2302 unsigned int prediv = 0; 2303 unsigned int findiv = 0; 2304 2305 clk_stm32_flexgen_get_round_rate(rate, parent_rate, &prediv, &findiv); 2306 2307 if (wait_predivsr(channel) != 0) 2308 panic(); 2309 2310 io_clrsetbits32(rcc_base + RCC_PREDIV0CFGR + (0x4 * channel), 2311 RCC_PREDIV0CFGR_PREDIV0_MASK, 2312 prediv); 2313 2314 if (wait_predivsr(channel) != 0) 2315 panic(); 2316 2317 if (wait_findivsr(channel) != 0) 2318 panic(); 2319 2320 io_clrsetbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel), 2321 RCC_FINDIV0CFGR_FINDIV0_MASK, 2322 findiv); 2323 2324 if (wait_findivsr(channel) != 0) 2325 panic(); 2326 2327 return TEE_SUCCESS; 2328 } 2329 2330 static TEE_Result clk_stm32_flexgen_enable(struct clk *clk) 2331 { 2332 struct clk_stm32_flexgen_cfg *cfg = clk->priv; 2333 uintptr_t rcc_base = clk_stm32_get_rcc_base(); 2334 uint8_t channel = cfg->flex_id; 2335 2336 io_setbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel), 2337 RCC_FINDIV0CFGR_FINDIV0EN); 2338 2339 return TEE_SUCCESS; 2340 } 2341 2342 static void clk_stm32_flexgen_disable(struct clk *clk) 2343 { 2344 struct clk_stm32_flexgen_cfg *cfg = clk->priv; 2345 uintptr_t rcc_base = clk_stm32_get_rcc_base(); 2346 uint8_t channel = cfg->flex_id; 2347 2348 io_clrbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel), 2349 RCC_FINDIV0CFGR_FINDIV0EN); 2350 } 2351 2352 static const struct clk_ops clk_stm32_flexgen_ops = { 2353 .get_rate = clk_stm32_flexgen_get_rate, 2354 .set_rate = clk_stm32_flexgen_set_rate, 2355 .get_parent = clk_stm32_flexgen_get_parent, 2356 .set_parent = clk_stm32_flexgen_set_parent, 2357 .enable = clk_stm32_flexgen_enable, 2358 .disable = clk_stm32_flexgen_disable, 2359 }; 2360 2361 static size_t clk_cpu1_get_parent(struct clk *clk __unused) 2362 { 2363 uint32_t reg = stm32mp_syscfg_read(A35SS_SSC_CHGCLKREQ); 2364 2365 return (reg & A35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK) >> 2366 A35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_SHIFT; 2367 } 2368 2369 static const struct clk_ops clk_stm32_cpu1_ops = { 2370 .get_parent = clk_cpu1_get_parent, 2371 }; 2372 2373 #define APB_DIV_MASK GENMASK_32(2, 0) 2374 #define TIM_PRE_MASK BIT(0) 2375 2376 static unsigned long ck_timer_get_rate_ops(struct clk *clk, unsigned long prate) 2377 { 2378 struct clk_stm32_timer_cfg *cfg = clk->priv; 2379 uintptr_t rcc_base = clk_stm32_get_rcc_base(); 2380 uint32_t prescaler = 0; 2381 uint32_t timpre = 0; 2382 2383 prescaler = io_read32(rcc_base + cfg->apbdiv) & APB_DIV_MASK; 2384 2385 timpre = io_read32(rcc_base + cfg->timpre) & TIM_PRE_MASK; 2386 2387 if (prescaler == 0) 2388 return prate; 2389 2390 return prate * (timpre + 1) * 2; 2391 }; 2392 2393 static const struct clk_ops ck_timer_ops = { 2394 .get_rate = ck_timer_get_rate_ops, 2395 }; 2396 2397 #define PLL_PARENTS { &ck_hsi, &ck_hse, &ck_msi } 2398 #define PLL_NUM_PATENTS 3 2399 2400 #define STM32_OSC(_name, _flags, _gate_id)\ 2401 struct clk _name = {\ 2402 .ops = &clk_stm32_osc_ops,\ 2403 .priv = &(struct clk_stm32_gate_cfg){\ 2404 .gate_id = (_gate_id),\ 2405 },\ 2406 .name = #_name,\ 2407 .flags = (_flags),\ 2408 .num_parents = 1,\ 2409 .parents = { NULL },\ 2410 } 2411 2412 #define STM32_OSC_MSI(_name, _flags, _gate_id)\ 2413 struct clk _name = {\ 2414 .ops = &clk_stm32_oscillator_msi_ops,\ 2415 .priv = &(struct clk_stm32_gate_cfg){\ 2416 .gate_id = (_gate_id),\ 2417 },\ 2418 .name = #_name,\ 2419 .flags = (_flags),\ 2420 .num_parents = 1,\ 2421 .parents = { NULL },\ 2422 } 2423 2424 #define STM32_HSE_DIV2(_name, _parent, _flags, _gate_id)\ 2425 struct clk _name = {\ 2426 .ops = &clk_hsediv2_ops,\ 2427 .priv = &(struct clk_stm32_gate_cfg){\ 2428 .gate_id = (_gate_id),\ 2429 },\ 2430 .name = #_name,\ 2431 .flags = (_flags),\ 2432 .num_parents = 1,\ 2433 .parents = { (_parent) },\ 2434 } 2435 2436 #define STM32_HSE_RTC(_name, _parent, _flags, _div_id)\ 2437 struct clk _name = {\ 2438 .ops = &clk_stm32_hse_div_ops,\ 2439 .priv = &(struct clk_stm32_div_cfg){\ 2440 .div_id = (_div_id),\ 2441 },\ 2442 .name = #_name,\ 2443 .flags = (_flags),\ 2444 .num_parents = 1,\ 2445 .parents = { (_parent) },\ 2446 } 2447 2448 #define STM32_PLL1(_name, _flags, _mux_id)\ 2449 struct clk _name = {\ 2450 .ops = &clk_stm32_pll1_ops,\ 2451 .priv = &(struct clk_stm32_pll_cfg){\ 2452 .mux_id = (_mux_id),\ 2453 },\ 2454 .name = #_name,\ 2455 .flags = (_flags),\ 2456 .num_parents = PLL_NUM_PATENTS,\ 2457 .parents = PLL_PARENTS,\ 2458 } 2459 2460 #define STM32_PLL2(_name, _flags, _reg, _gate_id, _mux_id)\ 2461 struct clk _name = {\ 2462 .ops = &clk_stm32_pll_ops,\ 2463 .priv = &(struct clk_stm32_pll_cfg){\ 2464 .pll_offset = (_reg),\ 2465 .gate_id = (_gate_id),\ 2466 .mux_id = (_mux_id),\ 2467 },\ 2468 .name = #_name,\ 2469 .flags = (_flags),\ 2470 .num_parents = PLL_NUM_PATENTS,\ 2471 .parents = PLL_PARENTS,\ 2472 } 2473 2474 #define STM32_PLL3(_name, _flags, _reg, _gate_id, _mux_id)\ 2475 struct clk _name = {\ 2476 .ops = &clk_stm32_pll3_ops,\ 2477 .priv = &(struct clk_stm32_pll_cfg){\ 2478 .pll_offset = (_reg),\ 2479 .gate_id = (_gate_id),\ 2480 .mux_id = (_mux_id),\ 2481 },\ 2482 .name = #_name,\ 2483 .flags = (_flags),\ 2484 .num_parents = PLL_NUM_PATENTS,\ 2485 .parents = PLL_PARENTS,\ 2486 } 2487 2488 #define STM32_PLLS(_name, _flags, _reg, _gate_id, _mux_id)\ 2489 struct clk _name = {\ 2490 .ops = &clk_stm32_pll_ops,\ 2491 .priv = &(struct clk_stm32_pll_cfg){\ 2492 .pll_offset = (_reg),\ 2493 .gate_id = (_gate_id),\ 2494 .mux_id = (_mux_id),\ 2495 },\ 2496 .name = #_name,\ 2497 .flags = (_flags),\ 2498 .num_parents = PLL_NUM_PATENTS,\ 2499 .parents = PLL_PARENTS,\ 2500 } 2501 2502 static STM32_FIXED_RATE(ck_off, RCC_0_MHZ); 2503 2504 static STM32_FIXED_RATE(ck_obser0, 0); 2505 static STM32_FIXED_RATE(ck_obser1, 0); 2506 static STM32_FIXED_RATE(spdifsymb, 0); 2507 static STM32_FIXED_RATE(txbyteclk, 27000000); 2508 2509 /* Oscillator clocks */ 2510 static STM32_OSC(ck_hsi, 0, GATE_HSI); 2511 static STM32_OSC(ck_hse, 0, GATE_HSE); 2512 static STM32_OSC_MSI(ck_msi, 0, GATE_MSI); 2513 static STM32_OSC(ck_lsi, 0, GATE_LSI); 2514 static STM32_OSC(ck_lse, 0, GATE_LSE); 2515 2516 static STM32_HSE_DIV2(ck_hse_div2, &ck_hse, 0, GATE_HSEDIV2); 2517 static STM32_HSE_RTC(ck_hse_rtc, &ck_hse, 0, DIV_RTC); 2518 2519 static STM32_FIXED_FACTOR(i2sckin, NULL, 0, 1, 1); 2520 2521 static STM32_PLL1(ck_pll1, 0, MUX_MUXSEL5); 2522 static STM32_PLL2(ck_pll2, 0, RCC_PLL2CFGR1, GATE_PLL2, MUX_MUXSEL6); 2523 static STM32_PLL3(ck_pll3, 0, RCC_PLL3CFGR1, GATE_PLL3, MUX_MUXSEL7); 2524 static STM32_PLLS(ck_pll4, 0, RCC_PLL4CFGR1, GATE_PLL4, MUX_MUXSEL0); 2525 static STM32_PLLS(ck_pll5, 0, RCC_PLL5CFGR1, GATE_PLL5, MUX_MUXSEL1); 2526 static STM32_PLLS(ck_pll6, 0, RCC_PLL6CFGR1, GATE_PLL6, MUX_MUXSEL2); 2527 static STM32_PLLS(ck_pll7, 0, RCC_PLL7CFGR1, GATE_PLL7, MUX_MUXSEL3); 2528 static STM32_PLLS(ck_pll8, 0, RCC_PLL8CFGR1, GATE_PLL8, MUX_MUXSEL4); 2529 2530 #define STM32_FLEXGEN(_name, _flags, _flex_id)\ 2531 struct clk _name = {\ 2532 .ops = &clk_stm32_flexgen_ops,\ 2533 .priv = &(struct clk_stm32_flexgen_cfg){\ 2534 .flex_id = (_flex_id),\ 2535 },\ 2536 .name = #_name,\ 2537 .flags = (_flags) | CLK_SET_RATE_UNGATE,\ 2538 .num_parents = 15,\ 2539 .parents = {\ 2540 &ck_pll4, &ck_pll5, &ck_pll6, &ck_pll7, &ck_pll8,\ 2541 &ck_hsi, &ck_hse, &ck_msi, &ck_hsi, &ck_hse, &ck_msi,\ 2542 &spdifsymb, &i2sckin, &ck_lsi, &ck_lse\ 2543 },\ 2544 } 2545 2546 static STM32_FLEXGEN(ck_icn_hs_mcu, 0, 0); 2547 static STM32_FLEXGEN(ck_icn_sdmmc, 0, 1); 2548 static STM32_FLEXGEN(ck_icn_ddr, 0, 2); 2549 static STM32_FLEXGEN(ck_icn_display, 0, 3); 2550 static STM32_FLEXGEN(ck_icn_hsl, 0, 4); 2551 static STM32_FLEXGEN(ck_icn_nic, 0, 5); 2552 static STM32_FLEXGEN(ck_icn_vid, 0, 6); 2553 2554 static STM32_DIVIDER(ck_icn_ls_mcu, &ck_icn_hs_mcu, 0, DIV_LSMCU); 2555 2556 static STM32_FLEXGEN(ck_flexgen_07, 0, 7); 2557 static STM32_FLEXGEN(ck_flexgen_08, 0, 8); 2558 static STM32_FLEXGEN(ck_flexgen_09, 0, 9); 2559 static STM32_FLEXGEN(ck_flexgen_10, 0, 10); 2560 static STM32_FLEXGEN(ck_flexgen_11, 0, 11); 2561 static STM32_FLEXGEN(ck_flexgen_12, 0, 12); 2562 static STM32_FLEXGEN(ck_flexgen_13, 0, 13); 2563 static STM32_FLEXGEN(ck_flexgen_14, 0, 14); 2564 static STM32_FLEXGEN(ck_flexgen_15, 0, 15); 2565 static STM32_FLEXGEN(ck_flexgen_16, 0, 16); 2566 static STM32_FLEXGEN(ck_flexgen_17, 0, 17); 2567 static STM32_FLEXGEN(ck_flexgen_18, 0, 18); 2568 static STM32_FLEXGEN(ck_flexgen_19, 0, 19); 2569 static STM32_FLEXGEN(ck_flexgen_20, 0, 20); 2570 static STM32_FLEXGEN(ck_flexgen_21, 0, 21); 2571 static STM32_FLEXGEN(ck_flexgen_22, 0, 22); 2572 static STM32_FLEXGEN(ck_flexgen_23, 0, 23); 2573 static STM32_FLEXGEN(ck_flexgen_24, 0, 24); 2574 static STM32_FLEXGEN(ck_flexgen_25, 0, 25); 2575 static STM32_FLEXGEN(ck_flexgen_26, 0, 26); 2576 static STM32_FLEXGEN(ck_flexgen_27, 0, 27); 2577 static STM32_FLEXGEN(ck_flexgen_28, 0, 28); 2578 static STM32_FLEXGEN(ck_flexgen_29, 0, 29); 2579 static STM32_FLEXGEN(ck_flexgen_30, 0, 30); 2580 static STM32_FLEXGEN(ck_flexgen_31, 0, 31); 2581 static STM32_FLEXGEN(ck_flexgen_32, 0, 32); 2582 static STM32_FLEXGEN(ck_flexgen_33, 0, 33); 2583 static STM32_FLEXGEN(ck_flexgen_34, 0, 34); 2584 static STM32_FLEXGEN(ck_flexgen_35, 0, 35); 2585 static STM32_FLEXGEN(ck_flexgen_36, 0, 36); 2586 static STM32_FLEXGEN(ck_flexgen_37, 0, 37); 2587 static STM32_FLEXGEN(ck_flexgen_38, 0, 38); 2588 static STM32_FLEXGEN(ck_flexgen_39, 0, 39); 2589 static STM32_FLEXGEN(ck_flexgen_40, 0, 40); 2590 static STM32_FLEXGEN(ck_flexgen_41, 0, 41); 2591 static STM32_FLEXGEN(ck_flexgen_42, 0, 42); 2592 static STM32_FLEXGEN(ck_flexgen_43, 0, 43); 2593 static STM32_FLEXGEN(ck_flexgen_44, 0, 44); 2594 static STM32_FLEXGEN(ck_flexgen_45, 0, 45); 2595 static STM32_FLEXGEN(ck_flexgen_46, 0, 46); 2596 static STM32_FLEXGEN(ck_flexgen_47, 0, 47); 2597 static STM32_FLEXGEN(ck_flexgen_48, 0, 48); 2598 static STM32_FLEXGEN(ck_flexgen_49, 0, 49); 2599 static STM32_FLEXGEN(ck_flexgen_50, 0, 50); 2600 static STM32_FLEXGEN(ck_flexgen_51, 0, 51); 2601 static STM32_FLEXGEN(ck_flexgen_52, 0, 52); 2602 static STM32_FLEXGEN(ck_flexgen_53, 0, 53); 2603 static STM32_FLEXGEN(ck_flexgen_54, 0, 54); 2604 static STM32_FLEXGEN(ck_flexgen_55, 0, 55); 2605 static STM32_FLEXGEN(ck_flexgen_56, 0, 56); 2606 static STM32_FLEXGEN(ck_flexgen_57, 0, 57); 2607 static STM32_FLEXGEN(ck_flexgen_58, 0, 58); 2608 static STM32_FLEXGEN(ck_flexgen_59, 0, 59); 2609 static STM32_FLEXGEN(ck_flexgen_60, 0, 60); 2610 static STM32_FLEXGEN(ck_flexgen_61, 0, 61); 2611 static STM32_FLEXGEN(ck_flexgen_62, 0, 62); 2612 static STM32_FLEXGEN(ck_flexgen_63, 0, 63); 2613 2614 static struct clk ck_cpu1 = { 2615 .ops = &clk_stm32_cpu1_ops, 2616 .name = "ck_cpu1", 2617 .flags = CLK_SET_RATE_PARENT, 2618 .num_parents = 2, 2619 .parents = { &ck_pll1, &ck_flexgen_63 }, 2620 }; 2621 2622 static STM32_DIVIDER(ck_icn_apb1, &ck_icn_ls_mcu, 0, DIV_APB1); 2623 static STM32_DIVIDER(ck_icn_apb2, &ck_icn_ls_mcu, 0, DIV_APB2); 2624 static STM32_DIVIDER(ck_icn_apb3, &ck_icn_ls_mcu, 0, DIV_APB3); 2625 static STM32_DIVIDER(ck_icn_apb4, &ck_icn_ls_mcu, 0, DIV_APB4); 2626 static STM32_COMPOSITE(ck_icn_apbdbg, 1, { &ck_icn_ls_mcu }, 0, 2627 GATE_DBG, DIV_APBDBG, NO_MUX); 2628 2629 #define STM32_TIMER(_name, _parent, _flags, _apbdiv, _timpre)\ 2630 struct clk _name = {\ 2631 .ops = &ck_timer_ops,\ 2632 .priv = &(struct clk_stm32_timer_cfg){\ 2633 .apbdiv = (_apbdiv),\ 2634 .timpre = (_timpre),\ 2635 },\ 2636 .name = #_name,\ 2637 .flags = (_flags),\ 2638 .num_parents = 1,\ 2639 .parents = { _parent },\ 2640 } 2641 2642 /* Kernel Timers */ 2643 static STM32_TIMER(ck_timg1, &ck_icn_apb1, 0, RCC_APB1DIVR, RCC_TIMG1PRER); 2644 static STM32_TIMER(ck_timg2, &ck_icn_apb2, 0, RCC_APB2DIVR, RCC_TIMG2PRER); 2645 2646 /* Clocks under RCC RIF protection */ 2647 static STM32_GATE(ck_sys_dbg, &ck_icn_apbdbg, 0, GATE_DBG); 2648 static STM32_GATE(ck_icn_p_stm, &ck_icn_apbdbg, 0, GATE_STM); 2649 static STM32_GATE(ck_icn_s_stm, &ck_icn_ls_mcu, 0, GATE_STM); 2650 static STM32_GATE(ck_ker_tsdbg, &ck_flexgen_43, 0, GATE_DBG); 2651 static STM32_GATE(ck_ker_tpiu, &ck_flexgen_44, 0, GATE_TRACE); 2652 static STM32_GATE(ck_icn_p_etr, &ck_icn_apbdbg, 0, GATE_ETR); 2653 static STM32_GATE(ck_icn_m_etr, &ck_flexgen_45, 0, GATE_ETR); 2654 static STM32_GATE(ck_sys_atb, &ck_flexgen_45, 0, GATE_DBG); 2655 2656 static STM32_GATE(ck_icn_s_sysram, &ck_icn_hs_mcu, 0, GATE_SYSRAM); 2657 static STM32_GATE(ck_icn_s_vderam, &ck_icn_hs_mcu, 0, GATE_VDERAM); 2658 static STM32_GATE(ck_icn_s_retram, &ck_icn_hs_mcu, 0, GATE_RETRAM); 2659 static STM32_GATE(ck_icn_s_bkpsram, &ck_icn_ls_mcu, 0, GATE_BKPSRAM); 2660 static STM32_GATE(ck_icn_s_sram1, &ck_icn_hs_mcu, 0, GATE_SRAM1); 2661 static STM32_GATE(ck_icn_s_sram2, &ck_icn_hs_mcu, 0, GATE_SRAM2); 2662 static STM32_GATE(ck_icn_s_lpsram1, &ck_icn_ls_mcu, 0, GATE_LPSRAM1); 2663 static STM32_GATE(ck_icn_s_lpsram2, &ck_icn_ls_mcu, 0, GATE_LPSRAM2); 2664 static STM32_GATE(ck_icn_s_lpsram3, &ck_icn_ls_mcu, 0, GATE_LPSRAM3); 2665 static STM32_GATE(ck_icn_p_hpdma1, &ck_icn_ls_mcu, 0, GATE_HPDMA1); 2666 static STM32_GATE(ck_icn_p_hpdma2, &ck_icn_ls_mcu, 0, GATE_HPDMA2); 2667 static STM32_GATE(ck_icn_p_hpdma3, &ck_icn_ls_mcu, 0, GATE_HPDMA3); 2668 static STM32_GATE(ck_icn_p_lpdma, &ck_icn_ls_mcu, 0, GATE_LPDMA); 2669 static STM32_GATE(ck_icn_p_ipcc1, &ck_icn_ls_mcu, 0, GATE_IPCC1); 2670 static STM32_GATE(ck_icn_p_ipcc2, &ck_icn_ls_mcu, 0, GATE_IPCC2); 2671 static STM32_GATE(ck_icn_p_hsem, &ck_icn_ls_mcu, 0, GATE_HSEM); 2672 static STM32_GATE(ck_icn_p_gpioa, &ck_icn_ls_mcu, 0, GATE_GPIOA); 2673 static STM32_GATE(ck_icn_p_gpiob, &ck_icn_ls_mcu, 0, GATE_GPIOB); 2674 static STM32_GATE(ck_icn_p_gpioc, &ck_icn_ls_mcu, 0, GATE_GPIOC); 2675 static STM32_GATE(ck_icn_p_gpiod, &ck_icn_ls_mcu, 0, GATE_GPIOD); 2676 static STM32_GATE(ck_icn_p_gpioe, &ck_icn_ls_mcu, 0, GATE_GPIOE); 2677 static STM32_GATE(ck_icn_p_gpiof, &ck_icn_ls_mcu, 0, GATE_GPIOF); 2678 static STM32_GATE(ck_icn_p_gpiog, &ck_icn_ls_mcu, 0, GATE_GPIOG); 2679 static STM32_GATE(ck_icn_p_gpioh, &ck_icn_ls_mcu, 0, GATE_GPIOH); 2680 static STM32_GATE(ck_icn_p_gpioi, &ck_icn_ls_mcu, 0, GATE_GPIOI); 2681 static STM32_GATE(ck_icn_p_gpioj, &ck_icn_ls_mcu, 0, GATE_GPIOJ); 2682 static STM32_GATE(ck_icn_p_gpiok, &ck_icn_ls_mcu, 0, GATE_GPIOK); 2683 static STM32_GATE(ck_icn_p_gpioz, &ck_icn_ls_mcu, 0, GATE_GPIOZ); 2684 static STM32_GATE(ck_icn_p_rtc, &ck_icn_ls_mcu, 0, GATE_RTC); 2685 static STM32_COMPOSITE(ck_rtc, 4, 2686 PARENT(&ck_off, &ck_lse, &ck_lsi, &ck_hse_rtc), 2687 0, GATE_RTCCK, NO_DIV, MUX_RTC); 2688 static STM32_GATE(ck_icn_p_bsec, &ck_icn_apb3, 0, GATE_BSEC); 2689 static STM32_GATE(ck_icn_p_ddrphyc, &ck_icn_ls_mcu, 0, GATE_DDRPHYCAPB); 2690 static STM32_GATE(ck_icn_p_risaf4, &ck_icn_ls_mcu, 0, GATE_DDRCP); 2691 static STM32_GATE(ck_icn_s_ddr, &ck_icn_ddr, 0, GATE_DDRCP); 2692 static STM32_GATE(ck_icn_p_ddrc, &ck_icn_apb4, 0, GATE_DDRCAPB); 2693 static STM32_GATE(ck_icn_p_ddrcfg, &ck_icn_apb4, 0, GATE_DDRCFG); 2694 static STM32_GATE(ck_icn_p_syscpu1, &ck_icn_ls_mcu, 0, GATE_SYSCPU1); 2695 static STM32_GATE(ck_icn_p_is2m, &ck_icn_apb3, 0, GATE_IS2M); 2696 static STM32_COMPOSITE(ck_mco1, 2, PARENT(&ck_flexgen_61, &ck_obser0), 0, 2697 GATE_MCO1, NO_DIV, MUX_MCO1); 2698 static STM32_COMPOSITE(ck_mco2, 2, PARENT(&ck_flexgen_62, &ck_obser1), 0, 2699 GATE_MCO2, NO_DIV, MUX_MCO2); 2700 static STM32_GATE(ck_icn_s_ospi1, &ck_icn_hs_mcu, 0, GATE_OSPI1); 2701 static STM32_GATE(ck_ker_ospi1, &ck_flexgen_48, 0, GATE_OSPI1); 2702 static STM32_GATE(ck_icn_s_ospi2, &ck_icn_hs_mcu, 0, GATE_OSPI2); 2703 static STM32_GATE(ck_ker_ospi2, &ck_flexgen_49, 0, GATE_OSPI2); 2704 static STM32_GATE(ck_icn_p_fmc, &ck_icn_ls_mcu, 0, GATE_FMC); 2705 static STM32_GATE(ck_ker_fmc, &ck_flexgen_50, 0, GATE_FMC); 2706 2707 /* Kernel Clocks */ 2708 static STM32_GATE(ck_icn_p_cci, &ck_icn_ls_mcu, 0, GATE_CCI); 2709 static STM32_GATE(ck_icn_p_crc, &ck_icn_ls_mcu, 0, GATE_CRC); 2710 static STM32_GATE(ck_icn_p_ospiiom, &ck_icn_ls_mcu, 0, GATE_OSPIIOM); 2711 static STM32_GATE(ck_icn_p_hash, &ck_icn_ls_mcu, 0, GATE_HASH); 2712 static STM32_GATE(ck_icn_p_rng, &ck_icn_ls_mcu, 0, GATE_RNG); 2713 static STM32_GATE(ck_icn_p_cryp1, &ck_icn_ls_mcu, 0, GATE_CRYP1); 2714 static STM32_GATE(ck_icn_p_cryp2, &ck_icn_ls_mcu, 0, GATE_CRYP2); 2715 static STM32_GATE(ck_icn_p_saes, &ck_icn_ls_mcu, 0, GATE_SAES); 2716 static STM32_GATE(ck_icn_p_pka, &ck_icn_ls_mcu, 0, GATE_PKA); 2717 static STM32_GATE(ck_icn_p_adf1, &ck_icn_ls_mcu, 0, GATE_ADF1); 2718 static STM32_GATE(ck_icn_p_iwdg5, &ck_icn_ls_mcu, 0, GATE_IWDG5); 2719 static STM32_GATE(ck_icn_p_wwdg2, &ck_icn_ls_mcu, 0, GATE_WWDG2); 2720 static STM32_GATE(ck_icn_p_eth1, &ck_icn_ls_mcu, 0, GATE_ETH1); 2721 static STM32_GATE(ck_icn_p_ethsw, &ck_icn_ls_mcu, 0, GATE_ETHSWMAC); 2722 static STM32_GATE(ck_icn_p_eth2, &ck_icn_ls_mcu, 0, GATE_ETH2); 2723 static STM32_GATE(ck_icn_p_pcie, &ck_icn_ls_mcu, 0, GATE_PCIE); 2724 static STM32_GATE(ck_icn_p_adc12, &ck_icn_ls_mcu, 0, GATE_ADC12); 2725 static STM32_GATE(ck_icn_p_adc3, &ck_icn_ls_mcu, 0, GATE_ADC3); 2726 static STM32_GATE(ck_icn_p_mdf1, &ck_icn_ls_mcu, 0, GATE_MDF1); 2727 static STM32_GATE(ck_icn_p_spi8, &ck_icn_ls_mcu, 0, GATE_SPI8); 2728 static STM32_GATE(ck_icn_p_lpuart1, &ck_icn_ls_mcu, 0, GATE_LPUART1); 2729 static STM32_GATE(ck_icn_p_i2c8, &ck_icn_ls_mcu, 0, GATE_I2C8); 2730 static STM32_GATE(ck_icn_p_lptim3, &ck_icn_ls_mcu, 0, GATE_LPTIM3); 2731 static STM32_GATE(ck_icn_p_lptim4, &ck_icn_ls_mcu, 0, GATE_LPTIM4); 2732 static STM32_GATE(ck_icn_p_lptim5, &ck_icn_ls_mcu, 0, GATE_LPTIM5); 2733 static STM32_GATE(ck_icn_m_sdmmc1, &ck_icn_sdmmc, 0, GATE_SDMMC1); 2734 static STM32_GATE(ck_icn_m_sdmmc2, &ck_icn_sdmmc, 0, GATE_SDMMC2); 2735 static STM32_GATE(ck_icn_m_sdmmc3, &ck_icn_sdmmc, 0, GATE_SDMMC3); 2736 static STM32_GATE(ck_icn_m_usb2ohci, &ck_icn_hsl, 0, GATE_USB2); 2737 static STM32_GATE(ck_icn_m_usb2ehci, &ck_icn_hsl, 0, GATE_USB2); 2738 static STM32_GATE(ck_icn_m_usb3dr, &ck_icn_hsl, 0, GATE_USB3DR); 2739 2740 static STM32_GATE(ck_icn_p_tim2, &ck_icn_apb1, 0, GATE_TIM2); 2741 static STM32_GATE(ck_icn_p_tim3, &ck_icn_apb1, 0, GATE_TIM3); 2742 static STM32_GATE(ck_icn_p_tim4, &ck_icn_apb1, 0, GATE_TIM4); 2743 static STM32_GATE(ck_icn_p_tim5, &ck_icn_apb1, 0, GATE_TIM5); 2744 static STM32_GATE(ck_icn_p_tim6, &ck_icn_apb1, 0, GATE_TIM6); 2745 static STM32_GATE(ck_icn_p_tim7, &ck_icn_apb1, 0, GATE_TIM7); 2746 static STM32_GATE(ck_icn_p_tim10, &ck_icn_apb1, 0, GATE_TIM10); 2747 static STM32_GATE(ck_icn_p_tim11, &ck_icn_apb1, 0, GATE_TIM11); 2748 static STM32_GATE(ck_icn_p_tim12, &ck_icn_apb1, 0, GATE_TIM12); 2749 static STM32_GATE(ck_icn_p_tim13, &ck_icn_apb1, 0, GATE_TIM13); 2750 static STM32_GATE(ck_icn_p_tim14, &ck_icn_apb1, 0, GATE_TIM14); 2751 static STM32_GATE(ck_icn_p_lptim1, &ck_icn_apb1, 0, GATE_LPTIM1); 2752 static STM32_GATE(ck_icn_p_lptim2, &ck_icn_apb1, 0, GATE_LPTIM2); 2753 static STM32_GATE(ck_icn_p_spi2, &ck_icn_apb1, 0, GATE_SPI2); 2754 static STM32_GATE(ck_icn_p_spi3, &ck_icn_apb1, 0, GATE_SPI3); 2755 static STM32_GATE(ck_icn_p_spdifrx, &ck_icn_apb1, 0, GATE_SPDIFRX); 2756 static STM32_GATE(ck_icn_p_usart2, &ck_icn_apb1, 0, GATE_USART2); 2757 static STM32_GATE(ck_icn_p_usart3, &ck_icn_apb1, 0, GATE_USART3); 2758 static STM32_GATE(ck_icn_p_uart4, &ck_icn_apb1, 0, GATE_UART4); 2759 static STM32_GATE(ck_icn_p_uart5, &ck_icn_apb1, 0, GATE_UART5); 2760 static STM32_GATE(ck_icn_p_i2c1, &ck_icn_apb1, 0, GATE_I2C1); 2761 static STM32_GATE(ck_icn_p_i2c2, &ck_icn_apb1, 0, GATE_I2C2); 2762 static STM32_GATE(ck_icn_p_i2c3, &ck_icn_apb1, 0, GATE_I2C3); 2763 static STM32_GATE(ck_icn_p_i2c4, &ck_icn_apb1, 0, GATE_I2C4); 2764 static STM32_GATE(ck_icn_p_i2c5, &ck_icn_apb1, 0, GATE_I2C5); 2765 static STM32_GATE(ck_icn_p_i2c6, &ck_icn_apb1, 0, GATE_I2C6); 2766 static STM32_GATE(ck_icn_p_i2c7, &ck_icn_apb1, 0, GATE_I2C7); 2767 static STM32_GATE(ck_icn_p_i3c1, &ck_icn_apb1, 0, GATE_I3C1); 2768 static STM32_GATE(ck_icn_p_i3c2, &ck_icn_apb1, 0, GATE_I3C2); 2769 static STM32_GATE(ck_icn_p_i3c3, &ck_icn_apb1, 0, GATE_I3C3); 2770 2771 static STM32_GATE(ck_icn_p_i3c4, &ck_icn_ls_mcu, 0, GATE_I3C4); 2772 2773 static STM32_GATE(ck_icn_p_tim1, &ck_icn_apb2, 0, GATE_TIM1); 2774 static STM32_GATE(ck_icn_p_tim8, &ck_icn_apb2, 0, GATE_TIM8); 2775 static STM32_GATE(ck_icn_p_tim15, &ck_icn_apb2, 0, GATE_TIM15); 2776 static STM32_GATE(ck_icn_p_tim16, &ck_icn_apb2, 0, GATE_TIM16); 2777 static STM32_GATE(ck_icn_p_tim17, &ck_icn_apb2, 0, GATE_TIM17); 2778 static STM32_GATE(ck_icn_p_tim20, &ck_icn_apb2, 0, GATE_TIM20); 2779 static STM32_GATE(ck_icn_p_sai1, &ck_icn_apb2, 0, GATE_SAI1); 2780 static STM32_GATE(ck_icn_p_sai2, &ck_icn_apb2, 0, GATE_SAI2); 2781 static STM32_GATE(ck_icn_p_sai3, &ck_icn_apb2, 0, GATE_SAI3); 2782 static STM32_GATE(ck_icn_p_sai4, &ck_icn_apb2, 0, GATE_SAI4); 2783 static STM32_GATE(ck_icn_p_usart1, &ck_icn_apb2, 0, GATE_USART1); 2784 static STM32_GATE(ck_icn_p_usart6, &ck_icn_apb2, 0, GATE_USART6); 2785 static STM32_GATE(ck_icn_p_uart7, &ck_icn_apb2, 0, GATE_UART7); 2786 static STM32_GATE(ck_icn_p_uart8, &ck_icn_apb2, 0, GATE_UART8); 2787 static STM32_GATE(ck_icn_p_uart9, &ck_icn_apb2, 0, GATE_UART9); 2788 static STM32_GATE(ck_icn_p_fdcan, &ck_icn_apb2, 0, GATE_FDCAN); 2789 static STM32_GATE(ck_icn_p_spi1, &ck_icn_apb2, 0, GATE_SPI1); 2790 static STM32_GATE(ck_icn_p_spi4, &ck_icn_apb2, 0, GATE_SPI4); 2791 static STM32_GATE(ck_icn_p_spi5, &ck_icn_apb2, 0, GATE_SPI5); 2792 static STM32_GATE(ck_icn_p_spi6, &ck_icn_apb2, 0, GATE_SPI6); 2793 static STM32_GATE(ck_icn_p_spi7, &ck_icn_apb2, 0, GATE_SPI7); 2794 static STM32_GATE(ck_icn_p_iwdg1, &ck_icn_apb3, 0, GATE_IWDG1); 2795 static STM32_GATE(ck_icn_p_iwdg2, &ck_icn_apb3, 0, GATE_IWDG2); 2796 static STM32_GATE(ck_icn_p_iwdg3, &ck_icn_apb3, 0, GATE_IWDG3); 2797 static STM32_GATE(ck_icn_p_iwdg4, &ck_icn_apb3, 0, GATE_IWDG4); 2798 static STM32_GATE(ck_icn_p_wwdg1, &ck_icn_apb3, 0, GATE_WWDG1); 2799 static STM32_GATE(ck_icn_p_vref, &ck_icn_apb3, 0, GATE_VREF); 2800 static STM32_GATE(ck_icn_p_dts, &ck_icn_apb3, 0, GATE_DTS); 2801 static STM32_GATE(ck_icn_p_serc, &ck_icn_apb3, 0, GATE_SERC); 2802 static STM32_GATE(ck_icn_p_hdp, &ck_icn_apb3, 0, GATE_HDP); 2803 static STM32_GATE(ck_icn_p_dsi, &ck_icn_apb4, 0, GATE_DSI); 2804 static STM32_GATE(ck_icn_p_ltdc, &ck_icn_apb4, 0, GATE_LTDC); 2805 static STM32_GATE(ck_icn_p_csi, &ck_icn_apb4, 0, GATE_CSI); 2806 static STM32_GATE(ck_icn_p_dcmipp, &ck_icn_apb4, 0, GATE_DCMIPP); 2807 static STM32_GATE(ck_icn_p_lvds, &ck_icn_apb4, 0, GATE_LVDS); 2808 static STM32_GATE(ck_icn_p_gicv2m, &ck_icn_apb4, 0, GATE_GICV2M); 2809 static STM32_GATE(ck_icn_p_usbtc, &ck_icn_apb4, 0, GATE_USBTC); 2810 static STM32_GATE(ck_icn_p_usb3pciephy, &ck_icn_apb4, 0, GATE_USB3PCIEPHY); 2811 static STM32_GATE(ck_icn_p_stgen, &ck_icn_apb4, 0, GATE_STGEN); 2812 static STM32_GATE(ck_icn_p_vdec, &ck_icn_apb4, 0, GATE_VDEC); 2813 static STM32_GATE(ck_icn_p_venc, &ck_icn_apb4, 0, GATE_VENC); 2814 2815 static STM32_GATE(ck_ker_tim2, &ck_timg1, 0, GATE_TIM2); 2816 static STM32_GATE(ck_ker_tim3, &ck_timg1, 0, GATE_TIM3); 2817 static STM32_GATE(ck_ker_tim4, &ck_timg1, 0, GATE_TIM4); 2818 static STM32_GATE(ck_ker_tim5, &ck_timg1, 0, GATE_TIM5); 2819 static STM32_GATE(ck_ker_tim6, &ck_timg1, 0, GATE_TIM6); 2820 static STM32_GATE(ck_ker_tim7, &ck_timg1, 0, GATE_TIM7); 2821 static STM32_GATE(ck_ker_tim10, &ck_timg1, 0, GATE_TIM10); 2822 static STM32_GATE(ck_ker_tim11, &ck_timg1, 0, GATE_TIM11); 2823 static STM32_GATE(ck_ker_tim12, &ck_timg1, 0, GATE_TIM12); 2824 static STM32_GATE(ck_ker_tim13, &ck_timg1, 0, GATE_TIM13); 2825 static STM32_GATE(ck_ker_tim14, &ck_timg1, 0, GATE_TIM14); 2826 static STM32_GATE(ck_ker_tim1, &ck_timg2, 0, GATE_TIM1); 2827 static STM32_GATE(ck_ker_tim8, &ck_timg2, 0, GATE_TIM8); 2828 static STM32_GATE(ck_ker_tim15, &ck_timg2, 0, GATE_TIM15); 2829 static STM32_GATE(ck_ker_tim16, &ck_timg2, 0, GATE_TIM16); 2830 static STM32_GATE(ck_ker_tim17, &ck_timg2, 0, GATE_TIM17); 2831 static STM32_GATE(ck_ker_tim20, &ck_timg2, 0, GATE_TIM20); 2832 static STM32_GATE(ck_ker_lptim1, &ck_flexgen_07, 0, GATE_LPTIM1); 2833 static STM32_GATE(ck_ker_lptim2, &ck_flexgen_07, 0, GATE_LPTIM2); 2834 static STM32_GATE(ck_ker_usart2, &ck_flexgen_08, 0, GATE_USART2); 2835 static STM32_GATE(ck_ker_uart4, &ck_flexgen_08, 0, GATE_UART4); 2836 static STM32_GATE(ck_ker_usart3, &ck_flexgen_09, 0, GATE_USART3); 2837 static STM32_GATE(ck_ker_uart5, &ck_flexgen_09, 0, GATE_UART5); 2838 static STM32_GATE(ck_ker_spi2, &ck_flexgen_10, 0, GATE_SPI2); 2839 static STM32_GATE(ck_ker_spi3, &ck_flexgen_10, 0, GATE_SPI3); 2840 static STM32_GATE(ck_ker_spdifrx, &ck_flexgen_11, 0, GATE_SPDIFRX); 2841 static STM32_GATE(ck_ker_i2c1, &ck_flexgen_12, 0, GATE_I2C1); 2842 static STM32_GATE(ck_ker_i2c2, &ck_flexgen_12, 0, GATE_I2C2); 2843 static STM32_GATE(ck_ker_i3c1, &ck_flexgen_12, 0, GATE_I3C1); 2844 static STM32_GATE(ck_ker_i3c2, &ck_flexgen_12, 0, GATE_I3C2); 2845 static STM32_GATE(ck_ker_i2c3, &ck_flexgen_13, 0, GATE_I2C3); 2846 static STM32_GATE(ck_ker_i2c5, &ck_flexgen_13, 0, GATE_I2C5); 2847 static STM32_GATE(ck_ker_i3c3, &ck_flexgen_13, 0, GATE_I3C3); 2848 static STM32_GATE(ck_ker_i2c4, &ck_flexgen_14, 0, GATE_I2C4); 2849 static STM32_GATE(ck_ker_i2c6, &ck_flexgen_14, 0, GATE_I2C6); 2850 static STM32_GATE(ck_ker_i2c7, &ck_flexgen_15, 0, GATE_I2C7); 2851 static STM32_GATE(ck_ker_spi1, &ck_flexgen_16, 0, GATE_SPI1); 2852 static STM32_GATE(ck_ker_spi4, &ck_flexgen_17, 0, GATE_SPI4); 2853 static STM32_GATE(ck_ker_spi5, &ck_flexgen_17, 0, GATE_SPI5); 2854 static STM32_GATE(ck_ker_spi6, &ck_flexgen_18, 0, GATE_SPI6); 2855 static STM32_GATE(ck_ker_spi7, &ck_flexgen_18, 0, GATE_SPI7); 2856 static STM32_GATE(ck_ker_usart1, &ck_flexgen_19, 0, GATE_USART1); 2857 static STM32_GATE(ck_ker_usart6, &ck_flexgen_20, 0, GATE_USART6); 2858 static STM32_GATE(ck_ker_uart7, &ck_flexgen_21, 0, GATE_UART7); 2859 static STM32_GATE(ck_ker_uart8, &ck_flexgen_21, 0, GATE_UART8); 2860 static STM32_GATE(ck_ker_uart9, &ck_flexgen_22, 0, GATE_UART9); 2861 static STM32_GATE(ck_ker_mdf1, &ck_flexgen_23, 0, GATE_MDF1); 2862 static STM32_GATE(ck_ker_sai1, &ck_flexgen_23, 0, GATE_SAI1); 2863 static STM32_GATE(ck_ker_sai2, &ck_flexgen_24, 0, GATE_SAI2); 2864 static STM32_GATE(ck_ker_sai3, &ck_flexgen_25, 0, GATE_SAI3); 2865 static STM32_GATE(ck_ker_sai4, &ck_flexgen_25, 0, GATE_SAI4); 2866 static STM32_GATE(ck_ker_fdcan, &ck_flexgen_26, 0, GATE_FDCAN); 2867 static STM32_GATE(ck_ker_csi, &ck_flexgen_29, 0, GATE_CSI); 2868 static STM32_GATE(ck_ker_csitxesc, &ck_flexgen_30, 0, GATE_CSI); 2869 static STM32_GATE(ck_ker_csiphy, &ck_flexgen_31, 0, GATE_CSI); 2870 static STM32_GATE(ck_ker_stgen, &ck_flexgen_33, CLK_SET_RATE_PARENT, 2871 GATE_STGEN); 2872 static STM32_GATE(ck_ker_usbtc, &ck_flexgen_35, 0, GATE_USBTC); 2873 static STM32_GATE(ck_ker_i3c4, &ck_flexgen_36, 0, GATE_I3C4); 2874 static STM32_GATE(ck_ker_spi8, &ck_flexgen_37, 0, GATE_SPI8); 2875 static STM32_GATE(ck_ker_i2c8, &ck_flexgen_38, 0, GATE_I2C8); 2876 static STM32_GATE(ck_ker_lpuart1, &ck_flexgen_39, 0, GATE_LPUART1); 2877 static STM32_GATE(ck_ker_lptim3, &ck_flexgen_40, 0, GATE_LPTIM3); 2878 static STM32_GATE(ck_ker_lptim4, &ck_flexgen_41, 0, GATE_LPTIM4); 2879 static STM32_GATE(ck_ker_lptim5, &ck_flexgen_41, 0, GATE_LPTIM5); 2880 static STM32_GATE(ck_ker_adf1, &ck_flexgen_42, 0, GATE_ADF1); 2881 static STM32_GATE(ck_ker_sdmmc1, &ck_flexgen_51, 0, GATE_SDMMC1); 2882 static STM32_GATE(ck_ker_sdmmc2, &ck_flexgen_52, 0, GATE_SDMMC2); 2883 static STM32_GATE(ck_ker_sdmmc3, &ck_flexgen_53, 0, GATE_SDMMC3); 2884 static STM32_GATE(ck_ker_eth1, &ck_flexgen_54, 0, GATE_ETH1); 2885 static STM32_GATE(ck_ker_ethsw, &ck_flexgen_54, 0, GATE_ETHSW); 2886 static STM32_GATE(ck_ker_eth2, &ck_flexgen_55, 0, GATE_ETH2); 2887 static STM32_GATE(ck_ker_eth1ptp, &ck_flexgen_56, 0, GATE_ETH1); 2888 static STM32_GATE(ck_ker_eth2ptp, &ck_flexgen_56, 0, GATE_ETH2); 2889 static STM32_GATE(ck_ker_usb2phy2, &ck_flexgen_58, 0, GATE_USB3DR); 2890 static STM32_GATE(ck_icn_m_gpu, &ck_flexgen_59, 0, GATE_GPU); 2891 static STM32_GATE(ck_ker_gpu, &ck_pll3, 0, GATE_GPU); 2892 static STM32_GATE(ck_ker_ethswref, &ck_flexgen_60, 0, GATE_ETHSWREF); 2893 2894 static STM32_GATE(ck_ker_eth1stp, &ck_icn_ls_mcu, 0, GATE_ETH1STP); 2895 static STM32_GATE(ck_ker_eth2stp, &ck_icn_ls_mcu, 0, GATE_ETH2STP); 2896 2897 static STM32_GATE(ck_ker_ltdc, &ck_flexgen_27, CLK_SET_RATE_PARENT, 2898 GATE_LTDC); 2899 2900 static STM32_COMPOSITE(ck_ker_adc12, 2, PARENT(&ck_flexgen_46, &ck_icn_ls_mcu), 2901 0, GATE_ADC12, NO_DIV, MUX_ADC12); 2902 2903 static STM32_COMPOSITE(ck_ker_adc3, 3, PARENT(&ck_flexgen_47, &ck_icn_ls_mcu, 2904 &ck_flexgen_46), 2905 0, GATE_ADC3, NO_DIV, MUX_ADC3); 2906 2907 static STM32_COMPOSITE(ck_ker_usb2phy1, 2, PARENT(&ck_flexgen_57, 2908 &ck_hse_div2), 2909 0, GATE_USB2PHY1, NO_DIV, MUX_USB2PHY1); 2910 2911 static STM32_COMPOSITE(ck_ker_usb2phy2_en, 2, PARENT(&ck_flexgen_58, 2912 &ck_hse_div2), 2913 0, GATE_USB2PHY2, NO_DIV, MUX_USB2PHY2); 2914 2915 static STM32_COMPOSITE(ck_ker_usb3pciephy, 2, PARENT(&ck_flexgen_34, 2916 &ck_hse_div2), 2917 0, GATE_USB3PCIEPHY, NO_DIV, MUX_USB3PCIEPHY); 2918 2919 static STM32_COMPOSITE(clk_lanebyte, 2, PARENT(&txbyteclk, &ck_ker_ltdc), 2920 0, GATE_DSI, NO_DIV, MUX_DSIBLANE); 2921 2922 static STM32_COMPOSITE(ck_phy_dsi, 2, PARENT(&ck_flexgen_28, &ck_hse), 2923 0, GATE_DSI, NO_DIV, MUX_DSIPHY); 2924 2925 static STM32_COMPOSITE(ck_ker_lvdsphy, 2, PARENT(&ck_flexgen_32, &ck_hse), 2926 0, GATE_LVDS, NO_DIV, MUX_LVDSPHY); 2927 2928 static STM32_COMPOSITE(ck_ker_dts, 3, PARENT(&ck_hsi, &ck_hse, &ck_msi), 2929 0, GATE_DTS, NO_DIV, MUX_DTS); 2930 2931 enum { 2932 CK_OFF = STM32MP25_LAST_CLK, 2933 I2SCKIN, 2934 SPDIFSYMB, 2935 CK_HSE_RTC, 2936 TXBYTECLK, 2937 CK_OBSER0, 2938 CK_OBSER1, 2939 STM32MP25_ALL_CLK_NB 2940 }; 2941 2942 static STM32_GATE(ck_ker_eth1mac, &ck_icn_ls_mcu, 0, GATE_ETH1MAC); 2943 static STM32_GATE(ck_ker_eth1tx, &ck_icn_ls_mcu, 0, GATE_ETH1TX); 2944 static STM32_GATE(ck_ker_eth1rx, &ck_icn_ls_mcu, 0, GATE_ETH1RX); 2945 static STM32_GATE(ck_ker_eth2mac, &ck_icn_ls_mcu, 0, GATE_ETH2MAC); 2946 static STM32_GATE(ck_ker_eth2tx, &ck_icn_ls_mcu, 0, GATE_ETH2TX); 2947 static STM32_GATE(ck_ker_eth2rx, &ck_icn_ls_mcu, 0, GATE_ETH2RX); 2948 2949 static struct clk *stm32mp25_clk_provided[STM32MP25_ALL_CLK_NB] = { 2950 [HSI_CK] = &ck_hsi, 2951 [HSE_CK] = &ck_hse, 2952 [MSI_CK] = &ck_msi, 2953 [LSI_CK] = &ck_lsi, 2954 [LSE_CK] = &ck_lse, 2955 2956 [HSE_DIV2_CK] = &ck_hse_div2, 2957 2958 [PLL1_CK] = &ck_pll1, 2959 [PLL2_CK] = &ck_pll2, 2960 [PLL3_CK] = &ck_pll3, 2961 [PLL4_CK] = &ck_pll4, 2962 [PLL5_CK] = &ck_pll5, 2963 [PLL6_CK] = &ck_pll6, 2964 [PLL7_CK] = &ck_pll7, 2965 [PLL8_CK] = &ck_pll8, 2966 2967 [CK_ICN_HS_MCU] = &ck_icn_hs_mcu, 2968 [CK_ICN_LS_MCU] = &ck_icn_ls_mcu, 2969 2970 [CK_ICN_SDMMC] = &ck_icn_sdmmc, 2971 [CK_ICN_DDR] = &ck_icn_ddr, 2972 [CK_ICN_DISPLAY] = &ck_icn_display, 2973 [CK_ICN_HSL] = &ck_icn_hsl, 2974 [CK_ICN_NIC] = &ck_icn_nic, 2975 [CK_ICN_VID] = &ck_icn_vid, 2976 [CK_FLEXGEN_07] = &ck_flexgen_07, 2977 [CK_FLEXGEN_08] = &ck_flexgen_08, 2978 [CK_FLEXGEN_09] = &ck_flexgen_09, 2979 [CK_FLEXGEN_10] = &ck_flexgen_10, 2980 [CK_FLEXGEN_11] = &ck_flexgen_11, 2981 [CK_FLEXGEN_12] = &ck_flexgen_12, 2982 [CK_FLEXGEN_13] = &ck_flexgen_13, 2983 [CK_FLEXGEN_14] = &ck_flexgen_14, 2984 [CK_FLEXGEN_15] = &ck_flexgen_15, 2985 [CK_FLEXGEN_16] = &ck_flexgen_16, 2986 [CK_FLEXGEN_17] = &ck_flexgen_17, 2987 [CK_FLEXGEN_18] = &ck_flexgen_18, 2988 [CK_FLEXGEN_19] = &ck_flexgen_19, 2989 [CK_FLEXGEN_20] = &ck_flexgen_20, 2990 [CK_FLEXGEN_21] = &ck_flexgen_21, 2991 [CK_FLEXGEN_22] = &ck_flexgen_22, 2992 [CK_FLEXGEN_23] = &ck_flexgen_23, 2993 [CK_FLEXGEN_24] = &ck_flexgen_24, 2994 [CK_FLEXGEN_25] = &ck_flexgen_25, 2995 [CK_FLEXGEN_26] = &ck_flexgen_26, 2996 [CK_FLEXGEN_27] = &ck_flexgen_27, 2997 [CK_FLEXGEN_28] = &ck_flexgen_28, 2998 [CK_FLEXGEN_29] = &ck_flexgen_29, 2999 [CK_FLEXGEN_30] = &ck_flexgen_30, 3000 [CK_FLEXGEN_31] = &ck_flexgen_31, 3001 [CK_FLEXGEN_32] = &ck_flexgen_32, 3002 [CK_FLEXGEN_33] = &ck_flexgen_33, 3003 [CK_FLEXGEN_34] = &ck_flexgen_34, 3004 [CK_FLEXGEN_35] = &ck_flexgen_35, 3005 [CK_FLEXGEN_36] = &ck_flexgen_36, 3006 [CK_FLEXGEN_37] = &ck_flexgen_37, 3007 [CK_FLEXGEN_38] = &ck_flexgen_38, 3008 [CK_FLEXGEN_39] = &ck_flexgen_39, 3009 [CK_FLEXGEN_40] = &ck_flexgen_40, 3010 [CK_FLEXGEN_41] = &ck_flexgen_41, 3011 [CK_FLEXGEN_42] = &ck_flexgen_42, 3012 [CK_FLEXGEN_43] = &ck_flexgen_43, 3013 [CK_FLEXGEN_44] = &ck_flexgen_44, 3014 [CK_FLEXGEN_45] = &ck_flexgen_45, 3015 [CK_FLEXGEN_46] = &ck_flexgen_46, 3016 [CK_FLEXGEN_47] = &ck_flexgen_47, 3017 [CK_FLEXGEN_48] = &ck_flexgen_48, 3018 [CK_FLEXGEN_49] = &ck_flexgen_49, 3019 [CK_FLEXGEN_50] = &ck_flexgen_50, 3020 [CK_FLEXGEN_51] = &ck_flexgen_51, 3021 [CK_FLEXGEN_52] = &ck_flexgen_52, 3022 [CK_FLEXGEN_53] = &ck_flexgen_53, 3023 [CK_FLEXGEN_54] = &ck_flexgen_54, 3024 [CK_FLEXGEN_55] = &ck_flexgen_55, 3025 [CK_FLEXGEN_56] = &ck_flexgen_56, 3026 [CK_FLEXGEN_57] = &ck_flexgen_57, 3027 [CK_FLEXGEN_58] = &ck_flexgen_58, 3028 [CK_FLEXGEN_59] = &ck_flexgen_59, 3029 [CK_FLEXGEN_60] = &ck_flexgen_60, 3030 [CK_FLEXGEN_61] = &ck_flexgen_61, 3031 [CK_FLEXGEN_62] = &ck_flexgen_62, 3032 [CK_FLEXGEN_63] = &ck_flexgen_63, 3033 3034 [CK_CPU1] = &ck_cpu1, 3035 3036 [CK_ICN_APB1] = &ck_icn_apb1, 3037 [CK_ICN_APB2] = &ck_icn_apb2, 3038 [CK_ICN_APB3] = &ck_icn_apb3, 3039 [CK_ICN_APB4] = &ck_icn_apb4, 3040 [CK_ICN_APBDBG] = &ck_icn_apbdbg, 3041 3042 [TIMG1_CK] = &ck_timg1, 3043 [TIMG2_CK] = &ck_timg2, 3044 3045 [CK_BUS_SYSRAM] = &ck_icn_s_sysram, 3046 [CK_BUS_VDERAM] = &ck_icn_s_vderam, 3047 [CK_BUS_RETRAM] = &ck_icn_s_retram, 3048 [CK_BUS_SRAM1] = &ck_icn_s_sram1, 3049 [CK_BUS_SRAM2] = &ck_icn_s_sram2, 3050 [CK_BUS_OSPI1] = &ck_icn_s_ospi1, 3051 [CK_BUS_OSPI2] = &ck_icn_s_ospi2, 3052 [CK_BUS_BKPSRAM] = &ck_icn_s_bkpsram, 3053 [CK_BUS_DDRPHYC] = &ck_icn_p_ddrphyc, 3054 [CK_BUS_SYSCPU1] = &ck_icn_p_syscpu1, 3055 [CK_BUS_HPDMA1] = &ck_icn_p_hpdma1, 3056 [CK_BUS_HPDMA2] = &ck_icn_p_hpdma2, 3057 [CK_BUS_HPDMA3] = &ck_icn_p_hpdma3, 3058 [CK_BUS_IPCC1] = &ck_icn_p_ipcc1, 3059 [CK_BUS_IPCC2] = &ck_icn_p_ipcc2, 3060 [CK_BUS_CCI] = &ck_icn_p_cci, 3061 [CK_BUS_CRC] = &ck_icn_p_crc, 3062 [CK_BUS_OSPIIOM] = &ck_icn_p_ospiiom, 3063 [CK_BUS_HASH] = &ck_icn_p_hash, 3064 [CK_BUS_RNG] = &ck_icn_p_rng, 3065 [CK_BUS_CRYP1] = &ck_icn_p_cryp1, 3066 [CK_BUS_CRYP2] = &ck_icn_p_cryp2, 3067 [CK_BUS_SAES] = &ck_icn_p_saes, 3068 [CK_BUS_PKA] = &ck_icn_p_pka, 3069 [CK_BUS_GPIOA] = &ck_icn_p_gpioa, 3070 [CK_BUS_GPIOB] = &ck_icn_p_gpiob, 3071 [CK_BUS_GPIOC] = &ck_icn_p_gpioc, 3072 [CK_BUS_GPIOD] = &ck_icn_p_gpiod, 3073 [CK_BUS_GPIOE] = &ck_icn_p_gpioe, 3074 [CK_BUS_GPIOF] = &ck_icn_p_gpiof, 3075 [CK_BUS_GPIOG] = &ck_icn_p_gpiog, 3076 [CK_BUS_GPIOH] = &ck_icn_p_gpioh, 3077 [CK_BUS_GPIOI] = &ck_icn_p_gpioi, 3078 [CK_BUS_GPIOJ] = &ck_icn_p_gpioj, 3079 [CK_BUS_GPIOK] = &ck_icn_p_gpiok, 3080 [CK_BUS_LPSRAM1] = &ck_icn_s_lpsram1, 3081 [CK_BUS_LPSRAM2] = &ck_icn_s_lpsram2, 3082 [CK_BUS_LPSRAM3] = &ck_icn_s_lpsram3, 3083 [CK_BUS_GPIOZ] = &ck_icn_p_gpioz, 3084 [CK_BUS_LPDMA] = &ck_icn_p_lpdma, 3085 [CK_BUS_ADF1] = &ck_icn_p_adf1, 3086 [CK_BUS_HSEM] = &ck_icn_p_hsem, 3087 [CK_BUS_RTC] = &ck_icn_p_rtc, 3088 [CK_BUS_IWDG5] = &ck_icn_p_iwdg5, 3089 [CK_BUS_WWDG2] = &ck_icn_p_wwdg2, 3090 [CK_BUS_STM] = &ck_icn_p_stm, 3091 [CK_KER_STM] = &ck_icn_s_stm, 3092 [CK_BUS_FMC] = &ck_icn_p_fmc, 3093 [CK_BUS_ETH1] = &ck_icn_p_eth1, 3094 [CK_BUS_ETHSW] = &ck_icn_p_ethsw, 3095 [CK_BUS_ETH2] = &ck_icn_p_eth2, 3096 [CK_BUS_PCIE] = &ck_icn_p_pcie, 3097 [CK_BUS_ADC12] = &ck_icn_p_adc12, 3098 [CK_BUS_ADC3] = &ck_icn_p_adc3, 3099 [CK_BUS_MDF1] = &ck_icn_p_mdf1, 3100 [CK_BUS_SPI8] = &ck_icn_p_spi8, 3101 [CK_BUS_LPUART1] = &ck_icn_p_lpuart1, 3102 [CK_BUS_I2C8] = &ck_icn_p_i2c8, 3103 [CK_BUS_LPTIM3] = &ck_icn_p_lptim3, 3104 [CK_BUS_LPTIM4] = &ck_icn_p_lptim4, 3105 [CK_BUS_LPTIM5] = &ck_icn_p_lptim5, 3106 [CK_BUS_RISAF4] = &ck_icn_p_risaf4, 3107 [CK_BUS_SDMMC1] = &ck_icn_m_sdmmc1, 3108 [CK_BUS_SDMMC2] = &ck_icn_m_sdmmc2, 3109 [CK_BUS_SDMMC3] = &ck_icn_m_sdmmc3, 3110 [CK_BUS_DDR] = &ck_icn_s_ddr, 3111 [CK_BUS_USB2OHCI] = &ck_icn_m_usb2ohci, 3112 [CK_BUS_USB2EHCI] = &ck_icn_m_usb2ehci, 3113 [CK_BUS_USB3DR] = &ck_icn_m_usb3dr, 3114 [CK_BUS_TIM2] = &ck_icn_p_tim2, 3115 [CK_BUS_TIM3] = &ck_icn_p_tim3, 3116 [CK_BUS_TIM4] = &ck_icn_p_tim4, 3117 [CK_BUS_TIM5] = &ck_icn_p_tim5, 3118 [CK_BUS_TIM6] = &ck_icn_p_tim6, 3119 [CK_BUS_TIM7] = &ck_icn_p_tim7, 3120 [CK_BUS_TIM10] = &ck_icn_p_tim10, 3121 [CK_BUS_TIM11] = &ck_icn_p_tim11, 3122 [CK_BUS_TIM12] = &ck_icn_p_tim12, 3123 [CK_BUS_TIM13] = &ck_icn_p_tim13, 3124 [CK_BUS_TIM14] = &ck_icn_p_tim14, 3125 [CK_BUS_LPTIM1] = &ck_icn_p_lptim1, 3126 [CK_BUS_LPTIM2] = &ck_icn_p_lptim2, 3127 [CK_BUS_SPI2] = &ck_icn_p_spi2, 3128 [CK_BUS_SPI3] = &ck_icn_p_spi3, 3129 [CK_BUS_SPDIFRX] = &ck_icn_p_spdifrx, 3130 [CK_BUS_USART2] = &ck_icn_p_usart2, 3131 [CK_BUS_USART3] = &ck_icn_p_usart3, 3132 [CK_BUS_UART4] = &ck_icn_p_uart4, 3133 [CK_BUS_UART5] = &ck_icn_p_uart5, 3134 [CK_BUS_I2C1] = &ck_icn_p_i2c1, 3135 [CK_BUS_I2C2] = &ck_icn_p_i2c2, 3136 [CK_BUS_I2C3] = &ck_icn_p_i2c3, 3137 [CK_BUS_I2C4] = &ck_icn_p_i2c4, 3138 [CK_BUS_I2C5] = &ck_icn_p_i2c5, 3139 [CK_BUS_I2C6] = &ck_icn_p_i2c6, 3140 [CK_BUS_I2C7] = &ck_icn_p_i2c7, 3141 [CK_BUS_I3C1] = &ck_icn_p_i3c1, 3142 [CK_BUS_I3C2] = &ck_icn_p_i3c2, 3143 [CK_BUS_I3C3] = &ck_icn_p_i3c3, 3144 [CK_BUS_I3C4] = &ck_icn_p_i3c4, 3145 [CK_BUS_TIM1] = &ck_icn_p_tim1, 3146 [CK_BUS_TIM8] = &ck_icn_p_tim8, 3147 [CK_BUS_TIM15] = &ck_icn_p_tim15, 3148 [CK_BUS_TIM16] = &ck_icn_p_tim16, 3149 [CK_BUS_TIM17] = &ck_icn_p_tim17, 3150 [CK_BUS_TIM20] = &ck_icn_p_tim20, 3151 [CK_BUS_SAI1] = &ck_icn_p_sai1, 3152 [CK_BUS_SAI2] = &ck_icn_p_sai2, 3153 [CK_BUS_SAI3] = &ck_icn_p_sai3, 3154 [CK_BUS_SAI4] = &ck_icn_p_sai4, 3155 [CK_BUS_USART1] = &ck_icn_p_usart1, 3156 [CK_BUS_USART6] = &ck_icn_p_usart6, 3157 [CK_BUS_UART7] = &ck_icn_p_uart7, 3158 [CK_BUS_UART8] = &ck_icn_p_uart8, 3159 [CK_BUS_UART9] = &ck_icn_p_uart9, 3160 [CK_BUS_FDCAN] = &ck_icn_p_fdcan, 3161 [CK_BUS_SPI1] = &ck_icn_p_spi1, 3162 [CK_BUS_SPI4] = &ck_icn_p_spi4, 3163 [CK_BUS_SPI5] = &ck_icn_p_spi5, 3164 [CK_BUS_SPI6] = &ck_icn_p_spi6, 3165 [CK_BUS_SPI7] = &ck_icn_p_spi7, 3166 [CK_BUS_BSEC] = &ck_icn_p_bsec, 3167 [CK_BUS_IWDG1] = &ck_icn_p_iwdg1, 3168 [CK_BUS_IWDG2] = &ck_icn_p_iwdg2, 3169 [CK_BUS_IWDG3] = &ck_icn_p_iwdg3, 3170 [CK_BUS_IWDG4] = &ck_icn_p_iwdg4, 3171 [CK_BUS_WWDG1] = &ck_icn_p_wwdg1, 3172 [CK_BUS_VREF] = &ck_icn_p_vref, 3173 [CK_BUS_SERC] = &ck_icn_p_serc, 3174 [CK_BUS_DTS] = &ck_icn_p_dts, 3175 [CK_BUS_HDP] = &ck_icn_p_hdp, 3176 [CK_BUS_IS2M] = &ck_icn_p_is2m, 3177 [CK_BUS_DSI] = &ck_icn_p_dsi, 3178 [CK_BUS_LTDC] = &ck_icn_p_ltdc, 3179 [CK_BUS_CSI] = &ck_icn_p_csi, 3180 [CK_BUS_DCMIPP] = &ck_icn_p_dcmipp, 3181 [CK_BUS_DDRC] = &ck_icn_p_ddrc, 3182 [CK_BUS_DDRCFG] = &ck_icn_p_ddrcfg, 3183 [CK_BUS_LVDS] = &ck_icn_p_lvds, 3184 [CK_BUS_GICV2M] = &ck_icn_p_gicv2m, 3185 [CK_BUS_USBTC] = &ck_icn_p_usbtc, 3186 [CK_BUS_USB3PCIEPHY] = &ck_icn_p_usb3pciephy, 3187 [CK_BUS_STGEN] = &ck_icn_p_stgen, 3188 [CK_BUS_VDEC] = &ck_icn_p_vdec, 3189 [CK_BUS_VENC] = &ck_icn_p_venc, 3190 [CK_SYSDBG] = &ck_sys_dbg, 3191 [CK_KER_TIM2] = &ck_ker_tim2, 3192 [CK_KER_TIM3] = &ck_ker_tim3, 3193 [CK_KER_TIM4] = &ck_ker_tim4, 3194 [CK_KER_TIM5] = &ck_ker_tim5, 3195 [CK_KER_TIM6] = &ck_ker_tim6, 3196 [CK_KER_TIM7] = &ck_ker_tim7, 3197 [CK_KER_TIM10] = &ck_ker_tim10, 3198 [CK_KER_TIM11] = &ck_ker_tim11, 3199 [CK_KER_TIM12] = &ck_ker_tim12, 3200 [CK_KER_TIM13] = &ck_ker_tim13, 3201 [CK_KER_TIM14] = &ck_ker_tim14, 3202 [CK_KER_TIM1] = &ck_ker_tim1, 3203 [CK_KER_TIM8] = &ck_ker_tim8, 3204 [CK_KER_TIM15] = &ck_ker_tim15, 3205 [CK_KER_TIM16] = &ck_ker_tim16, 3206 [CK_KER_TIM17] = &ck_ker_tim17, 3207 [CK_KER_TIM20] = &ck_ker_tim20, 3208 [CK_KER_LPTIM1] = &ck_ker_lptim1, 3209 [CK_KER_LPTIM2] = &ck_ker_lptim2, 3210 [CK_KER_USART2] = &ck_ker_usart2, 3211 [CK_KER_UART4] = &ck_ker_uart4, 3212 [CK_KER_USART3] = &ck_ker_usart3, 3213 [CK_KER_UART5] = &ck_ker_uart5, 3214 [CK_KER_SPI2] = &ck_ker_spi2, 3215 [CK_KER_SPI3] = &ck_ker_spi3, 3216 [CK_KER_SPDIFRX] = &ck_ker_spdifrx, 3217 [CK_KER_I2C1] = &ck_ker_i2c1, 3218 [CK_KER_I2C2] = &ck_ker_i2c2, 3219 [CK_KER_I3C1] = &ck_ker_i3c1, 3220 [CK_KER_I3C2] = &ck_ker_i3c2, 3221 [CK_KER_I2C3] = &ck_ker_i2c3, 3222 [CK_KER_I2C5] = &ck_ker_i2c5, 3223 [CK_KER_I3C3] = &ck_ker_i3c3, 3224 [CK_KER_I2C4] = &ck_ker_i2c4, 3225 [CK_KER_I2C6] = &ck_ker_i2c6, 3226 [CK_KER_I2C7] = &ck_ker_i2c7, 3227 [CK_KER_SPI1] = &ck_ker_spi1, 3228 [CK_KER_SPI4] = &ck_ker_spi4, 3229 [CK_KER_SPI5] = &ck_ker_spi5, 3230 [CK_KER_SPI6] = &ck_ker_spi6, 3231 [CK_KER_SPI7] = &ck_ker_spi7, 3232 [CK_KER_USART1] = &ck_ker_usart1, 3233 [CK_KER_USART6] = &ck_ker_usart6, 3234 [CK_KER_UART7] = &ck_ker_uart7, 3235 [CK_KER_UART8] = &ck_ker_uart8, 3236 [CK_KER_UART9] = &ck_ker_uart9, 3237 [CK_KER_MDF1] = &ck_ker_mdf1, 3238 [CK_KER_SAI1] = &ck_ker_sai1, 3239 [CK_KER_SAI2] = &ck_ker_sai2, 3240 [CK_KER_SAI3] = &ck_ker_sai3, 3241 [CK_KER_SAI4] = &ck_ker_sai4, 3242 [CK_KER_FDCAN] = &ck_ker_fdcan, 3243 [CK_KER_CSI] = &ck_ker_csi, 3244 [CK_KER_CSITXESC] = &ck_ker_csitxesc, 3245 [CK_KER_CSIPHY] = &ck_ker_csiphy, 3246 [CK_KER_STGEN] = &ck_ker_stgen, 3247 [CK_KER_USBTC] = &ck_ker_usbtc, 3248 [CK_KER_I3C4] = &ck_ker_i3c4, 3249 [CK_KER_SPI8] = &ck_ker_spi8, 3250 [CK_KER_I2C8] = &ck_ker_i2c8, 3251 [CK_KER_LPUART1] = &ck_ker_lpuart1, 3252 [CK_KER_LPTIM3] = &ck_ker_lptim3, 3253 [CK_KER_LPTIM4] = &ck_ker_lptim4, 3254 [CK_KER_LPTIM5] = &ck_ker_lptim5, 3255 [CK_KER_ADF1] = &ck_ker_adf1, 3256 [CK_KER_TSDBG] = &ck_ker_tsdbg, 3257 [CK_KER_TPIU] = &ck_ker_tpiu, 3258 [CK_BUS_ETR] = &ck_icn_p_etr, 3259 [CK_KER_ETR] = &ck_icn_m_etr, 3260 [CK_BUS_SYSATB] = &ck_sys_atb, 3261 [CK_KER_OSPI1] = &ck_ker_ospi1, 3262 [CK_KER_OSPI2] = &ck_ker_ospi2, 3263 [CK_KER_FMC] = &ck_ker_fmc, 3264 [CK_KER_SDMMC1] = &ck_ker_sdmmc1, 3265 [CK_KER_SDMMC2] = &ck_ker_sdmmc2, 3266 [CK_KER_SDMMC3] = &ck_ker_sdmmc3, 3267 [CK_KER_ETH1] = &ck_ker_eth1, 3268 [CK_ETH1_STP] = &ck_ker_eth1stp, 3269 [CK_KER_ETHSW] = &ck_ker_ethsw, 3270 [CK_KER_ETH2] = &ck_ker_eth2, 3271 [CK_ETH2_STP] = &ck_ker_eth2stp, 3272 [CK_KER_ETH1PTP] = &ck_ker_eth1ptp, 3273 [CK_KER_ETH2PTP] = &ck_ker_eth2ptp, 3274 [CK_BUS_GPU] = &ck_icn_m_gpu, 3275 [CK_KER_GPU] = &ck_ker_gpu, 3276 [CK_KER_ETHSWREF] = &ck_ker_ethswref, 3277 3278 [CK_MCO1] = &ck_mco1, 3279 [CK_MCO2] = &ck_mco2, 3280 [CK_KER_ADC12] = &ck_ker_adc12, 3281 [CK_KER_ADC3] = &ck_ker_adc3, 3282 [CK_KER_USB2PHY1] = &ck_ker_usb2phy1, 3283 [CK_KER_USB2PHY2] = &ck_ker_usb2phy2, 3284 [CK_KER_USB2PHY2EN] = &ck_ker_usb2phy2_en, 3285 [CK_KER_USB3PCIEPHY] = &ck_ker_usb3pciephy, 3286 [CK_KER_LTDC] = &ck_ker_ltdc, 3287 [CK_KER_DSIBLANE] = &clk_lanebyte, 3288 [CK_KER_DSIPHY] = &ck_phy_dsi, 3289 [CK_KER_LVDSPHY] = &ck_ker_lvdsphy, 3290 [CK_KER_DTS] = &ck_ker_dts, 3291 [RTC_CK] = &ck_rtc, 3292 3293 [CK_ETH1_MAC] = &ck_ker_eth1mac, 3294 [CK_ETH1_TX] = &ck_ker_eth1tx, 3295 [CK_ETH1_RX] = &ck_ker_eth1rx, 3296 [CK_ETH2_MAC] = &ck_ker_eth2mac, 3297 [CK_ETH2_TX] = &ck_ker_eth2tx, 3298 [CK_ETH2_RX] = &ck_ker_eth2rx, 3299 3300 [CK_HSE_RTC] = &ck_hse_rtc, 3301 [CK_OBSER0] = &ck_obser0, 3302 [CK_OBSER1] = &ck_obser1, 3303 [CK_OFF] = &ck_off, 3304 [I2SCKIN] = &i2sckin, 3305 [SPDIFSYMB] = &spdifsymb, 3306 [TXBYTECLK] = &txbyteclk, 3307 }; 3308 3309 static bool clk_stm32_clock_is_critical(struct clk *clk) 3310 { 3311 struct clk *clk_criticals[] = { 3312 &ck_hsi, 3313 &ck_hse, 3314 &ck_msi, 3315 &ck_lsi, 3316 &ck_lse, 3317 &ck_cpu1, 3318 &ck_icn_p_syscpu1, 3319 &ck_icn_s_ddr, 3320 &ck_icn_p_ddrc, 3321 &ck_icn_p_ddrcfg, 3322 &ck_icn_p_ddrphyc, 3323 &ck_icn_s_sysram, 3324 &ck_icn_s_bkpsram, 3325 &ck_ker_fmc, 3326 &ck_ker_ospi1, 3327 &ck_ker_ospi2, 3328 &ck_icn_s_vderam, 3329 &ck_icn_s_lpsram1, 3330 &ck_icn_s_lpsram2, 3331 &ck_icn_s_lpsram3, 3332 &ck_icn_p_hpdma1, 3333 &ck_icn_p_hpdma2, 3334 &ck_icn_p_hpdma3, 3335 &ck_icn_p_gpioa, 3336 &ck_icn_p_gpiob, 3337 &ck_icn_p_gpioc, 3338 &ck_icn_p_gpiod, 3339 &ck_icn_p_gpioe, 3340 &ck_icn_p_gpiof, 3341 &ck_icn_p_gpiog, 3342 &ck_icn_p_gpioh, 3343 &ck_icn_p_gpioi, 3344 &ck_icn_p_gpioj, 3345 &ck_icn_p_gpiok, 3346 &ck_icn_p_gpioz, 3347 &ck_icn_p_ipcc1, 3348 &ck_icn_p_ipcc2, 3349 &ck_icn_p_gicv2m, 3350 &ck_icn_p_rtc 3351 }; 3352 size_t i = 0; 3353 3354 for (i = 0; i < ARRAY_SIZE(clk_criticals); i++) 3355 if (clk == clk_criticals[i]) 3356 return true; 3357 return false; 3358 } 3359 3360 static void clk_stm32_init_oscillators(const void *fdt, int node) 3361 { 3362 size_t i = 0; 3363 static const char * const name[] = { 3364 "clk-hse", "clk-hsi", "clk-lse", 3365 "clk-lsi", "clk-msi", "clk-i2sin" 3366 }; 3367 struct clk *clks[ARRAY_SIZE(name)] = { 3368 &ck_hse, &ck_hsi, &ck_lse, 3369 &ck_lsi, &ck_msi, &i2sckin 3370 }; 3371 3372 for (i = 0; i < ARRAY_SIZE(clks); i++) { 3373 struct clk *clk = NULL; 3374 3375 if (clk_dt_get_by_name(fdt, node, name[i], &clk)) 3376 panic(); 3377 3378 clks[i]->parents[0] = clk; 3379 } 3380 } 3381 3382 static TEE_Result clk_stm32_apply_rcc_config(struct stm32_clk_platdata *pdata) 3383 { 3384 if (pdata->safe_rst) 3385 stm32mp25_syscfg_set_safe_reset(true); 3386 3387 return TEE_SUCCESS; 3388 } 3389 3390 static struct stm32_pll_dt_cfg mp25_pll[PLL_NB]; 3391 static struct stm32_clk_opp_dt_cfg mp25_clk_opp; 3392 static struct stm32_osci_dt_cfg mp25_osci[NB_OSCILLATOR]; 3393 3394 #define DT_FLEXGEN_CLK_MAX 64 3395 static uint32_t mp25_flexgen[DT_FLEXGEN_CLK_MAX]; 3396 3397 #define DT_BUS_CLK_MAX 6 3398 static uint32_t mp25_busclk[DT_BUS_CLK_MAX]; 3399 3400 #define DT_KERNEL_CLK_MAX 20 3401 static uint32_t mp25_kernelclk[DT_KERNEL_CLK_MAX]; 3402 3403 static struct stm32_clk_platdata stm32mp25_clock_pdata = { 3404 .osci = mp25_osci, 3405 .nosci = NB_OSCILLATOR, 3406 .pll = mp25_pll, 3407 .npll = PLL_NB, 3408 .opp = &mp25_clk_opp, 3409 .busclk = mp25_busclk, 3410 .nbusclk = DT_BUS_CLK_MAX, 3411 .kernelclk = mp25_kernelclk, 3412 .nkernelclk = DT_KERNEL_CLK_MAX, 3413 .flexgen = mp25_flexgen, 3414 .nflexgen = DT_FLEXGEN_CLK_MAX, 3415 }; 3416 3417 static struct clk_stm32_priv stm32mp25_clock_data = { 3418 .muxes = parent_mp25, 3419 .nb_muxes = ARRAY_SIZE(parent_mp25), 3420 .gates = gates_mp25, 3421 .nb_gates = ARRAY_SIZE(gates_mp25), 3422 .div = dividers_mp25, 3423 .nb_div = ARRAY_SIZE(dividers_mp25), 3424 .pdata = &stm32mp25_clock_pdata, 3425 .nb_clk_refs = STM32MP25_ALL_CLK_NB, 3426 .clk_refs = stm32mp25_clk_provided, 3427 .is_critical = clk_stm32_clock_is_critical, 3428 }; 3429 3430 static TEE_Result stm32mp2_clk_probe(const void *fdt, int node, 3431 const void *compat_data __unused) 3432 { 3433 TEE_Result res = TEE_ERROR_GENERIC; 3434 int fdt_rc = 0; 3435 int rc = 0; 3436 struct clk_stm32_priv *priv = &stm32mp25_clock_data; 3437 struct stm32_clk_platdata *pdata = &stm32mp25_clock_pdata; 3438 3439 fdt_rc = stm32_clk_parse_fdt(fdt, node, pdata); 3440 if (fdt_rc) { 3441 EMSG("Failed to parse clock node %s: %d", 3442 fdt_get_name(fdt, node, NULL), fdt_rc); 3443 return TEE_ERROR_GENERIC; 3444 } 3445 3446 rc = clk_stm32_init(priv, stm32_rcc_base()); 3447 if (rc) 3448 return TEE_ERROR_GENERIC; 3449 3450 stm32mp2_init_clock_tree(priv, pdata); 3451 3452 clk_stm32_init_oscillators(fdt, node); 3453 3454 res = clk_stm32_apply_rcc_config(pdata); 3455 if (res) 3456 panic("Error when applying RCC config"); 3457 3458 stm32mp_clk_provider_probe_final(fdt, node, priv); 3459 3460 if (IS_ENABLED(CFG_STM32_CLK_DEBUG)) 3461 clk_print_tree(); 3462 3463 return TEE_SUCCESS; 3464 } 3465 3466 CLK_DT_DECLARE(stm32mp25_clk, "st,stm32mp25-rcc", stm32mp2_clk_probe); 3467