1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2024, STMicroelectronics 4 */ 5 6 #include <assert.h> 7 #include <config.h> 8 #include <drivers/clk_dt.h> 9 #include <drivers/stm32_rif.h> 10 #include <drivers/stm32_shared_io.h> 11 #include <drivers/stm32mp25_rcc.h> 12 #include <drivers/stm32mp_dt_bindings.h> 13 #include <initcall.h> 14 #include <io.h> 15 #include <kernel/dt.h> 16 #include <kernel/panic.h> 17 #include <kernel/pm.h> 18 #include <libfdt.h> 19 #include <stdbool.h> 20 #include <stdio.h> 21 #include <stm32_sysconf.h> 22 #include <stm32_util.h> 23 #include <trace.h> 24 #include <util.h> 25 26 #include "clk-stm32-core.h" 27 28 #define MAX_OPP CFG_STM32MP_OPP_COUNT 29 30 #define RCC_SECCFGR(x) (U(0x0) + U(0x4) * (x)) 31 #define RCC_PRIVCFGR(x) (U(0x10) + U(0x4) * (x)) 32 #define RCC_RCFGLOCKR(x) (U(0x20) + U(0x4) * (x)) 33 #define RCC_CIDCFGR(x) (U(0x030) + U(0x08) * (x)) 34 #define RCC_SEMCR(x) (U(0x034) + U(0x08) * (x)) 35 36 #define TIMEOUT_US_100MS U(100000) 37 #define TIMEOUT_US_200MS U(200000) 38 #define TIMEOUT_US_1S U(1000000) 39 40 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 41 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 42 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 43 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 44 45 /* PLL minimal frequencies for clock sources */ 46 #define PLL_REFCLK_MIN UL(5000000) 47 #define PLL_FRAC_REFCLK_MIN UL(10000000) 48 49 /* Parameters from XBAR_CFG in st,cksrc field */ 50 #define XBAR_CKSRC_CHANNEL GENMASK_32(5, 0) 51 #define XBAR_CKSRC_SRC GENMASK_32(9, 6) 52 #define XBAR_CKSRC_SRC_OFFSET U(6) 53 #define XBAR_CKSRC_PREDIV GENMASK_32(19, 10) 54 #define XBAR_CKSRC_PREDIV_OFFSET U(10) 55 #define XBAR_CKSRC_FINDIV GENMASK_32(25, 20) 56 #define XBAR_CKSRC_FINDIV_OFFSET U(20) 57 58 #define XBAR_CHANNEL_NB U(64) 59 #define XBAR_ROOT_CHANNEL_NB U(7) 60 61 #define FLEX_STGEN U(33) 62 63 #define RCC_0_MHZ UL(0) 64 #define RCC_4_MHZ UL(4000000) 65 #define RCC_16_MHZ UL(16000000) 66 67 /* CIDCFGR register bitfields */ 68 #define RCC_CIDCFGR_SEMWL_MASK GENMASK_32(23, 16) 69 #define RCC_CIDCFGR_SCID_MASK GENMASK_32(6, 4) 70 #define RCC_CIDCFGR_CONF_MASK (_CIDCFGR_CFEN | \ 71 _CIDCFGR_SEMEN | \ 72 RCC_CIDCFGR_SCID_MASK |\ 73 RCC_CIDCFGR_SEMWL_MASK) 74 75 /* SECCFGR register bitfields */ 76 #define RCC_SECCFGR_EN BIT(0) 77 78 /* SEMCR register bitfields */ 79 #define RCC_SEMCR_SCID_MASK GENMASK_32(6, 4) 80 #define RCC_SEMCR_SCID_SHIFT U(4) 81 82 /* RIF miscellaneous */ 83 #define RCC_NB_RIF_RES U(114) 84 #define RCC_NB_CONFS ROUNDUP_DIV(RCC_NB_RIF_RES, 32) 85 86 enum pll_cfg { 87 FBDIV, 88 REFDIV, 89 POSTDIV1, 90 POSTDIV2, 91 PLLCFG_NB 92 }; 93 94 enum pll_csg { 95 DIVVAL, 96 SPREAD, 97 DOWNSPREAD, 98 PLLCSG_NB 99 }; 100 101 struct stm32_pll_dt_cfg { 102 bool enabled; 103 uint32_t cfg[PLLCFG_NB]; 104 uint32_t csg[PLLCSG_NB]; 105 uint32_t frac; 106 bool csg_enabled; 107 uint32_t src; 108 }; 109 110 struct stm32_osci_dt_cfg { 111 unsigned long freq; 112 bool bypass; 113 bool digbyp; 114 bool css; 115 uint32_t drive; 116 }; 117 118 struct stm32_clk_opp_cfg { 119 uint32_t frq; 120 uint32_t src; 121 struct stm32_pll_dt_cfg pll_cfg; 122 }; 123 124 struct stm32_clk_opp_dt_cfg { 125 struct stm32_clk_opp_cfg cpu1_opp[MAX_OPP]; 126 }; 127 128 struct stm32_clk_platdata { 129 uintptr_t rcc_base; 130 uint32_t nosci; 131 struct stm32_osci_dt_cfg *osci; 132 uint32_t npll; 133 struct stm32_pll_dt_cfg *pll; 134 struct stm32_clk_opp_dt_cfg *opp; 135 struct rif_conf_data conf_data; 136 unsigned int nb_res; 137 uint32_t nbusclk; 138 uint32_t *busclk; 139 uint32_t nkernelclk; 140 uint32_t *kernelclk; 141 uint32_t nflexgen; 142 uint32_t *flexgen; 143 uint32_t c1msrd; 144 bool safe_rst; 145 }; 146 147 /* 148 * GATE CONFIG 149 */ 150 151 /* WARNING GATE_XXX_RDY MUST FOLLOW GATE_XXX */ 152 153 enum enum_gate_cfg { 154 GATE_HSI, 155 GATE_HSI_RDY, 156 GATE_HSE, 157 GATE_HSE_RDY, 158 GATE_LSE, 159 GATE_LSE_RDY, 160 GATE_LSI, 161 GATE_LSI_RDY, 162 GATE_MSI, 163 GATE_MSI_RDY, 164 GATE_PLL1, 165 GATE_PLL1_RDY, 166 GATE_PLL2, 167 GATE_PLL2_RDY, 168 GATE_PLL3, 169 GATE_PLL3_RDY, 170 GATE_PLL4, 171 GATE_PLL4_RDY, 172 GATE_PLL5, 173 GATE_PLL5_RDY, 174 GATE_PLL6, 175 GATE_PLL6_RDY, 176 GATE_PLL7, 177 GATE_PLL7_RDY, 178 GATE_PLL8, 179 GATE_PLL8_RDY, 180 GATE_PLL4_CKREFST, 181 GATE_PLL5_CKREFST, 182 GATE_PLL6_CKREFST, 183 GATE_PLL7_CKREFST, 184 GATE_PLL8_CKREFST, 185 GATE_HSEDIV2, 186 GATE_APB1DIV_RDY, 187 GATE_APB2DIV_RDY, 188 GATE_APB3DIV_RDY, 189 GATE_APB4DIV_RDY, 190 GATE_APBDBGDIV_RDY, 191 GATE_TIMG1PRE_RDY, 192 GATE_TIMG2PRE_RDY, 193 GATE_LSMCUDIV_RDY, 194 GATE_RTCCK, 195 GATE_C3, 196 GATE_LPTIM3C3, 197 GATE_LPTIM4C3, 198 GATE_LPTIM5C3, 199 GATE_SPI8C3, 200 GATE_LPUART1C3, 201 GATE_I2C8C3, 202 GATE_ADF1C3, 203 GATE_GPIOZC3, 204 GATE_LPDMAC3, 205 GATE_RTCC3, 206 GATE_I3C4C3, 207 GATE_MCO1, 208 GATE_MCO2, 209 GATE_DDRCP, 210 GATE_DDRCAPB, 211 GATE_DDRPHYCAPB, 212 GATE_DDRPHYC, 213 GATE_DDRCFG, 214 GATE_SYSRAM, 215 GATE_VDERAM, 216 GATE_SRAM1, 217 GATE_SRAM2, 218 GATE_RETRAM, 219 GATE_BKPSRAM, 220 GATE_LPSRAM1, 221 GATE_LPSRAM2, 222 GATE_LPSRAM3, 223 GATE_OSPI1, 224 GATE_OSPI2, 225 GATE_FMC, 226 GATE_DBG, 227 GATE_TRACE, 228 GATE_STM, 229 GATE_ETR, 230 GATE_GPIOA, 231 GATE_GPIOB, 232 GATE_GPIOC, 233 GATE_GPIOD, 234 GATE_GPIOE, 235 GATE_GPIOF, 236 GATE_GPIOG, 237 GATE_GPIOH, 238 GATE_GPIOI, 239 GATE_GPIOJ, 240 GATE_GPIOK, 241 GATE_GPIOZ, 242 GATE_HPDMA1, 243 GATE_HPDMA2, 244 GATE_HPDMA3, 245 GATE_LPDMA, 246 GATE_HSEM, 247 GATE_IPCC1, 248 GATE_IPCC2, 249 GATE_RTC, 250 GATE_SYSCPU1, 251 GATE_BSEC, 252 GATE_IS2M, 253 GATE_HSIMON, 254 GATE_TIM1, 255 GATE_TIM2, 256 GATE_TIM3, 257 GATE_TIM4, 258 GATE_TIM5, 259 GATE_TIM6, 260 GATE_TIM7, 261 GATE_TIM8, 262 GATE_TIM10, 263 GATE_TIM11, 264 GATE_TIM12, 265 GATE_TIM13, 266 GATE_TIM14, 267 GATE_TIM15, 268 GATE_TIM16, 269 GATE_TIM17, 270 GATE_TIM20, 271 GATE_LPTIM1, 272 GATE_LPTIM2, 273 GATE_LPTIM3, 274 GATE_LPTIM4, 275 GATE_LPTIM5, 276 GATE_SPI1, 277 GATE_SPI2, 278 GATE_SPI3, 279 GATE_SPI4, 280 GATE_SPI5, 281 GATE_SPI6, 282 GATE_SPI7, 283 GATE_SPI8, 284 GATE_SPDIFRX, 285 GATE_USART1, 286 GATE_USART2, 287 GATE_USART3, 288 GATE_UART4, 289 GATE_UART5, 290 GATE_USART6, 291 GATE_UART7, 292 GATE_UART8, 293 GATE_UART9, 294 GATE_LPUART1, 295 GATE_I2C1, 296 GATE_I2C2, 297 GATE_I2C3, 298 GATE_I2C4, 299 GATE_I2C5, 300 GATE_I2C6, 301 GATE_I2C7, 302 GATE_I2C8, 303 GATE_SAI1, 304 GATE_SAI2, 305 GATE_SAI3, 306 GATE_SAI4, 307 GATE_MDF1, 308 GATE_ADF1, 309 GATE_FDCAN, 310 GATE_HDP, 311 GATE_ADC12, 312 GATE_ADC3, 313 GATE_ETH1MAC, 314 GATE_ETH1, 315 GATE_ETH1TX, 316 GATE_ETH1RX, 317 GATE_ETH1STP, 318 GATE_ETH2MAC, 319 GATE_ETH2, 320 GATE_ETH2STP, 321 GATE_ETH2TX, 322 GATE_ETH2RX, 323 GATE_USB2, 324 GATE_USB2PHY1, 325 GATE_USB2PHY2, 326 GATE_USB3DR, 327 GATE_USB3PCIEPHY, 328 GATE_PCIE, 329 GATE_USBTC, 330 GATE_ETHSWMAC, 331 GATE_ETHSW, 332 GATE_ETHSWREF, 333 GATE_STGEN, 334 GATE_SDMMC1, 335 GATE_SDMMC2, 336 GATE_SDMMC3, 337 GATE_GPU, 338 GATE_LTDC, 339 GATE_DSI, 340 GATE_LVDS, 341 GATE_CSI, 342 GATE_DCMIPP, 343 GATE_CCI, 344 GATE_VDEC, 345 GATE_VENC, 346 GATE_RNG, 347 GATE_PKA, 348 GATE_SAES, 349 GATE_HASH, 350 GATE_CRYP1, 351 GATE_CRYP2, 352 GATE_IWDG1, 353 GATE_IWDG2, 354 GATE_IWDG3, 355 GATE_IWDG4, 356 GATE_IWDG5, 357 GATE_WWDG1, 358 GATE_WWDG2, 359 GATE_VREF, 360 GATE_DTS, 361 GATE_CRC, 362 GATE_SERC, 363 GATE_OSPIIOM, 364 GATE_GICV2M, 365 GATE_I3C1, 366 GATE_I3C2, 367 GATE_I3C3, 368 GATE_I3C4, 369 GATE_NB 370 }; 371 372 #define GATE_CFG(_id, _offset, _bit_idx, _offset_clr)\ 373 [(_id)] = {\ 374 .offset = (_offset),\ 375 .bit_idx = (_bit_idx),\ 376 .set_clr = (_offset_clr),\ 377 } 378 379 static const struct gate_cfg gates_mp25[GATE_NB] = { 380 GATE_CFG(GATE_LSE, RCC_BDCR, 0, 0), 381 GATE_CFG(GATE_LSE_RDY, RCC_BDCR, 2, 0), 382 GATE_CFG(GATE_LSI, RCC_BDCR, 9, 0), 383 GATE_CFG(GATE_LSI_RDY, RCC_BDCR, 10, 0), 384 GATE_CFG(GATE_RTCCK, RCC_BDCR, 20, 0), 385 GATE_CFG(GATE_MSI, RCC_D3DCR, 0, 0), 386 GATE_CFG(GATE_MSI_RDY, RCC_D3DCR, 2, 0), 387 GATE_CFG(GATE_PLL1, RCC_PLL2CFGR1, 8, 0), 388 GATE_CFG(GATE_PLL1_RDY, RCC_PLL2CFGR1, 24, 0), 389 GATE_CFG(GATE_PLL2, RCC_PLL2CFGR1, 8, 0), 390 GATE_CFG(GATE_PLL2_RDY, RCC_PLL2CFGR1, 24, 0), 391 GATE_CFG(GATE_PLL3, RCC_PLL3CFGR1, 8, 0), 392 GATE_CFG(GATE_PLL3_RDY, RCC_PLL3CFGR1, 24, 0), 393 GATE_CFG(GATE_PLL4, RCC_PLL4CFGR1, 8, 0), 394 GATE_CFG(GATE_PLL4_RDY, RCC_PLL4CFGR1, 24, 0), 395 GATE_CFG(GATE_PLL5, RCC_PLL5CFGR1, 8, 0), 396 GATE_CFG(GATE_PLL5_RDY, RCC_PLL5CFGR1, 24, 0), 397 GATE_CFG(GATE_PLL6, RCC_PLL6CFGR1, 8, 0), 398 GATE_CFG(GATE_PLL6_RDY, RCC_PLL6CFGR1, 24, 0), 399 GATE_CFG(GATE_PLL7, RCC_PLL7CFGR1, 8, 0), 400 GATE_CFG(GATE_PLL7_RDY, RCC_PLL7CFGR1, 24, 0), 401 GATE_CFG(GATE_PLL8, RCC_PLL8CFGR1, 8, 0), 402 GATE_CFG(GATE_PLL8_RDY, RCC_PLL8CFGR1, 24, 0), 403 GATE_CFG(GATE_PLL4_CKREFST, RCC_PLL4CFGR1, 28, 0), 404 GATE_CFG(GATE_PLL5_CKREFST, RCC_PLL5CFGR1, 28, 0), 405 GATE_CFG(GATE_PLL6_CKREFST, RCC_PLL6CFGR1, 28, 0), 406 GATE_CFG(GATE_PLL7_CKREFST, RCC_PLL7CFGR1, 28, 0), 407 GATE_CFG(GATE_PLL8_CKREFST, RCC_PLL8CFGR1, 28, 0), 408 GATE_CFG(GATE_C3, RCC_C3CFGR, 1, 0), 409 GATE_CFG(GATE_LPTIM3C3, RCC_C3CFGR, 16, 0), 410 GATE_CFG(GATE_LPTIM4C3, RCC_C3CFGR, 17, 0), 411 GATE_CFG(GATE_LPTIM5C3, RCC_C3CFGR, 18, 0), 412 GATE_CFG(GATE_SPI8C3, RCC_C3CFGR, 19, 0), 413 GATE_CFG(GATE_LPUART1C3, RCC_C3CFGR, 20, 0), 414 GATE_CFG(GATE_I2C8C3, RCC_C3CFGR, 21, 0), 415 GATE_CFG(GATE_ADF1C3, RCC_C3CFGR, 23, 0), 416 GATE_CFG(GATE_GPIOZC3, RCC_C3CFGR, 24, 0), 417 GATE_CFG(GATE_LPDMAC3, RCC_C3CFGR, 25, 0), 418 GATE_CFG(GATE_RTCC3, RCC_C3CFGR, 26, 0), 419 GATE_CFG(GATE_I3C4C3, RCC_C3CFGR, 27, 0), 420 GATE_CFG(GATE_MCO1, RCC_MCO1CFGR, 8, 0), 421 GATE_CFG(GATE_MCO2, RCC_MCO2CFGR, 8, 0), 422 GATE_CFG(GATE_HSI, RCC_OCENSETR, 0, 1), 423 GATE_CFG(GATE_HSEDIV2, RCC_OCENSETR, 5, 1), 424 GATE_CFG(GATE_HSE, RCC_OCENSETR, 8, 1), 425 GATE_CFG(GATE_HSI_RDY, RCC_OCRDYR, 0, 0), 426 GATE_CFG(GATE_HSE_RDY, RCC_OCRDYR, 8, 0), 427 GATE_CFG(GATE_APB1DIV_RDY, RCC_APB1DIVR, 31, 0), 428 GATE_CFG(GATE_APB2DIV_RDY, RCC_APB2DIVR, 31, 0), 429 GATE_CFG(GATE_APB3DIV_RDY, RCC_APB3DIVR, 31, 0), 430 GATE_CFG(GATE_APB4DIV_RDY, RCC_APB4DIVR, 31, 0), 431 GATE_CFG(GATE_APBDBGDIV_RDY, RCC_APBDBGDIVR, 31, 0), 432 GATE_CFG(GATE_TIMG1PRE_RDY, RCC_TIMG1PRER, 31, 0), 433 GATE_CFG(GATE_TIMG2PRE_RDY, RCC_TIMG2PRER, 31, 0), 434 GATE_CFG(GATE_LSMCUDIV_RDY, RCC_LSMCUDIVR, 31, 0), 435 GATE_CFG(GATE_DDRCP, RCC_DDRCPCFGR, 1, 0), 436 GATE_CFG(GATE_DDRCAPB, RCC_DDRCAPBCFGR, 1, 0), 437 GATE_CFG(GATE_DDRPHYCAPB, RCC_DDRPHYCAPBCFGR, 1, 0), 438 GATE_CFG(GATE_DDRPHYC, RCC_DDRPHYCCFGR, 1, 0), 439 GATE_CFG(GATE_DDRCFG, RCC_DDRCFGR, 1, 0), 440 GATE_CFG(GATE_SYSRAM, RCC_SYSRAMCFGR, 1, 0), 441 GATE_CFG(GATE_VDERAM, RCC_VDERAMCFGR, 1, 0), 442 GATE_CFG(GATE_SRAM1, RCC_SRAM1CFGR, 1, 0), 443 GATE_CFG(GATE_SRAM2, RCC_SRAM2CFGR, 1, 0), 444 GATE_CFG(GATE_RETRAM, RCC_RETRAMCFGR, 1, 0), 445 GATE_CFG(GATE_BKPSRAM, RCC_BKPSRAMCFGR, 1, 0), 446 GATE_CFG(GATE_LPSRAM1, RCC_LPSRAM1CFGR, 1, 0), 447 GATE_CFG(GATE_LPSRAM2, RCC_LPSRAM2CFGR, 1, 0), 448 GATE_CFG(GATE_LPSRAM3, RCC_LPSRAM3CFGR, 1, 0), 449 GATE_CFG(GATE_OSPI1, RCC_OSPI1CFGR, 1, 0), 450 GATE_CFG(GATE_OSPI2, RCC_OSPI2CFGR, 1, 0), 451 GATE_CFG(GATE_FMC, RCC_FMCCFGR, 1, 0), 452 GATE_CFG(GATE_DBG, RCC_DBGCFGR, 8, 0), 453 GATE_CFG(GATE_TRACE, RCC_DBGCFGR, 9, 0), 454 GATE_CFG(GATE_STM, RCC_STMCFGR, 1, 0), 455 GATE_CFG(GATE_ETR, RCC_ETRCFGR, 1, 0), 456 GATE_CFG(GATE_GPIOA, RCC_GPIOACFGR, 1, 0), 457 GATE_CFG(GATE_GPIOB, RCC_GPIOBCFGR, 1, 0), 458 GATE_CFG(GATE_GPIOC, RCC_GPIOCCFGR, 1, 0), 459 GATE_CFG(GATE_GPIOD, RCC_GPIODCFGR, 1, 0), 460 GATE_CFG(GATE_GPIOE, RCC_GPIOECFGR, 1, 0), 461 GATE_CFG(GATE_GPIOF, RCC_GPIOFCFGR, 1, 0), 462 GATE_CFG(GATE_GPIOG, RCC_GPIOGCFGR, 1, 0), 463 GATE_CFG(GATE_GPIOH, RCC_GPIOHCFGR, 1, 0), 464 GATE_CFG(GATE_GPIOI, RCC_GPIOICFGR, 1, 0), 465 GATE_CFG(GATE_GPIOJ, RCC_GPIOJCFGR, 1, 0), 466 GATE_CFG(GATE_GPIOK, RCC_GPIOKCFGR, 1, 0), 467 GATE_CFG(GATE_GPIOZ, RCC_GPIOZCFGR, 1, 0), 468 GATE_CFG(GATE_HPDMA1, RCC_HPDMA1CFGR, 1, 0), 469 GATE_CFG(GATE_HPDMA2, RCC_HPDMA2CFGR, 1, 0), 470 GATE_CFG(GATE_HPDMA3, RCC_HPDMA3CFGR, 1, 0), 471 GATE_CFG(GATE_LPDMA, RCC_LPDMACFGR, 1, 0), 472 GATE_CFG(GATE_HSEM, RCC_HSEMCFGR, 1, 0), 473 GATE_CFG(GATE_IPCC1, RCC_IPCC1CFGR, 1, 0), 474 GATE_CFG(GATE_IPCC2, RCC_IPCC2CFGR, 1, 0), 475 GATE_CFG(GATE_RTC, RCC_RTCCFGR, 1, 0), 476 GATE_CFG(GATE_SYSCPU1, RCC_SYSCPU1CFGR, 1, 0), 477 GATE_CFG(GATE_BSEC, RCC_BSECCFGR, 1, 0), 478 GATE_CFG(GATE_IS2M, RCC_IS2MCFGR, 1, 0), 479 GATE_CFG(GATE_HSIMON, RCC_HSIFMONCR, 15, 0), 480 GATE_CFG(GATE_TIM1, RCC_TIM1CFGR, 1, 0), 481 GATE_CFG(GATE_TIM2, RCC_TIM2CFGR, 1, 0), 482 GATE_CFG(GATE_TIM3, RCC_TIM3CFGR, 1, 0), 483 GATE_CFG(GATE_TIM4, RCC_TIM4CFGR, 1, 0), 484 GATE_CFG(GATE_TIM5, RCC_TIM5CFGR, 1, 0), 485 GATE_CFG(GATE_TIM6, RCC_TIM6CFGR, 1, 0), 486 GATE_CFG(GATE_TIM7, RCC_TIM7CFGR, 1, 0), 487 GATE_CFG(GATE_TIM8, RCC_TIM8CFGR, 1, 0), 488 GATE_CFG(GATE_TIM10, RCC_TIM10CFGR, 1, 0), 489 GATE_CFG(GATE_TIM11, RCC_TIM11CFGR, 1, 0), 490 GATE_CFG(GATE_TIM12, RCC_TIM12CFGR, 1, 0), 491 GATE_CFG(GATE_TIM13, RCC_TIM13CFGR, 1, 0), 492 GATE_CFG(GATE_TIM14, RCC_TIM14CFGR, 1, 0), 493 GATE_CFG(GATE_TIM15, RCC_TIM15CFGR, 1, 0), 494 GATE_CFG(GATE_TIM16, RCC_TIM16CFGR, 1, 0), 495 GATE_CFG(GATE_TIM17, RCC_TIM17CFGR, 1, 0), 496 GATE_CFG(GATE_TIM20, RCC_TIM20CFGR, 1, 0), 497 GATE_CFG(GATE_LPTIM1, RCC_LPTIM1CFGR, 1, 0), 498 GATE_CFG(GATE_LPTIM2, RCC_LPTIM2CFGR, 1, 0), 499 GATE_CFG(GATE_LPTIM3, RCC_LPTIM3CFGR, 1, 0), 500 GATE_CFG(GATE_LPTIM4, RCC_LPTIM4CFGR, 1, 0), 501 GATE_CFG(GATE_LPTIM5, RCC_LPTIM5CFGR, 1, 0), 502 GATE_CFG(GATE_SPI1, RCC_SPI1CFGR, 1, 0), 503 GATE_CFG(GATE_SPI2, RCC_SPI2CFGR, 1, 0), 504 GATE_CFG(GATE_SPI3, RCC_SPI3CFGR, 1, 0), 505 GATE_CFG(GATE_SPI4, RCC_SPI4CFGR, 1, 0), 506 GATE_CFG(GATE_SPI5, RCC_SPI5CFGR, 1, 0), 507 GATE_CFG(GATE_SPI6, RCC_SPI6CFGR, 1, 0), 508 GATE_CFG(GATE_SPI7, RCC_SPI7CFGR, 1, 0), 509 GATE_CFG(GATE_SPI8, RCC_SPI8CFGR, 1, 0), 510 GATE_CFG(GATE_SPDIFRX, RCC_SPDIFRXCFGR, 1, 0), 511 GATE_CFG(GATE_USART1, RCC_USART1CFGR, 1, 0), 512 GATE_CFG(GATE_USART2, RCC_USART2CFGR, 1, 0), 513 GATE_CFG(GATE_USART3, RCC_USART3CFGR, 1, 0), 514 GATE_CFG(GATE_UART4, RCC_UART4CFGR, 1, 0), 515 GATE_CFG(GATE_UART5, RCC_UART5CFGR, 1, 0), 516 GATE_CFG(GATE_USART6, RCC_USART6CFGR, 1, 0), 517 GATE_CFG(GATE_UART7, RCC_UART7CFGR, 1, 0), 518 GATE_CFG(GATE_UART8, RCC_UART8CFGR, 1, 0), 519 GATE_CFG(GATE_UART9, RCC_UART9CFGR, 1, 0), 520 GATE_CFG(GATE_LPUART1, RCC_LPUART1CFGR, 1, 0), 521 GATE_CFG(GATE_I2C1, RCC_I2C1CFGR, 1, 0), 522 GATE_CFG(GATE_I2C2, RCC_I2C2CFGR, 1, 0), 523 GATE_CFG(GATE_I2C3, RCC_I2C3CFGR, 1, 0), 524 GATE_CFG(GATE_I2C4, RCC_I2C4CFGR, 1, 0), 525 GATE_CFG(GATE_I2C5, RCC_I2C5CFGR, 1, 0), 526 GATE_CFG(GATE_I2C6, RCC_I2C6CFGR, 1, 0), 527 GATE_CFG(GATE_I2C7, RCC_I2C7CFGR, 1, 0), 528 GATE_CFG(GATE_I2C8, RCC_I2C8CFGR, 1, 0), 529 GATE_CFG(GATE_SAI1, RCC_SAI1CFGR, 1, 0), 530 GATE_CFG(GATE_SAI2, RCC_SAI2CFGR, 1, 0), 531 GATE_CFG(GATE_SAI3, RCC_SAI3CFGR, 1, 0), 532 GATE_CFG(GATE_SAI4, RCC_SAI4CFGR, 1, 0), 533 GATE_CFG(GATE_MDF1, RCC_MDF1CFGR, 1, 0), 534 GATE_CFG(GATE_ADF1, RCC_ADF1CFGR, 1, 0), 535 GATE_CFG(GATE_FDCAN, RCC_FDCANCFGR, 1, 0), 536 GATE_CFG(GATE_HDP, RCC_HDPCFGR, 1, 0), 537 GATE_CFG(GATE_ADC12, RCC_ADC12CFGR, 1, 0), 538 GATE_CFG(GATE_ADC3, RCC_ADC3CFGR, 1, 0), 539 GATE_CFG(GATE_ETH1MAC, RCC_ETH1CFGR, 1, 0), 540 GATE_CFG(GATE_ETH1STP, RCC_ETH1CFGR, 4, 0), 541 GATE_CFG(GATE_ETH1, RCC_ETH1CFGR, 5, 0), 542 GATE_CFG(GATE_ETH1TX, RCC_ETH1CFGR, 8, 0), 543 GATE_CFG(GATE_ETH1RX, RCC_ETH1CFGR, 10, 0), 544 GATE_CFG(GATE_ETH2MAC, RCC_ETH2CFGR, 1, 0), 545 GATE_CFG(GATE_ETH2STP, RCC_ETH2CFGR, 4, 0), 546 GATE_CFG(GATE_ETH2, RCC_ETH2CFGR, 5, 0), 547 GATE_CFG(GATE_ETH2TX, RCC_ETH2CFGR, 8, 0), 548 GATE_CFG(GATE_ETH2RX, RCC_ETH2CFGR, 10, 0), 549 GATE_CFG(GATE_USB2, RCC_USB2CFGR, 1, 0), 550 GATE_CFG(GATE_USB2PHY1, RCC_USB2PHY1CFGR, 1, 0), 551 GATE_CFG(GATE_USB2PHY2, RCC_USB2PHY2CFGR, 1, 0), 552 GATE_CFG(GATE_USB3DR, RCC_USB3DRCFGR, 1, 0), 553 GATE_CFG(GATE_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 1, 0), 554 GATE_CFG(GATE_PCIE, RCC_PCIECFGR, 1, 0), 555 GATE_CFG(GATE_USBTC, RCC_USBTCCFGR, 1, 0), 556 GATE_CFG(GATE_ETHSWMAC, RCC_ETHSWCFGR, 1, 0), 557 GATE_CFG(GATE_ETHSW, RCC_ETHSWCFGR, 5, 0), 558 GATE_CFG(GATE_ETHSWREF, RCC_ETHSWCFGR, 21, 0), 559 GATE_CFG(GATE_STGEN, RCC_STGENCFGR, 1, 0), 560 GATE_CFG(GATE_SDMMC1, RCC_SDMMC1CFGR, 1, 0), 561 GATE_CFG(GATE_SDMMC2, RCC_SDMMC2CFGR, 1, 0), 562 GATE_CFG(GATE_SDMMC3, RCC_SDMMC3CFGR, 1, 0), 563 GATE_CFG(GATE_GPU, RCC_GPUCFGR, 1, 0), 564 GATE_CFG(GATE_LTDC, RCC_LTDCCFGR, 1, 0), 565 GATE_CFG(GATE_DSI, RCC_DSICFGR, 1, 0), 566 GATE_CFG(GATE_LVDS, RCC_LVDSCFGR, 1, 0), 567 GATE_CFG(GATE_CSI, RCC_CSICFGR, 1, 0), 568 GATE_CFG(GATE_DCMIPP, RCC_DCMIPPCFGR, 1, 0), 569 GATE_CFG(GATE_CCI, RCC_CCICFGR, 1, 0), 570 GATE_CFG(GATE_VDEC, RCC_VDECCFGR, 1, 0), 571 GATE_CFG(GATE_VENC, RCC_VENCCFGR, 1, 0), 572 GATE_CFG(GATE_RNG, RCC_RNGCFGR, 1, 0), 573 GATE_CFG(GATE_PKA, RCC_PKACFGR, 1, 0), 574 GATE_CFG(GATE_SAES, RCC_SAESCFGR, 1, 0), 575 GATE_CFG(GATE_HASH, RCC_HASHCFGR, 1, 0), 576 GATE_CFG(GATE_CRYP1, RCC_CRYP1CFGR, 1, 0), 577 GATE_CFG(GATE_CRYP2, RCC_CRYP2CFGR, 1, 0), 578 GATE_CFG(GATE_IWDG1, RCC_IWDG1CFGR, 1, 0), 579 GATE_CFG(GATE_IWDG2, RCC_IWDG2CFGR, 1, 0), 580 GATE_CFG(GATE_IWDG3, RCC_IWDG3CFGR, 1, 0), 581 GATE_CFG(GATE_IWDG4, RCC_IWDG4CFGR, 1, 0), 582 GATE_CFG(GATE_IWDG5, RCC_IWDG5CFGR, 1, 0), 583 GATE_CFG(GATE_WWDG1, RCC_WWDG1CFGR, 1, 0), 584 GATE_CFG(GATE_WWDG2, RCC_WWDG2CFGR, 1, 0), 585 GATE_CFG(GATE_VREF, RCC_VREFCFGR, 1, 0), 586 GATE_CFG(GATE_DTS, RCC_DTSCFGR, 1, 0), 587 GATE_CFG(GATE_CRC, RCC_CRCCFGR, 1, 0), 588 GATE_CFG(GATE_SERC, RCC_SERCCFGR, 1, 0), 589 GATE_CFG(GATE_OSPIIOM, RCC_OSPIIOMCFGR, 1, 0), 590 GATE_CFG(GATE_GICV2M, RCC_GICV2MCFGR, 1, 0), 591 GATE_CFG(GATE_I3C1, RCC_I3C1CFGR, 1, 0), 592 GATE_CFG(GATE_I3C2, RCC_I3C2CFGR, 1, 0), 593 GATE_CFG(GATE_I3C3, RCC_I3C3CFGR, 1, 0), 594 GATE_CFG(GATE_I3C4, RCC_I3C4CFGR, 1, 0), 595 }; 596 597 /* 598 * MUX CONFIG 599 */ 600 601 #define _MUX_CFG(_id, _offset, _shift, _width, _rdy)\ 602 [(_id)] = {\ 603 .offset = (_offset),\ 604 .shift = (_shift),\ 605 .width = (_width),\ 606 .ready = (_rdy),\ 607 } 608 609 static const struct mux_cfg parent_mp25[MUX_NB] = { 610 _MUX_CFG(MUX_MUXSEL0, RCC_MUXSELCFGR, 0, 2, GATE_PLL4_CKREFST), 611 _MUX_CFG(MUX_MUXSEL1, RCC_MUXSELCFGR, 4, 2, GATE_PLL5_CKREFST), 612 _MUX_CFG(MUX_MUXSEL2, RCC_MUXSELCFGR, 8, 2, GATE_PLL6_CKREFST), 613 _MUX_CFG(MUX_MUXSEL3, RCC_MUXSELCFGR, 12, 2, GATE_PLL7_CKREFST), 614 _MUX_CFG(MUX_MUXSEL4, RCC_MUXSELCFGR, 16, 2, GATE_PLL8_CKREFST), 615 _MUX_CFG(MUX_MUXSEL5, RCC_MUXSELCFGR, 20, 2, MUX_NO_RDY), 616 _MUX_CFG(MUX_MUXSEL6, RCC_MUXSELCFGR, 24, 2, MUX_NO_RDY), 617 _MUX_CFG(MUX_MUXSEL7, RCC_MUXSELCFGR, 28, 2, MUX_NO_RDY), 618 _MUX_CFG(MUX_XBARSEL, RCC_XBAR0CFGR, 0, 4, MUX_NO_RDY), 619 _MUX_CFG(MUX_RTC, RCC_BDCR, 16, 2, MUX_NO_RDY), 620 _MUX_CFG(MUX_D3PER, RCC_D3DCR, 16, 2, MUX_NO_RDY), 621 _MUX_CFG(MUX_MCO1, RCC_MCO1CFGR, 0, 1, MUX_NO_RDY), 622 _MUX_CFG(MUX_MCO2, RCC_MCO2CFGR, 0, 1, MUX_NO_RDY), 623 _MUX_CFG(MUX_ADC12, RCC_ADC12CFGR, 12, 1, MUX_NO_RDY), 624 _MUX_CFG(MUX_ADC3, RCC_ADC3CFGR, 12, 2, MUX_NO_RDY), 625 _MUX_CFG(MUX_USB2PHY1, RCC_USB2PHY1CFGR, 15, 1, MUX_NO_RDY), 626 _MUX_CFG(MUX_USB2PHY2, RCC_USB2PHY2CFGR, 15, 1, MUX_NO_RDY), 627 _MUX_CFG(MUX_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 15, 1, MUX_NO_RDY), 628 _MUX_CFG(MUX_DSIBLANE, RCC_DSICFGR, 12, 1, MUX_NO_RDY), 629 _MUX_CFG(MUX_DSIPHY, RCC_DSICFGR, 15, 1, MUX_NO_RDY), 630 _MUX_CFG(MUX_LVDSPHY, RCC_LVDSCFGR, 15, 1, MUX_NO_RDY), 631 _MUX_CFG(MUX_DTS, RCC_DTSCFGR, 12, 2, MUX_NO_RDY), 632 }; 633 634 /* 635 * DIV CONFIG 636 */ 637 638 static const struct div_table_cfg apb_div_table[] = { 639 { .val = 0, .div = 1 }, 640 { .val = 1, .div = 2 }, 641 { .val = 2, .div = 4 }, 642 { .val = 3, .div = 8 }, 643 { .val = 4, .div = 16 }, 644 { .val = 5, .div = 16 }, 645 { .val = 6, .div = 16 }, 646 { .val = 7, .div = 16 }, 647 /* .div = 0 termination cell */ 648 { } 649 }; 650 651 #define _DIV_CFG(_id, _offset, _shift, _width, _flags, _table, _ready)\ 652 [(_id)] = {\ 653 .offset = (_offset),\ 654 .shift = (_shift),\ 655 .width = (_width),\ 656 .flags = (_flags),\ 657 .table = (_table),\ 658 .ready = (_ready),\ 659 } 660 661 static const struct div_cfg dividers_mp25[DIV_NB] = { 662 _DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, DIV_NO_RDY), 663 _DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 0, apb_div_table, 664 GATE_APB1DIV_RDY), 665 _DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 0, apb_div_table, 666 GATE_APB2DIV_RDY), 667 _DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 0, apb_div_table, 668 GATE_APB3DIV_RDY), 669 _DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 0, apb_div_table, 670 GATE_APB4DIV_RDY), 671 _DIV_CFG(DIV_APBDBG, RCC_APBDBGDIVR, 0, 3, 0, apb_div_table, 672 GATE_APBDBGDIV_RDY), 673 _DIV_CFG(DIV_LSMCU, RCC_LSMCUDIVR, 0, 1, 0, NULL, GATE_LSMCUDIV_RDY), 674 }; 675 676 enum stm32_osc { 677 OSC_HSI, 678 OSC_HSE, 679 OSC_MSI, 680 OSC_LSI, 681 OSC_LSE, 682 NB_OSCILLATOR 683 }; 684 685 struct clk_stm32_bypass { 686 uint16_t offset; 687 uint8_t bit_byp; 688 uint8_t bit_digbyp; 689 }; 690 691 struct clk_stm32_css { 692 uint16_t offset; 693 uint8_t bit_css; 694 }; 695 696 struct clk_stm32_drive { 697 uint16_t offset; 698 uint8_t drv_shift; 699 uint8_t drv_width; 700 uint8_t drv_default; 701 }; 702 703 struct clk_oscillator_data { 704 const char *name; 705 unsigned long frequency; 706 uint16_t gate_id; 707 struct clk_stm32_bypass *bypass; 708 struct clk_stm32_css *css; 709 struct clk_stm32_drive *drive; 710 }; 711 712 #define BYPASS(_offset, _bit_byp, _bit_digbyp) \ 713 (&(struct clk_stm32_bypass){\ 714 .offset = (_offset),\ 715 .bit_byp = (_bit_byp),\ 716 .bit_digbyp = (_bit_digbyp),\ 717 }) 718 719 #define CSS(_offset, _bit_css) \ 720 (&(struct clk_stm32_css){\ 721 .offset = (_offset),\ 722 .bit_css = (_bit_css),\ 723 }) 724 725 #define DRIVE(_offset, _shift, _width, _default) \ 726 (&(struct clk_stm32_drive){\ 727 .offset = (_offset),\ 728 .drv_shift = (_shift),\ 729 .drv_width = (_width),\ 730 .drv_default = (_default),\ 731 }) 732 733 #define OSCILLATOR(idx_osc, _name, _gate_id, _bypass, _css, _drive) \ 734 [(idx_osc)] = (struct clk_oscillator_data){\ 735 .name = (_name),\ 736 .gate_id = (_gate_id),\ 737 .bypass = (_bypass),\ 738 .css = (_css),\ 739 .drive = (_drive),\ 740 } 741 742 static struct clk_oscillator_data stm32mp25_osc_data[NB_OSCILLATOR] = { 743 OSCILLATOR(OSC_HSI, "clk-hsi", GATE_HSI, 744 NULL, NULL, NULL), 745 746 OSCILLATOR(OSC_LSI, "clk-lsi", GATE_LSI, 747 NULL, NULL, NULL), 748 749 OSCILLATOR(OSC_MSI, "clk-msi", GATE_MSI, 750 NULL, NULL, NULL), 751 752 OSCILLATOR(OSC_LSE, "clk-lse", GATE_LSE, 753 BYPASS(RCC_BDCR, RCC_BDCR_LSEBYP_BIT, 754 RCC_BDCR_LSEDIGBYP_BIT), 755 CSS(RCC_BDCR, RCC_BDCR_LSECSSON_BIT), 756 DRIVE(RCC_BDCR, RCC_BDCR_LSEDRV_SHIFT, 757 RCC_BDCR_LSEDRV_WIDTH, LSEDRV_MEDIUM_HIGH)), 758 759 OSCILLATOR(OSC_HSE, "clk-hse", GATE_HSE, 760 BYPASS(RCC_OCENSETR, RCC_OCENSETR_HSEBYP_BIT, 761 RCC_OCENSETR_HSEDIGBYP_BIT), 762 CSS(RCC_OCENSETR, RCC_OCENSETR_HSECSSON_BIT), 763 NULL), 764 }; 765 766 static struct clk_oscillator_data *clk_oscillator_get_data(unsigned int osc_id) 767 { 768 assert(osc_id < ARRAY_SIZE(stm32mp25_osc_data)); 769 770 return &stm32mp25_osc_data[osc_id]; 771 } 772 773 static unsigned long clk_stm32_get_rate_oscillator(unsigned int osc_id) 774 { 775 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 776 struct stm32_clk_platdata *pdata = priv->pdata; 777 struct stm32_osci_dt_cfg *osci = &pdata->osci[osc_id]; 778 779 return osci->freq; 780 } 781 782 static unsigned long clk_stm32_pll_get_oscillator_rate(unsigned int sel) 783 { 784 unsigned int osc[] = { OSC_HSI, OSC_HSE, OSC_MSI }; 785 786 assert(sel < ARRAY_SIZE(osc)); 787 788 return clk_stm32_get_rate_oscillator(osc[sel]); 789 } 790 791 static void clk_oscillator_set_bypass(struct clk_stm32_priv *priv, 792 struct clk_oscillator_data *osc_data, 793 bool digbyp, bool bypass) 794 { 795 struct clk_stm32_bypass *bypass_data = osc_data->bypass; 796 uintptr_t address = 0; 797 798 if (!bypass_data) 799 return; 800 801 address = priv->base + bypass_data->offset; 802 803 if (digbyp) 804 io_setbits32(address, BIT(bypass_data->bit_digbyp)); 805 806 if (bypass || digbyp) 807 io_setbits32(address, BIT(bypass_data->bit_byp)); 808 } 809 810 static void clk_oscillator_set_css(struct clk_stm32_priv *priv, 811 struct clk_oscillator_data *osc_data, 812 bool css) 813 { 814 struct clk_stm32_css *css_data = osc_data->css; 815 816 if (css_data && css) 817 io_setbits32(priv->base + css_data->offset, 818 BIT(css_data->bit_css)); 819 } 820 821 static void clk_oscillator_set_drive(struct clk_stm32_priv *priv, 822 struct clk_oscillator_data *osc_data, 823 uint8_t lsedrv) 824 { 825 struct clk_stm32_drive *drive_data = osc_data->drive; 826 uintptr_t address = 0; 827 uint32_t mask = 0; 828 uint32_t value = 0; 829 830 if (!drive_data) 831 return; 832 833 address = priv->base + drive_data->offset; 834 835 mask = SHIFT_U32(BIT(drive_data->drv_width) - 1, drive_data->drv_shift); 836 837 /* 838 * Warning: not recommended to switch directly from "high drive" 839 * to "medium low drive", and vice-versa. 840 */ 841 value = (io_read32(address) & mask) >> drive_data->drv_shift; 842 843 while (value != lsedrv) { 844 if (value > lsedrv) 845 value--; 846 else 847 value++; 848 849 io_clrsetbits32(address, mask, 850 SHIFT_U32(value, drive_data->drv_shift)); 851 } 852 } 853 854 static void stm32_enable_oscillator_hse(struct clk_stm32_priv *priv, 855 struct stm32_clk_platdata *pdata) 856 { 857 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_HSE); 858 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_HSE]; 859 860 if (!osci->freq) 861 return; 862 863 clk_oscillator_set_bypass(priv, osc_data, osci->digbyp, osci->bypass); 864 865 /* Enable clock and wait ready bit */ 866 if (stm32_gate_rdy_enable(osc_data->gate_id)) 867 panic("timeout to enable hse clock"); 868 869 clk_oscillator_set_css(priv, osc_data, osci->css); 870 } 871 872 static void stm32_enable_oscillator_lse(struct clk_stm32_priv *priv, 873 struct stm32_clk_platdata *pdata) 874 { 875 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_LSE); 876 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE]; 877 878 if (!osci->freq) 879 return; 880 881 if (stm32_gate_is_enabled(osc_data->gate_id)) 882 return; 883 884 clk_oscillator_set_bypass(priv, osc_data, osci->digbyp, osci->bypass); 885 886 clk_oscillator_set_drive(priv, osc_data, osci->drive); 887 888 /* Enable LSE clock, but don't wait ready bit */ 889 stm32_gate_enable(osc_data->gate_id); 890 } 891 892 static void stm32_enable_oscillator_lsi(struct clk_stm32_priv *priv __unused, 893 struct stm32_clk_platdata *pdata) 894 { 895 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_LSI); 896 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSI]; 897 898 if (!osci->freq) 899 return; 900 901 /* Enable clock and wait ready bit */ 902 if (stm32_gate_rdy_enable(osc_data->gate_id)) 903 panic("timeout to enable lsi clock"); 904 } 905 906 static TEE_Result clk_stm32_osc_msi_set_rate(struct clk_stm32_priv *priv, 907 unsigned long rate) 908 { 909 uintptr_t address = priv->base + RCC_BDCR; 910 uint32_t mask = RCC_BDCR_MSIFREQSEL; 911 912 switch (rate) { 913 case RCC_4_MHZ: 914 io_clrbits32_stm32shregs(address, mask); 915 break; 916 case RCC_16_MHZ: 917 io_setbits32_stm32shregs(address, mask); 918 break; 919 default: 920 return TEE_ERROR_GENERIC; 921 } 922 923 return TEE_SUCCESS; 924 } 925 926 static void stm32_enable_oscillator_msi(struct clk_stm32_priv *priv, 927 struct stm32_clk_platdata *pdata) 928 { 929 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_MSI); 930 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_MSI]; 931 932 if (!osci->freq) 933 return; 934 935 if (clk_stm32_osc_msi_set_rate(priv, osci->freq) != TEE_SUCCESS) { 936 EMSG("invalid rate %ld Hz for MSI ! (4000000 or 16000000 only)", 937 osci->freq); 938 panic(); 939 } 940 941 /* Enable clock and wait ready bit */ 942 if (stm32_gate_rdy_enable(osc_data->gate_id)) 943 panic("timeout to enable msi clock"); 944 } 945 946 static void stm32_clk_oscillators_lse_set_css(struct clk_stm32_priv *priv, 947 struct stm32_clk_platdata *pdata) 948 949 { 950 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_LSE); 951 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE]; 952 953 clk_oscillator_set_css(priv, osc_data, osci->css); 954 } 955 956 static int 957 stm32_clk_oscillators_wait_lse_ready(struct clk_stm32_priv *priv __unused, 958 struct stm32_clk_platdata *pdata) 959 { 960 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_LSE); 961 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE]; 962 int ret = 0; 963 964 if (osci->freq && stm32_gate_wait_ready(osc_data->gate_id, true)) 965 ret = -1; 966 967 return ret; 968 } 969 970 static void stm32_clk_oscillators_enable(struct clk_stm32_priv *priv, 971 struct stm32_clk_platdata *pdata) 972 { 973 stm32_enable_oscillator_hse(priv, pdata); 974 stm32_enable_oscillator_lse(priv, pdata); 975 stm32_enable_oscillator_lsi(priv, pdata); 976 stm32_enable_oscillator_msi(priv, pdata); 977 } 978 979 enum stm32_pll_id { 980 PLL1_ID, 981 PLL2_ID, 982 PLL3_ID, 983 PLL4_ID, 984 PLL5_ID, 985 PLL6_ID, 986 PLL7_ID, 987 PLL8_ID, 988 PLL_NB 989 }; 990 991 /* PLL configuration registers offsets from RCC_PLLxCFGR1 */ 992 #define RCC_OFFSET_PLLXCFGR1 0x00 993 #define RCC_OFFSET_PLLXCFGR2 0x04 994 #define RCC_OFFSET_PLLXCFGR3 0x08 995 #define RCC_OFFSET_PLLXCFGR4 0x0C 996 #define RCC_OFFSET_PLLXCFGR5 0x10 997 #define RCC_OFFSET_PLLXCFGR6 0x18 998 #define RCC_OFFSET_PLLXCFGR7 0x1C 999 1000 struct stm32_clk_pll { 1001 uint16_t gate_id; 1002 uint16_t mux_id; 1003 uint16_t reg_pllxcfgr1; 1004 }; 1005 1006 #define CLK_PLL_CFG(_idx, _gate_id, _mux_id, _reg)\ 1007 [(_idx)] = {\ 1008 .gate_id = (_gate_id),\ 1009 .mux_id = (_mux_id),\ 1010 .reg_pllxcfgr1 = (_reg),\ 1011 } 1012 1013 static const struct stm32_clk_pll stm32mp25_clk_pll[PLL_NB] = { 1014 CLK_PLL_CFG(PLL1_ID, GATE_PLL1, MUX_MUXSEL5, 0), 1015 CLK_PLL_CFG(PLL2_ID, GATE_PLL2, MUX_MUXSEL6, RCC_PLL2CFGR1), 1016 CLK_PLL_CFG(PLL3_ID, GATE_PLL3, MUX_MUXSEL7, RCC_PLL3CFGR1), 1017 CLK_PLL_CFG(PLL4_ID, GATE_PLL4, MUX_MUXSEL0, RCC_PLL4CFGR1), 1018 CLK_PLL_CFG(PLL5_ID, GATE_PLL5, MUX_MUXSEL1, RCC_PLL5CFGR1), 1019 CLK_PLL_CFG(PLL6_ID, GATE_PLL6, MUX_MUXSEL2, RCC_PLL6CFGR1), 1020 CLK_PLL_CFG(PLL7_ID, GATE_PLL7, MUX_MUXSEL3, RCC_PLL7CFGR1), 1021 CLK_PLL_CFG(PLL8_ID, GATE_PLL8, MUX_MUXSEL4, RCC_PLL8CFGR1), 1022 }; 1023 1024 static const struct stm32_clk_pll *clk_stm32_pll_data(unsigned int idx) 1025 { 1026 assert(idx < ARRAY_SIZE(stm32mp25_clk_pll)); 1027 1028 return &stm32mp25_clk_pll[idx]; 1029 } 1030 1031 static int stm32_clk_parse_oscillator_fdt(const void *fdt, int node, 1032 const char *name, 1033 struct stm32_osci_dt_cfg *osci) 1034 { 1035 int subnode = 0; 1036 1037 /* default value when oscillator is not found */ 1038 osci->freq = 0; 1039 1040 fdt_for_each_subnode(subnode, fdt, node) { 1041 const char *cchar = NULL; 1042 const fdt32_t *cuint = NULL; 1043 int ret = 0; 1044 1045 cchar = fdt_get_name(fdt, subnode, &ret); 1046 if (!cchar) 1047 return ret; 1048 1049 if (strncmp(cchar, name, (size_t)ret) || 1050 fdt_get_status(fdt, subnode) == DT_STATUS_DISABLED) 1051 continue; 1052 1053 cuint = fdt_getprop(fdt, subnode, "clock-frequency", &ret); 1054 if (!cuint) 1055 return ret; 1056 1057 osci->freq = fdt32_to_cpu(*cuint); 1058 1059 if (fdt_getprop(fdt, subnode, "st,bypass", NULL)) 1060 osci->bypass = true; 1061 1062 if (fdt_getprop(fdt, subnode, "st,digbypass", NULL)) 1063 osci->digbyp = true; 1064 1065 if (fdt_getprop(fdt, subnode, "st,css", NULL)) 1066 osci->css = true; 1067 1068 osci->drive = fdt_read_uint32_default(fdt, subnode, "st,drive", 1069 LSEDRV_MEDIUM_HIGH); 1070 1071 return 0; 1072 } 1073 1074 return 0; 1075 } 1076 1077 static const char *stm32_clk_get_oscillator_name(enum stm32_osc id) 1078 { 1079 if (id < NB_OSCILLATOR) 1080 return stm32mp25_osc_data[id].name; 1081 1082 return NULL; 1083 } 1084 1085 static int stm32_clk_parse_fdt_all_oscillator(const void *fdt, 1086 int node __unused, 1087 struct stm32_clk_platdata *pdata) 1088 { 1089 int fdt_err = 0; 1090 size_t i = 0; 1091 int osc_node = 0; 1092 1093 osc_node = fdt_path_offset(fdt, "/clocks"); 1094 if (osc_node < 0) 1095 return -FDT_ERR_NOTFOUND; 1096 1097 for (i = 0; i < pdata->nosci; i++) { 1098 const char *name = NULL; 1099 1100 name = stm32_clk_get_oscillator_name((enum stm32_osc)i); 1101 if (!name) 1102 continue; 1103 1104 fdt_err = stm32_clk_parse_oscillator_fdt(fdt, osc_node, name, 1105 &pdata->osci[i]); 1106 if (fdt_err < 0) 1107 panic(); 1108 } 1109 1110 return 0; 1111 } 1112 1113 static int clk_stm32_parse_pll_fdt(const void *fdt, int subnode, 1114 struct stm32_pll_dt_cfg *pll) 1115 { 1116 const fdt32_t *cuint = NULL; 1117 int subnode_pll = 0; 1118 int err = 0; 1119 1120 cuint = fdt_getprop(fdt, subnode, "st,pll", NULL); 1121 if (!cuint) 1122 return 0; 1123 1124 subnode_pll = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 1125 if (subnode_pll < 0) 1126 return -FDT_ERR_NOTFOUND; 1127 1128 if (fdt_read_uint32_array(fdt, subnode_pll, "cfg", pll->cfg, 1129 PLLCFG_NB) != 0) 1130 panic("cfg property is mandatory"); 1131 1132 err = fdt_read_uint32_array(fdt, subnode_pll, "csg", pll->csg, 1133 PLLCSG_NB); 1134 1135 pll->csg_enabled = (err == 0); 1136 1137 if (err == -FDT_ERR_NOTFOUND) 1138 err = 0; 1139 1140 if (err != 0) 1141 return err; 1142 1143 pll->enabled = true; 1144 1145 pll->frac = fdt_read_uint32_default(fdt, subnode_pll, "frac", 0); 1146 1147 if (fdt_read_uint32(fdt, subnode_pll, "src", &pll->src)) 1148 panic("src property is mandatory"); 1149 1150 return 0; 1151 } 1152 1153 #define RCC_PLL_NAME_SIZE 20 1154 1155 static int stm32_clk_parse_fdt_all_pll(const void *fdt, int node, 1156 struct stm32_clk_platdata *pdata) 1157 { 1158 unsigned int i = 0; 1159 1160 for (i = 0; i < pdata->npll; i++) { 1161 struct stm32_pll_dt_cfg *pll = pdata->pll + i; 1162 char name[RCC_PLL_NAME_SIZE] = { }; 1163 int subnode = 0; 1164 1165 snprintf(name, sizeof(name), "st,pll-%u", i + 1); 1166 1167 subnode = fdt_subnode_offset(fdt, node, name); 1168 if (subnode < 0) 1169 continue; 1170 1171 if (clk_stm32_parse_pll_fdt(fdt, subnode, pll)) 1172 panic(); 1173 } 1174 1175 return 0; 1176 } 1177 1178 static int stm32_clk_parse_fdt_opp(const void *fdt, int node, 1179 const char *opp_name, 1180 struct stm32_clk_opp_cfg *opp_cfg) 1181 { 1182 int subnode = 0; 1183 int nb_opp = 0; 1184 int ret = 0; 1185 1186 node = fdt_subnode_offset(fdt, node, opp_name); 1187 if (node == -FDT_ERR_NOTFOUND) 1188 return 0; 1189 1190 if (node < 0) 1191 return node; 1192 1193 fdt_for_each_subnode(subnode, fdt, node) { 1194 assert(nb_opp <= MAX_OPP); 1195 1196 if (fdt_read_uint32(fdt, subnode, "hz", &opp_cfg->frq)) 1197 panic("hz property is mandatory"); 1198 1199 if (fdt_read_uint32(fdt, subnode, "st,clksrc", &opp_cfg->src)) 1200 panic("st,clksrc property is mandatory"); 1201 1202 ret = clk_stm32_parse_pll_fdt(fdt, subnode, &opp_cfg->pll_cfg); 1203 if (ret < 0) 1204 return ret; 1205 1206 opp_cfg++; 1207 nb_opp++; 1208 } 1209 1210 return 0; 1211 } 1212 1213 static int stm32_clk_parse_fdt_all_opp(const void *fdt, int node, 1214 struct stm32_clk_platdata *pdata) 1215 { 1216 struct stm32_clk_opp_dt_cfg *opp = pdata->opp; 1217 1218 node = fdt_subnode_offset(fdt, node, "st,clk_opp"); 1219 if (node == -FDT_ERR_NOTFOUND) 1220 return 0; 1221 1222 if (node < 0) 1223 return node; 1224 1225 return stm32_clk_parse_fdt_opp(fdt, node, "st,ck_cpu1", opp->cpu1_opp); 1226 } 1227 1228 static int stm32_clk_parse_fdt(const void *fdt, int node, 1229 struct stm32_clk_platdata *pdata) 1230 { 1231 const fdt32_t *cuint = NULL; 1232 unsigned int i = 0; 1233 int lenp = 0; 1234 int err = 0; 1235 1236 err = stm32_clk_parse_fdt_all_oscillator(fdt, node, pdata); 1237 if (err != 0) 1238 return err; 1239 1240 err = stm32_clk_parse_fdt_all_pll(fdt, node, pdata); 1241 if (err != 0) 1242 return err; 1243 1244 err = stm32_clk_parse_fdt_all_opp(fdt, node, pdata); 1245 if (err != 0) 1246 return err; 1247 1248 err = clk_stm32_parse_fdt_by_name(fdt, node, "st,busclk", 1249 pdata->busclk, 1250 &pdata->nbusclk); 1251 if (err != 0) 1252 return err; 1253 1254 err = clk_stm32_parse_fdt_by_name(fdt, node, "st,flexgen", 1255 pdata->flexgen, 1256 &pdata->nflexgen); 1257 if (err != 0) 1258 return err; 1259 1260 err = clk_stm32_parse_fdt_by_name(fdt, node, "st,kerclk", 1261 pdata->kernelclk, 1262 &pdata->nkernelclk); 1263 if (err != 0) 1264 return err; 1265 1266 pdata->c1msrd = fdt_read_uint32_default(fdt, node, "st,c1msrd", 0); 1267 1268 if (fdt_getprop(fdt, node, "st,safe_rst", NULL)) 1269 pdata->safe_rst = true; 1270 1271 pdata->rcc_base = stm32_rcc_base(); 1272 1273 cuint = fdt_getprop(fdt, node, "st,protreg", &lenp); 1274 if (lenp < 0) { 1275 if (lenp != -FDT_ERR_NOTFOUND) 1276 return lenp; 1277 1278 lenp = 0; 1279 DMSG("No RIF configuration available"); 1280 } 1281 1282 pdata->nb_res = (unsigned int)(lenp / sizeof(uint32_t)); 1283 1284 assert(pdata->nb_res <= RCC_NB_RIF_RES); 1285 1286 pdata->conf_data.cid_confs = calloc(RCC_NB_RIF_RES, sizeof(uint32_t)); 1287 pdata->conf_data.sec_conf = calloc(RCC_NB_CONFS, sizeof(uint32_t)); 1288 pdata->conf_data.priv_conf = calloc(RCC_NB_CONFS, sizeof(uint32_t)); 1289 pdata->conf_data.lock_conf = calloc(RCC_NB_CONFS, sizeof(uint32_t)); 1290 pdata->conf_data.access_mask = calloc(RCC_NB_CONFS, sizeof(uint32_t)); 1291 if (!pdata->conf_data.cid_confs || !pdata->conf_data.sec_conf || 1292 !pdata->conf_data.priv_conf || !pdata->conf_data.access_mask || 1293 !pdata->conf_data.lock_conf) 1294 panic("Missing memory capacity for RCC RIF configuration"); 1295 1296 for (i = 0; i < pdata->nb_res; i++) 1297 stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), &pdata->conf_data, 1298 RCC_NB_RIF_RES); 1299 1300 return 0; 1301 } 1302 1303 static void stm32mp2_a35_ss_on_hsi(void) 1304 { 1305 uint64_t timeout = 0; 1306 1307 /* Nothing to do if clock source is already set on bypass clock */ 1308 if (stm32mp_syscfg_read(A35SS_SSC_CHGCLKREQ) & 1309 A35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK) 1310 return; 1311 1312 stm32mp_syscfg_write(A35SS_SSC_CHGCLKREQ, 1313 A35SS_SSC_CHGCLKREQ_ARM_CHGCLKREQ_EN, 1314 A35SS_SSC_CHGCLKREQ_ARM_CHGCLKREQ_MASK); 1315 1316 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1317 while (!timeout_elapsed(timeout)) 1318 if (stm32mp_syscfg_read(A35SS_SSC_CHGCLKREQ) & 1319 A35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK) 1320 break; 1321 1322 if (!(stm32mp_syscfg_read(A35SS_SSC_CHGCLKREQ) & 1323 A35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK)) 1324 panic("Cannot switch A35 to bypass clock"); 1325 1326 stm32mp_syscfg_write(A35SS_SSC_PLL_EN, 1327 0, 1328 A35SS_SSC_PLL_ENABLE_NRESET_SWPLL_FF_MASK); 1329 } 1330 1331 static void stm32mp2_clk_xbar_on_hsi(struct clk_stm32_priv *priv) 1332 { 1333 uintptr_t xbar0cfgr = priv->base + RCC_XBAR0CFGR; 1334 uint32_t i = 0; 1335 1336 for (i = 0; i < XBAR_ROOT_CHANNEL_NB; i++) 1337 io_clrsetbits32(xbar0cfgr + (0x4 * i), 1338 RCC_XBAR0CFGR_XBAR0SEL_MASK, XBAR_SRC_HSI); 1339 } 1340 1341 static int stm32mp2_a35_pll1_start(void) 1342 { 1343 uint64_t timeout = 0; 1344 1345 stm32mp_syscfg_write(A35SS_SSC_PLL_EN, 1346 A35SS_SSC_PLL_ENABLE_PD_EN, 1347 A35SS_SSC_PLL_ENABLE_PD_EN); 1348 1349 /* Wait PLL lock */ 1350 timeout = timeout_init_us(PLLRDY_TIMEOUT); 1351 while (!timeout_elapsed(timeout)) 1352 if (stm32mp_syscfg_read(A35SS_SSC_PLL_EN) & 1353 A35SS_SSC_PLL_ENABLE_LOCKP_MASK) 1354 break; 1355 1356 if (!(stm32mp_syscfg_read(A35SS_SSC_PLL_EN) & 1357 A35SS_SSC_PLL_ENABLE_LOCKP_MASK)) { 1358 EMSG("PLL1 not locked"); 1359 return -1; 1360 } 1361 1362 /* De-assert reset on PLL output clock path */ 1363 stm32mp_syscfg_write(A35SS_SSC_PLL_EN, 1364 A35SS_SSC_PLL_ENABLE_NRESET_SWPLL_FF_EN, 1365 A35SS_SSC_PLL_ENABLE_NRESET_SWPLL_FF_MASK); 1366 1367 /* Switch CPU clock to PLL clock */ 1368 stm32mp_syscfg_write(A35SS_SSC_CHGCLKREQ, 1369 0, 1370 A35SS_SSC_CHGCLKREQ_ARM_CHGCLKREQ_MASK); 1371 1372 /* Wait for clock change acknowledge */ 1373 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1374 while (!timeout_elapsed(timeout)) 1375 if (!(stm32mp_syscfg_read(A35SS_SSC_CHGCLKREQ) & 1376 A35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK)) 1377 break; 1378 1379 if (stm32mp_syscfg_read(A35SS_SSC_CHGCLKREQ) & 1380 A35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK) { 1381 EMSG("A35 switch to PLL1 failed"); 1382 return -1; 1383 } 1384 1385 return 0; 1386 } 1387 1388 static void stm32mp2_a35_pll1_config(uint32_t fbdiv, uint32_t refdiv, 1389 uint32_t postdiv1, uint32_t postdiv2) 1390 { 1391 stm32mp_syscfg_write(A35SS_SSC_PLL_FREQ1, 1392 SHIFT_U32(refdiv, 1393 A35SS_SSC_PLL_FREQ1_REFDIV_SHIFT) | 1394 SHIFT_U32(fbdiv, A35SS_SSC_PLL_FREQ1_FBDIV_SHIFT), 1395 A35SS_SSC_PLL_FREQ1_MASK); 1396 1397 stm32mp_syscfg_write(A35SS_SSC_PLL_FREQ2, 1398 SHIFT_U32(postdiv1, 1399 A35SS_SSC_PLL_FREQ2_POSTDIV1_SHIFT) | 1400 SHIFT_U32(postdiv2, 1401 A35SS_SSC_PLL_FREQ2_POSTDIV2_SHIFT), 1402 A35SS_SSC_PLL_FREQ2_MASK); 1403 } 1404 1405 static void clk_stm32_pll_config_output(struct clk_stm32_priv *priv, 1406 const struct stm32_clk_pll *pll, 1407 uint32_t pllsrc, 1408 uint32_t *pllcfg, 1409 uint32_t fracv) 1410 { 1411 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 1412 uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2; 1413 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3; 1414 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4; 1415 uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6; 1416 uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7; 1417 int sel = (pllsrc & MUX_SEL_MASK) >> MUX_SEL_SHIFT; 1418 unsigned long refclk = clk_stm32_pll_get_oscillator_rate(sel); 1419 1420 if (fracv == 0) { 1421 /* PLL in integer mode */ 1422 1423 /* 1424 * No need to check max clock, as oscillator reference clocks 1425 * will always be less than 1.2GHz 1426 */ 1427 if (refclk < PLL_REFCLK_MIN) 1428 panic(); 1429 1430 io_clrbits32(pllxcfgr3, RCC_PLLxCFGR3_FRACIN_MASK); 1431 io_clrbits32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN); 1432 io_clrbits32(pllxcfgr3, RCC_PLLxCFGR3_DACEN); 1433 io_setbits32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS); 1434 io_setbits32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST); 1435 } else { 1436 /* PLL in frac mode */ 1437 1438 /* 1439 * No need to check max clock, as oscillator reference clocks 1440 * will always be less than 1.2GHz 1441 */ 1442 if (refclk < PLL_FRAC_REFCLK_MIN) 1443 panic(); 1444 1445 io_clrsetbits32(pllxcfgr3, RCC_PLLxCFGR3_FRACIN_MASK, 1446 fracv & RCC_PLLxCFGR3_FRACIN_MASK); 1447 io_setbits32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS); 1448 io_setbits32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN); 1449 } 1450 1451 assert(pllcfg[REFDIV]); 1452 1453 io_clrsetbits32(pllxcfgr2, RCC_PLLxCFGR2_FBDIV_MASK, 1454 SHIFT_U32(pllcfg[FBDIV], RCC_PLLxCFGR2_FBDIV_SHIFT) & 1455 RCC_PLLxCFGR2_FBDIV_MASK); 1456 io_clrsetbits32(pllxcfgr2, RCC_PLLxCFGR2_FREFDIV_MASK, 1457 pllcfg[REFDIV] & RCC_PLLxCFGR2_FREFDIV_MASK); 1458 io_clrsetbits32(pllxcfgr6, RCC_PLLxCFGR6_POSTDIV1_MASK, 1459 pllcfg[POSTDIV1] & RCC_PLLxCFGR6_POSTDIV1_MASK); 1460 io_clrsetbits32(pllxcfgr7, RCC_PLLxCFGR7_POSTDIV2_MASK, 1461 pllcfg[POSTDIV2] & RCC_PLLxCFGR7_POSTDIV2_MASK); 1462 1463 if (pllcfg[POSTDIV1] == 0 || pllcfg[POSTDIV2] == 0) { 1464 /* Bypass mode */ 1465 io_setbits32(pllxcfgr4, RCC_PLLxCFGR4_BYPASS); 1466 io_clrbits32(pllxcfgr4, RCC_PLLxCFGR4_FOUTPOSTDIVEN); 1467 } else { 1468 io_clrbits32(pllxcfgr4, RCC_PLLxCFGR4_BYPASS); 1469 io_setbits32(pllxcfgr4, RCC_PLLxCFGR4_FOUTPOSTDIVEN); 1470 } 1471 } 1472 1473 static void clk_stm32_pll_config_csg(struct clk_stm32_priv *priv, 1474 const struct stm32_clk_pll *pll, 1475 uint32_t *csg) 1476 { 1477 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 1478 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3; 1479 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4; 1480 uintptr_t pllxcfgr5 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR5; 1481 1482 io_clrsetbits32(pllxcfgr5, RCC_PLLxCFGR5_DIVVAL_MASK, 1483 csg[DIVVAL] & RCC_PLLxCFGR5_DIVVAL_MASK); 1484 io_clrsetbits32(pllxcfgr5, RCC_PLLxCFGR5_SPREAD_MASK, 1485 SHIFT_U32(csg[SPREAD], RCC_PLLxCFGR5_SPREAD_SHIFT) & 1486 RCC_PLLxCFGR5_SPREAD_MASK); 1487 1488 if (csg[DOWNSPREAD] != 0) 1489 io_setbits32(pllxcfgr3, RCC_PLLxCFGR3_DOWNSPREAD); 1490 else 1491 io_clrbits32(pllxcfgr3, RCC_PLLxCFGR3_DOWNSPREAD); 1492 1493 io_clrbits32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS); 1494 1495 io_clrbits32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN); 1496 udelay(1); 1497 1498 io_setbits32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN); 1499 io_setbits32(pllxcfgr3, RCC_PLLxCFGR3_DACEN); 1500 } 1501 1502 static struct stm32_pll_dt_cfg *clk_stm32_pll_get_pdata(unsigned int pll_idx) 1503 { 1504 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 1505 struct stm32_clk_platdata *pdata = priv->pdata; 1506 1507 assert(pll_idx < pdata->npll); 1508 1509 return &pdata->pll[pll_idx]; 1510 } 1511 1512 static int clk_stm32_pll_set_mux(struct clk_stm32_priv *priv __unused, 1513 uint32_t src) 1514 { 1515 int mux = (src & MUX_ID_MASK) >> MUX_ID_SHIFT; 1516 int sel = (src & MUX_SEL_MASK) >> MUX_SEL_SHIFT; 1517 1518 if (stm32_mux_set_parent(mux, sel)) 1519 return -1; 1520 else 1521 return 0; 1522 1523 } 1524 1525 static void clk_stm32_pll1_init(struct clk_stm32_priv *priv, 1526 int pll_idx __unused, 1527 struct stm32_pll_dt_cfg *pll_conf) 1528 { 1529 int sel = (pll_conf->src & MUX_SEL_MASK) >> MUX_SEL_SHIFT; 1530 unsigned long refclk = 0; 1531 1532 /* 1533 * TODO: check if pll has already good parameters or if we could make 1534 * a configuration on the fly. 1535 */ 1536 1537 stm32mp2_a35_ss_on_hsi(); 1538 1539 if (clk_stm32_pll_set_mux(priv, pll_conf->src)) 1540 panic(); 1541 1542 refclk = clk_stm32_pll_get_oscillator_rate(sel); 1543 1544 /* 1545 * No need to check max clock, as oscillator reference clocks will 1546 * always be less than 1.2GHz 1547 */ 1548 if (refclk < PLL_REFCLK_MIN) 1549 panic(); 1550 1551 stm32mp2_a35_pll1_config(pll_conf->cfg[FBDIV], 1552 pll_conf->cfg[REFDIV], 1553 pll_conf->cfg[POSTDIV1], 1554 pll_conf->cfg[POSTDIV2]); 1555 1556 if (stm32mp2_a35_pll1_start()) 1557 panic(); 1558 } 1559 1560 static void clk_stm32_pll_init(struct clk_stm32_priv *priv, int pll_idx, 1561 struct stm32_pll_dt_cfg *pll_conf) 1562 { 1563 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_idx); 1564 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1; 1565 bool spread_spectrum = false; 1566 1567 /* 1568 * TODO: check if pll has already good parameters or if we could make 1569 * a configuration on the fly. 1570 */ 1571 1572 if (stm32_gate_rdy_disable(pll->gate_id)) 1573 panic(); 1574 1575 if (clk_stm32_pll_set_mux(priv, pll_conf->src)) 1576 panic(); 1577 1578 clk_stm32_pll_config_output(priv, pll, pll_conf->src, 1579 pll_conf->cfg, pll_conf->frac); 1580 1581 if (pll_conf->csg_enabled) { 1582 clk_stm32_pll_config_csg(priv, pll, pll_conf->csg); 1583 spread_spectrum = true; 1584 } 1585 1586 if (stm32_gate_rdy_enable(pll->gate_id)) 1587 panic(); 1588 1589 if (spread_spectrum) 1590 io_clrbits32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST); 1591 } 1592 1593 static int stm32_clk_pll_configure(struct clk_stm32_priv *priv) 1594 { 1595 struct stm32_pll_dt_cfg *pll_conf = NULL; 1596 size_t i = 0; 1597 1598 for (i = 0; i < PLL_NB; i++) { 1599 pll_conf = clk_stm32_pll_get_pdata(i); 1600 1601 if (pll_conf->enabled) { 1602 /* Skip the pll3 (need GPU regulator to configure) */ 1603 if (i == PLL3_ID) 1604 continue; 1605 1606 /* Skip the pll2 (reserved to DDR) */ 1607 if (i == PLL2_ID) 1608 continue; 1609 1610 if (i == PLL1_ID) 1611 clk_stm32_pll1_init(priv, i, pll_conf); 1612 else 1613 clk_stm32_pll_init(priv, i, pll_conf); 1614 } 1615 } 1616 1617 return 0; 1618 } 1619 1620 #define __WORD_BIT 32 1621 1622 static int wait_predivsr(uint16_t channel) 1623 { 1624 uintptr_t rcc_base = stm32_rcc_base(); 1625 uintptr_t previvsr = 0; 1626 uint32_t channel_bit = 0; 1627 uint32_t value = 0; 1628 1629 if (channel < __WORD_BIT) { 1630 previvsr = rcc_base + RCC_PREDIVSR1; 1631 channel_bit = BIT(channel); 1632 } else { 1633 previvsr = rcc_base + RCC_PREDIVSR2; 1634 channel_bit = BIT(channel - __WORD_BIT); 1635 } 1636 1637 if (IO_READ32_POLL_TIMEOUT(previvsr, value, !(value & channel_bit), 0, 1638 CLKDIV_TIMEOUT)) { 1639 EMSG("Pre divider status: %#"PRIx32, io_read32(previvsr)); 1640 return -1; 1641 } 1642 1643 return 0; 1644 } 1645 1646 static int wait_findivsr(uint16_t channel) 1647 { 1648 uintptr_t rcc_base = stm32_rcc_base(); 1649 uintptr_t finvivsr = 0; 1650 uint32_t channel_bit = 0; 1651 uint32_t value = 0; 1652 1653 if (channel < __WORD_BIT) { 1654 finvivsr = rcc_base + RCC_FINDIVSR1; 1655 channel_bit = BIT(channel); 1656 } else { 1657 finvivsr = rcc_base + RCC_FINDIVSR2; 1658 channel_bit = BIT(channel - __WORD_BIT); 1659 } 1660 1661 if (IO_READ32_POLL_TIMEOUT(finvivsr, value, !(value & channel_bit), 0, 1662 CLKDIV_TIMEOUT)) { 1663 EMSG("Final divider status: %#"PRIx32, io_read32(finvivsr)); 1664 return -1; 1665 } 1666 1667 return 0; 1668 } 1669 1670 static int wait_xbar_sts(uint16_t channel) 1671 { 1672 uintptr_t rcc_base = stm32_rcc_base(); 1673 uintptr_t xbar_cfgr = rcc_base + RCC_XBAR0CFGR + (0x4 * channel); 1674 uint32_t value = 0; 1675 1676 if (IO_READ32_POLL_TIMEOUT(xbar_cfgr, value, 1677 !(value & RCC_XBAR0CFGR_XBAR0STS), 0, 1678 CLKDIV_TIMEOUT)) { 1679 EMSG("XBAR%"PRIu16"CFGR: %#"PRIx32, channel, 1680 io_read32(xbar_cfgr)); 1681 return -1; 1682 } 1683 1684 return 0; 1685 } 1686 1687 static TEE_Result flexclkgen_search_config(uint16_t channel, 1688 unsigned int *clk_src, 1689 unsigned int *prediv, 1690 unsigned int *findiv) 1691 { 1692 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 1693 struct stm32_clk_platdata *pdata = priv->pdata; 1694 unsigned int flex_id = U(0); 1695 uint32_t dt_cfg = U(0); 1696 uint32_t i = U(0); 1697 1698 assert(clk_src && prediv && findiv); 1699 1700 /* 1701 * pdata->flexgen is the array of all the flexgen configuration from 1702 * the device tree. 1703 * The binding does not enforce the description of all flexgen nor 1704 * the order it which they are listed. 1705 */ 1706 for (i = 0; i < pdata->nflexgen; i++) { 1707 dt_cfg = pdata->flexgen[i]; 1708 1709 flex_id = (dt_cfg & FLEX_ID_MASK) >> FLEX_ID_SHIFT; 1710 if (flex_id == channel) { 1711 *clk_src = (dt_cfg & FLEX_SEL_MASK) >> FLEX_SEL_SHIFT; 1712 *prediv = (dt_cfg & FLEX_PDIV_MASK) >> FLEX_PDIV_SHIFT; 1713 *findiv = (dt_cfg & FLEX_FDIV_MASK) >> FLEX_FDIV_SHIFT; 1714 1715 return TEE_SUCCESS; 1716 } 1717 } 1718 1719 return TEE_ERROR_ITEM_NOT_FOUND; 1720 } 1721 1722 static void flexclkgen_config_channel(uint16_t channel, unsigned int clk_src, 1723 unsigned int prediv, unsigned int findiv) 1724 { 1725 uintptr_t rcc_base = stm32_rcc_base(); 1726 1727 if (wait_predivsr(channel) != 0) 1728 panic(); 1729 1730 io_clrsetbits32(rcc_base + RCC_PREDIV0CFGR + (0x4 * channel), 1731 RCC_PREDIV0CFGR_PREDIV0_MASK, prediv); 1732 1733 if (wait_predivsr(channel) != 0) 1734 panic(); 1735 1736 if (wait_findivsr(channel) != 0) 1737 panic(); 1738 1739 io_clrsetbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel), 1740 RCC_FINDIV0CFGR_FINDIV0_MASK, 1741 findiv); 1742 1743 if (wait_findivsr(channel) != 0) 1744 panic(); 1745 1746 if (wait_xbar_sts(channel) != 0) 1747 panic(); 1748 1749 io_clrsetbits32(rcc_base + RCC_XBAR0CFGR + (0x4 * channel), 1750 RCC_XBAR0CFGR_XBAR0SEL_MASK, 1751 clk_src); 1752 1753 io_setbits32(rcc_base + RCC_XBAR0CFGR + (0x4 * channel), 1754 RCC_XBAR0CFGR_XBAR0EN); 1755 1756 if (wait_xbar_sts(channel) != 0) 1757 panic(); 1758 } 1759 1760 static int stm32mp2_clk_flexgen_configure(struct clk_stm32_priv *priv) 1761 { 1762 struct stm32_clk_platdata *pdata = priv->pdata; 1763 uint32_t i = 0; 1764 1765 for (i = 0; i < pdata->nflexgen; i++) { 1766 uint32_t val = pdata->flexgen[i]; 1767 uint32_t cmd = 0; 1768 uint32_t cmd_data = 0; 1769 unsigned int channel = 0; 1770 unsigned int clk_src = 0; 1771 unsigned int pdiv = 0; 1772 unsigned int fdiv = 0; 1773 1774 cmd = (val & CMD_MASK) >> CMD_SHIFT; 1775 cmd_data = val & ~CMD_MASK; 1776 1777 if (cmd != CMD_FLEXGEN) 1778 continue; 1779 1780 channel = (cmd_data & FLEX_ID_MASK) >> FLEX_ID_SHIFT; 1781 1782 /* 1783 * Skip ck_ker_stgen configuration, will be done by 1784 * stgen driver. 1785 */ 1786 if (channel == FLEX_STGEN) 1787 continue; 1788 1789 clk_src = (cmd_data & FLEX_SEL_MASK) >> FLEX_SEL_SHIFT; 1790 pdiv = (cmd_data & FLEX_PDIV_MASK) >> FLEX_PDIV_SHIFT; 1791 fdiv = (cmd_data & FLEX_FDIV_MASK) >> FLEX_FDIV_SHIFT; 1792 1793 flexclkgen_config_channel(channel, clk_src, pdiv, fdiv); 1794 } 1795 1796 return 0; 1797 } 1798 1799 static int stm32_clk_configure_div(struct clk_stm32_priv *priv __unused, 1800 uint32_t data) 1801 { 1802 uint32_t div_id = 0; 1803 uint32_t div_n = 0; 1804 1805 div_id = (data & DIV_ID_MASK) >> DIV_ID_SHIFT; 1806 div_n = (data & DIV_DIVN_MASK) >> DIV_DIVN_SHIFT; 1807 1808 return stm32_div_set_value(div_id, div_n); 1809 } 1810 1811 static int stm32_clk_configure_mux(struct clk_stm32_priv *priv __unused, 1812 uint32_t data) 1813 { 1814 int mux = (data & MUX_ID_MASK) >> MUX_ID_SHIFT; 1815 int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT; 1816 1817 if (stm32_mux_set_parent(mux, sel)) 1818 return -1; 1819 else 1820 return 0; 1821 } 1822 1823 static int stm32_clk_configure_by_addr_val(struct clk_stm32_priv *priv, 1824 uint32_t data) 1825 { 1826 uint32_t addr = data >> CLK_ADDR_SHIFT; 1827 uint32_t val = data & CLK_ADDR_VAL_MASK; 1828 1829 io_setbits32(priv->base + addr, val); 1830 1831 return 0; 1832 } 1833 1834 static void stm32_clk_configure_obs(struct clk_stm32_priv *priv, 1835 uint32_t data) 1836 { 1837 uint32_t id = (data & OBS_ID_MASK) >> OBS_ID_SHIFT; 1838 uint32_t status = (data & OBS_STATUS_MASK) >> OBS_STATUS_SHIFT; 1839 uint32_t int_ext = (data & OBS_INTEXT_MASK) >> OBS_INTEXT_SHIFT; 1840 uint32_t div = (data & OBS_DIV_MASK) >> OBS_DIV_SHIFT; 1841 uint32_t inv = (data & OBS_INV_MASK) >> OBS_INV_SHIFT; 1842 uint32_t sel = (data & OBS_SEL_MASK) >> OBS_SEL_SHIFT; 1843 uint32_t reg = 0; 1844 uint32_t val = 0; 1845 1846 if (!id) 1847 reg = RCC_FCALCOBS0CFGR; 1848 else 1849 reg = RCC_FCALCOBS1CFGR; 1850 1851 if (status) 1852 val |= RCC_FCALCOBS0CFGR_CKOBSEN; 1853 1854 if (int_ext == OBS_EXT) { 1855 val |= RCC_FCALCOBS0CFGR_CKOBSEXTSEL; 1856 val |= SHIFT_U32(sel, RCC_FCALCOBS0CFGR_CKEXTSEL_SHIFT); 1857 } else { 1858 val |= SHIFT_U32(sel, RCC_FCALCOBS0CFGR_CKINTSEL_SHIFT); 1859 } 1860 1861 if (inv) 1862 val |= RCC_FCALCOBS0CFGR_CKOBSINV; 1863 1864 val |= SHIFT_U32(div, RCC_FCALCOBS0CFGR_CKOBSDIV_SHIFT); 1865 1866 io_write32(priv->base + reg, val); 1867 } 1868 1869 static int stm32_clk_configure(struct clk_stm32_priv *priv, uint32_t val) 1870 { 1871 uint32_t cmd_data = 0; 1872 uint32_t cmd = 0; 1873 int ret = 0; 1874 1875 if (val & CMD_ADDR_BIT) { 1876 cmd_data = val & ~CMD_ADDR_BIT; 1877 1878 return stm32_clk_configure_by_addr_val(priv, cmd_data); 1879 } 1880 1881 cmd = (val & CMD_MASK) >> CMD_SHIFT; 1882 cmd_data = val & ~CMD_MASK; 1883 1884 switch (cmd) { 1885 case CMD_DIV: 1886 ret = stm32_clk_configure_div(priv, cmd_data); 1887 break; 1888 1889 case CMD_MUX: 1890 ret = stm32_clk_configure_mux(priv, cmd_data); 1891 break; 1892 1893 case CMD_OBS: 1894 stm32_clk_configure_obs(priv, cmd_data); 1895 break; 1896 1897 default: 1898 EMSG("cmd unknown ! : %#"PRIx32, val); 1899 ret = -1; 1900 } 1901 1902 return ret; 1903 } 1904 1905 static int stm32_clk_bus_configure(struct clk_stm32_priv *priv) 1906 { 1907 struct stm32_clk_platdata *pdata = priv->pdata; 1908 uint32_t i = 0; 1909 1910 for (i = 0; i < pdata->nbusclk; i++) { 1911 int ret = 0; 1912 1913 ret = stm32_clk_configure(priv, pdata->busclk[i]); 1914 if (ret != 0) 1915 return ret; 1916 } 1917 1918 return 0; 1919 } 1920 1921 static int stm32_clk_kernel_configure(struct clk_stm32_priv *priv) 1922 { 1923 struct stm32_clk_platdata *pdata = priv->pdata; 1924 uint32_t i = 0; 1925 1926 for (i = 0; i < pdata->nkernelclk; i++) { 1927 int ret = 0; 1928 1929 ret = stm32_clk_configure(priv, pdata->kernelclk[i]); 1930 if (ret != 0) 1931 return ret; 1932 } 1933 1934 return 0; 1935 } 1936 1937 static void stm32mp2_init_clock_tree(struct clk_stm32_priv *priv, 1938 struct stm32_clk_platdata *pdata) 1939 { 1940 stm32_clk_oscillators_enable(priv, pdata); 1941 1942 /* Come back to HSI for flexgen */ 1943 stm32mp2_clk_xbar_on_hsi(priv); 1944 1945 if (stm32_clk_pll_configure(priv)) 1946 panic("Cannot configure plls"); 1947 1948 /* Wait LSE ready before to use it */ 1949 if (stm32_clk_oscillators_wait_lse_ready(priv, pdata)) 1950 panic("Timeout: to enable LSE"); 1951 1952 if (stm32mp2_clk_flexgen_configure(priv)) 1953 panic("Cannot configure flexgen"); 1954 1955 if (stm32_clk_bus_configure(priv)) 1956 panic("Cannot config bus clocks"); 1957 1958 if (stm32_clk_kernel_configure(priv)) 1959 panic("Cannot configure kernel clocks"); 1960 1961 /* Configure LSE css after RTC source configuration */ 1962 stm32_clk_oscillators_lse_set_css(priv, pdata); 1963 } 1964 1965 static TEE_Result clk_stm32_osc_enable(struct clk *clk) 1966 { 1967 return clk_stm32_gate_ready_ops.enable(clk); 1968 } 1969 1970 static void clk_stm32_osc_disable(struct clk *clk) 1971 { 1972 clk_stm32_gate_ready_ops.disable(clk); 1973 } 1974 1975 static const struct clk_ops clk_stm32_osc_ops = { 1976 .enable = clk_stm32_osc_enable, 1977 .disable = clk_stm32_osc_disable, 1978 }; 1979 1980 static unsigned long clk_stm32_msi_get_rate(struct clk *clk __unused, 1981 unsigned long prate __unused) 1982 { 1983 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 1984 uintptr_t address = priv->base + RCC_BDCR; 1985 1986 if ((io_read32(address) & RCC_BDCR_MSIFREQSEL)) 1987 return RCC_16_MHZ; 1988 1989 return RCC_4_MHZ; 1990 } 1991 1992 static TEE_Result clk_stm32_msi_set_rate(struct clk *clk __unused, 1993 unsigned long rate, 1994 unsigned long prate __unused) 1995 { 1996 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 1997 1998 return clk_stm32_osc_msi_set_rate(priv, rate); 1999 } 2000 2001 static const struct clk_ops clk_stm32_oscillator_msi_ops = { 2002 .enable = clk_stm32_osc_enable, 2003 .disable = clk_stm32_osc_disable, 2004 .get_rate = clk_stm32_msi_get_rate, 2005 .set_rate = clk_stm32_msi_set_rate, 2006 }; 2007 2008 static TEE_Result clk_stm32_hse_div_set_rate(struct clk *clk, 2009 unsigned long rate, 2010 unsigned long parent_rate) 2011 { 2012 return clk_stm32_divider_set_rate(clk, rate, parent_rate); 2013 } 2014 2015 static const struct clk_ops clk_stm32_hse_div_ops = { 2016 .get_rate = clk_stm32_divider_get_rate, 2017 .set_rate = clk_stm32_hse_div_set_rate, 2018 }; 2019 2020 static TEE_Result clk_stm32_hsediv2_enable(struct clk *clk) 2021 { 2022 return clk_stm32_gate_ops.enable(clk); 2023 } 2024 2025 static void clk_stm32_hsediv2_disable(struct clk *clk) 2026 { 2027 clk_stm32_gate_ops.disable(clk); 2028 } 2029 2030 static unsigned long clk_stm32_hsediv2_get_rate(struct clk *clk __unused, 2031 unsigned long prate) 2032 { 2033 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 2034 uintptr_t addr = priv->base + RCC_OCENSETR; 2035 2036 if (io_read32(addr) & RCC_OCENSETR_HSEDIV2BYP) 2037 return prate; 2038 2039 return prate / 2; 2040 } 2041 2042 static const struct clk_ops clk_hsediv2_ops = { 2043 .enable = clk_stm32_hsediv2_enable, 2044 .disable = clk_stm32_hsediv2_disable, 2045 .get_rate = clk_stm32_hsediv2_get_rate, 2046 }; 2047 2048 struct clk_stm32_pll_cfg { 2049 uint32_t pll_offset; 2050 int gate_id; 2051 int mux_id; 2052 }; 2053 2054 static unsigned long clk_get_pll1_fvco_rate(unsigned long refclk) 2055 { 2056 uint32_t reg = stm32mp_syscfg_read(A35SS_SSC_PLL_FREQ1); 2057 uint32_t fbdiv = 0; 2058 uint32_t refdiv = 0; 2059 unsigned long freq = 0; 2060 2061 fbdiv = (reg & A35SS_SSC_PLL_FREQ1_FBDIV_MASK) >> 2062 A35SS_SSC_PLL_FREQ1_FBDIV_SHIFT; 2063 2064 refdiv = (reg & A35SS_SSC_PLL_FREQ1_REFDIV_MASK) >> 2065 A35SS_SSC_PLL_FREQ1_REFDIV_SHIFT; 2066 2067 if (!refdiv || MUL_OVERFLOW(refclk, fbdiv, &freq)) 2068 panic(); 2069 2070 return freq / refdiv; 2071 } 2072 2073 static unsigned long clk_stm32_pll1_get_rate(struct clk *clk __unused, 2074 unsigned long prate) 2075 { 2076 uint32_t reg = stm32mp_syscfg_read(A35SS_SSC_PLL_FREQ2); 2077 unsigned long dfout = 0; 2078 uint32_t postdiv1 = 0; 2079 uint32_t postdiv2 = 0; 2080 2081 postdiv1 = (reg & A35SS_SSC_PLL_FREQ2_POSTDIV1_MASK) >> 2082 A35SS_SSC_PLL_FREQ2_POSTDIV1_SHIFT; 2083 2084 postdiv2 = (reg & A35SS_SSC_PLL_FREQ2_POSTDIV2_MASK) >> 2085 A35SS_SSC_PLL_FREQ2_POSTDIV2_SHIFT; 2086 2087 if (postdiv1 == 0 || postdiv2 == 0) 2088 dfout = prate; 2089 else 2090 dfout = clk_get_pll1_fvco_rate(prate) / (postdiv1 * postdiv2); 2091 2092 return dfout; 2093 } 2094 2095 static struct stm32_clk_opp_cfg * 2096 clk_stm32_get_opp_config(struct stm32_clk_opp_cfg *opp_cfg, unsigned long rate) 2097 { 2098 unsigned int i = 0; 2099 2100 for (i = 0; i < MAX_OPP && opp_cfg->frq; i++, opp_cfg++) 2101 if (opp_cfg->frq == rate) 2102 return opp_cfg; 2103 2104 return NULL; 2105 } 2106 2107 static TEE_Result clk_stm32_pll1_set_rate(struct clk *clk __unused, 2108 unsigned long rate, 2109 unsigned long parent_rate __unused) 2110 { 2111 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 2112 struct stm32_clk_platdata *pdata = priv->pdata; 2113 struct stm32_pll_dt_cfg *pll_conf = NULL; 2114 struct stm32_clk_opp_cfg *opp = NULL; 2115 2116 opp = clk_stm32_get_opp_config(pdata->opp->cpu1_opp, rate); 2117 if (!opp) 2118 return TEE_ERROR_GENERIC; 2119 2120 pll_conf = &opp->pll_cfg; 2121 2122 clk_stm32_pll1_init(priv, PLL1_ID, pll_conf); 2123 2124 return TEE_SUCCESS; 2125 } 2126 2127 static size_t clk_stm32_pll_get_parent(struct clk *clk) 2128 { 2129 struct clk_stm32_pll_cfg *cfg = clk->priv; 2130 2131 return stm32_mux_get_parent(cfg->mux_id); 2132 } 2133 2134 static const struct clk_ops clk_stm32_pll1_ops = { 2135 .get_parent = clk_stm32_pll_get_parent, 2136 .get_rate = clk_stm32_pll1_get_rate, 2137 .set_rate = clk_stm32_pll1_set_rate, 2138 }; 2139 2140 static unsigned long clk_get_pll_fvco(uint32_t offset_base, 2141 unsigned long prate) 2142 { 2143 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 2144 uintptr_t pllxcfgr1 = priv->base + offset_base; 2145 uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2; 2146 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3; 2147 unsigned long fvco = 0; 2148 uint32_t fracin = 0; 2149 uint32_t fbdiv = 0; 2150 uint32_t refdiv = 0; 2151 2152 fracin = io_read32(pllxcfgr3) & RCC_PLLxCFGR3_FRACIN_MASK; 2153 fbdiv = (io_read32(pllxcfgr2) & RCC_PLLxCFGR2_FBDIV_MASK) >> 2154 RCC_PLLxCFGR2_FBDIV_SHIFT; 2155 2156 refdiv = io_read32(pllxcfgr2) & RCC_PLLxCFGR2_FREFDIV_MASK; 2157 2158 assert(refdiv); 2159 2160 if (fracin) { 2161 unsigned long long numerator = 0; 2162 unsigned long long denominator = 0; 2163 2164 numerator = SHIFT_U64(fbdiv, 24) + fracin; 2165 numerator = prate * numerator; 2166 denominator = SHIFT_U64(refdiv, 24); 2167 fvco = (unsigned long)(numerator / denominator); 2168 } else { 2169 fvco = (unsigned long)(prate * fbdiv / refdiv); 2170 } 2171 2172 return fvco; 2173 } 2174 2175 static unsigned long clk_stm32_pll_get_rate(struct clk *clk __unused, 2176 unsigned long prate) 2177 { 2178 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 2179 struct clk_stm32_pll_cfg *cfg = clk->priv; 2180 uintptr_t pllxcfgr1 = priv->base + cfg->pll_offset; 2181 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4; 2182 uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6; 2183 uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7; 2184 unsigned long dfout = 0; 2185 uint32_t postdiv1 = 0; 2186 uint32_t postdiv2 = 0; 2187 2188 postdiv1 = io_read32(pllxcfgr6) & RCC_PLLxCFGR6_POSTDIV1_MASK; 2189 postdiv2 = io_read32(pllxcfgr7) & RCC_PLLxCFGR7_POSTDIV2_MASK; 2190 2191 if ((io_read32(pllxcfgr4) & RCC_PLLxCFGR4_BYPASS) || 2192 !postdiv1 || !postdiv2) 2193 dfout = prate; 2194 else 2195 dfout = clk_get_pll_fvco(cfg->pll_offset, 2196 prate) / (postdiv1 * postdiv2); 2197 2198 return dfout; 2199 } 2200 2201 static TEE_Result clk_stm32_pll_enable(struct clk *clk) 2202 { 2203 struct clk_stm32_pll_cfg *cfg = clk->priv; 2204 2205 if (stm32_gate_rdy_enable(cfg->gate_id)) { 2206 EMSG("%s timeout", clk_get_name(clk)); 2207 return TEE_ERROR_TIMEOUT; 2208 } 2209 2210 return TEE_SUCCESS; 2211 } 2212 2213 static void clk_stm32_pll_disable(struct clk *clk) 2214 { 2215 struct clk_stm32_pll_cfg *cfg = clk->priv; 2216 2217 if (stm32_gate_rdy_disable(cfg->gate_id)) { 2218 EMSG("%s timeout", clk_get_name(clk)); 2219 panic(); 2220 } 2221 } 2222 2223 static const struct clk_ops clk_stm32_pll_ops = { 2224 .get_parent = clk_stm32_pll_get_parent, 2225 .get_rate = clk_stm32_pll_get_rate, 2226 .enable = clk_stm32_pll_enable, 2227 .disable = clk_stm32_pll_disable, 2228 }; 2229 2230 static TEE_Result clk_stm32_pll3_enable(struct clk *clk) 2231 { 2232 struct clk_stm32_pll_cfg *cfg = clk->priv; 2233 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 2234 struct stm32_pll_dt_cfg *pll_conf = clk_stm32_pll_get_pdata(PLL3_ID); 2235 struct clk *parent = NULL; 2236 size_t pidx = 0; 2237 2238 /* ck_icn_p_gpu activate */ 2239 stm32_gate_enable(GATE_GPU); 2240 2241 clk_stm32_pll_init(priv, PLL3_ID, pll_conf); 2242 2243 if (stm32_gate_rdy_enable(cfg->gate_id)) { 2244 EMSG("%s timeout", clk_get_name(clk)); 2245 return TEE_ERROR_TIMEOUT; 2246 } 2247 2248 /* Update parent */ 2249 pidx = clk_stm32_pll_get_parent(clk); 2250 parent = clk_get_parent_by_index(clk, pidx); 2251 2252 clk->parent = parent; 2253 2254 return TEE_SUCCESS; 2255 } 2256 2257 static void clk_stm32_pll3_disable(struct clk *clk) 2258 { 2259 clk_stm32_pll_disable(clk); 2260 stm32_gate_disable(GATE_GPU); 2261 } 2262 2263 static const struct clk_ops clk_stm32_pll3_ops = { 2264 .get_parent = clk_stm32_pll_get_parent, 2265 .get_rate = clk_stm32_pll_get_rate, 2266 .enable = clk_stm32_pll3_enable, 2267 .disable = clk_stm32_pll3_disable, 2268 }; 2269 2270 struct clk_stm32_flexgen_cfg { 2271 int flex_id; 2272 }; 2273 2274 static size_t clk_stm32_flexgen_get_parent(struct clk *clk) 2275 { 2276 struct clk_stm32_flexgen_cfg *cfg = clk->priv; 2277 uintptr_t rcc_base = clk_stm32_get_rcc_base(); 2278 uint32_t address = 0; 2279 2280 address = rcc_base + RCC_XBAR0CFGR + (cfg->flex_id * 4); 2281 2282 return io_read32(address) & RCC_XBAR0CFGR_XBAR0SEL_MASK; 2283 } 2284 2285 static TEE_Result clk_stm32_flexgen_set_parent(struct clk *clk, size_t pidx) 2286 { 2287 uintptr_t rcc_base = clk_stm32_get_rcc_base(); 2288 struct clk_stm32_flexgen_cfg *cfg = clk->priv; 2289 uint16_t channel = cfg->flex_id * 4; 2290 2291 io_clrsetbits32(rcc_base + RCC_XBAR0CFGR + (channel), 2292 RCC_XBAR0CFGR_XBAR0SEL_MASK, pidx); 2293 2294 if (wait_xbar_sts(channel)) 2295 return TEE_ERROR_GENERIC; 2296 2297 return TEE_SUCCESS; 2298 } 2299 2300 static unsigned long clk_stm32_flexgen_get_rate(struct clk *clk __unused, 2301 unsigned long prate) 2302 { 2303 struct clk_stm32_flexgen_cfg *cfg = clk->priv; 2304 uintptr_t rcc_base = clk_stm32_get_rcc_base(); 2305 uint32_t prediv = 0; 2306 uint32_t findiv = 0; 2307 uint8_t channel = cfg->flex_id; 2308 unsigned long freq = prate; 2309 2310 prediv = io_read32(rcc_base + RCC_PREDIV0CFGR + (0x4 * channel)) & 2311 RCC_PREDIV0CFGR_PREDIV0_MASK; 2312 findiv = io_read32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel)) & 2313 RCC_FINDIV0CFGR_FINDIV0_MASK; 2314 2315 if (freq == 0) 2316 return 0; 2317 2318 switch (prediv) { 2319 case 0x0: 2320 break; 2321 2322 case 0x1: 2323 freq /= 2; 2324 break; 2325 2326 case 0x3: 2327 freq /= 4; 2328 break; 2329 2330 case 0x3FF: 2331 freq /= 1024; 2332 break; 2333 2334 default: 2335 EMSG("Unsupported PREDIV value (%#"PRIx32")", prediv); 2336 panic(); 2337 break; 2338 } 2339 2340 freq /= findiv + 1; 2341 2342 return freq; 2343 } 2344 2345 static unsigned long clk_stm32_flexgen_get_round_rate(unsigned long rate, 2346 unsigned long prate, 2347 unsigned int *prediv, 2348 unsigned int *findiv) 2349 { 2350 unsigned int pre_val[] = { 0x0, 0x1, 0x3, 0x3FF }; 2351 unsigned int pre_div[] = { 1, 2, 4, 1024 }; 2352 long best_diff = LONG_MAX; 2353 unsigned int i = 0; 2354 2355 *prediv = 0; 2356 *findiv = 0; 2357 2358 for (i = 0; i < ARRAY_SIZE(pre_div); i++) { 2359 unsigned long freq = 0; 2360 unsigned long ratio = 0; 2361 long diff = 0L; 2362 2363 freq = UDIV_ROUND_NEAREST((uint64_t)prate, pre_div[i]); 2364 ratio = UDIV_ROUND_NEAREST((uint64_t)freq, rate); 2365 2366 if (ratio == 0) 2367 ratio = 1; 2368 else if (ratio > 64) 2369 ratio = 64; 2370 2371 freq = UDIV_ROUND_NEAREST((uint64_t)freq, ratio); 2372 if (freq < rate) 2373 diff = rate - freq; 2374 else 2375 diff = freq - rate; 2376 2377 if (diff < best_diff) { 2378 best_diff = diff; 2379 *prediv = pre_val[i]; 2380 *findiv = ratio - 1; 2381 2382 if (diff == 0) 2383 break; 2384 } 2385 } 2386 2387 return (prate / (*prediv + 1)) / (*findiv + 1); 2388 } 2389 2390 static TEE_Result clk_stm32_flexgen_set_rate(struct clk *clk, 2391 unsigned long rate, 2392 unsigned long parent_rate) 2393 { 2394 struct clk_stm32_flexgen_cfg *cfg = clk->priv; 2395 uint8_t channel = cfg->flex_id; 2396 uintptr_t rcc_base = stm32_rcc_base(); 2397 unsigned int prediv = 0; 2398 unsigned int findiv = 0; 2399 2400 clk_stm32_flexgen_get_round_rate(rate, parent_rate, &prediv, &findiv); 2401 2402 if (wait_predivsr(channel) != 0) 2403 panic(); 2404 2405 io_clrsetbits32(rcc_base + RCC_PREDIV0CFGR + (0x4 * channel), 2406 RCC_PREDIV0CFGR_PREDIV0_MASK, 2407 prediv); 2408 2409 if (wait_predivsr(channel) != 0) 2410 panic(); 2411 2412 if (wait_findivsr(channel) != 0) 2413 panic(); 2414 2415 io_clrsetbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel), 2416 RCC_FINDIV0CFGR_FINDIV0_MASK, 2417 findiv); 2418 2419 if (wait_findivsr(channel) != 0) 2420 panic(); 2421 2422 return TEE_SUCCESS; 2423 } 2424 2425 static TEE_Result clk_stm32_flexgen_enable(struct clk *clk) 2426 { 2427 struct clk_stm32_flexgen_cfg *cfg = clk->priv; 2428 uintptr_t rcc_base = clk_stm32_get_rcc_base(); 2429 TEE_Result ret = TEE_ERROR_GENERIC; 2430 uint8_t channel = cfg->flex_id; 2431 2432 /* 2433 * Configure flexgen of STGEN since it has been skipped during 2434 * flexgen configuration. 2435 */ 2436 if (channel == FLEX_STGEN) { 2437 unsigned int clk_src = U(0); 2438 unsigned int pdiv = U(0); 2439 unsigned int fdiv = U(0); 2440 2441 ret = flexclkgen_search_config(channel, &clk_src, &pdiv, &fdiv); 2442 if (ret) { 2443 EMSG("Error %#"PRIx32" when getting STGEN flexgen conf", 2444 ret); 2445 return ret; 2446 } 2447 2448 flexclkgen_config_channel(channel, clk_src, pdiv, fdiv); 2449 2450 /* Update parent */ 2451 clk->parent = clk_get_parent_by_index(clk, clk_src); 2452 } 2453 2454 io_setbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel), 2455 RCC_FINDIV0CFGR_FINDIV0EN); 2456 2457 return TEE_SUCCESS; 2458 } 2459 2460 static void clk_stm32_flexgen_disable(struct clk *clk) 2461 { 2462 struct clk_stm32_flexgen_cfg *cfg = clk->priv; 2463 uintptr_t rcc_base = clk_stm32_get_rcc_base(); 2464 uint8_t channel = cfg->flex_id; 2465 2466 io_clrbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel), 2467 RCC_FINDIV0CFGR_FINDIV0EN); 2468 } 2469 2470 static const struct clk_ops clk_stm32_flexgen_ops = { 2471 .get_rate = clk_stm32_flexgen_get_rate, 2472 .set_rate = clk_stm32_flexgen_set_rate, 2473 .get_parent = clk_stm32_flexgen_get_parent, 2474 .set_parent = clk_stm32_flexgen_set_parent, 2475 .enable = clk_stm32_flexgen_enable, 2476 .disable = clk_stm32_flexgen_disable, 2477 }; 2478 2479 static size_t clk_cpu1_get_parent(struct clk *clk __unused) 2480 { 2481 uint32_t reg = stm32mp_syscfg_read(A35SS_SSC_CHGCLKREQ); 2482 2483 return (reg & A35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK) >> 2484 A35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_SHIFT; 2485 } 2486 2487 static const struct clk_ops clk_stm32_cpu1_ops = { 2488 .get_parent = clk_cpu1_get_parent, 2489 }; 2490 2491 #define APB_DIV_MASK GENMASK_32(2, 0) 2492 #define TIM_PRE_MASK BIT(0) 2493 2494 static unsigned long ck_timer_get_rate_ops(struct clk *clk, unsigned long prate) 2495 { 2496 struct clk_stm32_timer_cfg *cfg = clk->priv; 2497 uintptr_t rcc_base = clk_stm32_get_rcc_base(); 2498 uint32_t prescaler = 0; 2499 uint32_t timpre = 0; 2500 2501 prescaler = io_read32(rcc_base + cfg->apbdiv) & APB_DIV_MASK; 2502 2503 timpre = io_read32(rcc_base + cfg->timpre) & TIM_PRE_MASK; 2504 2505 if (prescaler == 0) 2506 return prate; 2507 2508 return prate * (timpre + 1) * 2; 2509 }; 2510 2511 static const struct clk_ops ck_timer_ops = { 2512 .get_rate = ck_timer_get_rate_ops, 2513 }; 2514 2515 #define PLL_PARENTS { &ck_hsi, &ck_hse, &ck_msi } 2516 #define PLL_NUM_PATENTS 3 2517 2518 #define STM32_OSC(_name, _flags, _gate_id)\ 2519 struct clk _name = {\ 2520 .ops = &clk_stm32_osc_ops,\ 2521 .priv = &(struct clk_stm32_gate_cfg){\ 2522 .gate_id = (_gate_id),\ 2523 },\ 2524 .name = #_name,\ 2525 .flags = (_flags),\ 2526 .num_parents = 1,\ 2527 .parents = { NULL },\ 2528 } 2529 2530 #define STM32_OSC_MSI(_name, _flags, _gate_id)\ 2531 struct clk _name = {\ 2532 .ops = &clk_stm32_oscillator_msi_ops,\ 2533 .priv = &(struct clk_stm32_gate_cfg){\ 2534 .gate_id = (_gate_id),\ 2535 },\ 2536 .name = #_name,\ 2537 .flags = (_flags),\ 2538 .num_parents = 1,\ 2539 .parents = { NULL },\ 2540 } 2541 2542 #define STM32_HSE_DIV2(_name, _parent, _flags, _gate_id)\ 2543 struct clk _name = {\ 2544 .ops = &clk_hsediv2_ops,\ 2545 .priv = &(struct clk_stm32_gate_cfg){\ 2546 .gate_id = (_gate_id),\ 2547 },\ 2548 .name = #_name,\ 2549 .flags = (_flags),\ 2550 .num_parents = 1,\ 2551 .parents = { (_parent) },\ 2552 } 2553 2554 #define STM32_HSE_RTC(_name, _parent, _flags, _div_id)\ 2555 struct clk _name = {\ 2556 .ops = &clk_stm32_hse_div_ops,\ 2557 .priv = &(struct clk_stm32_div_cfg){\ 2558 .div_id = (_div_id),\ 2559 },\ 2560 .name = #_name,\ 2561 .flags = (_flags),\ 2562 .num_parents = 1,\ 2563 .parents = { (_parent) },\ 2564 } 2565 2566 #define STM32_PLL1(_name, _flags, _mux_id)\ 2567 struct clk _name = {\ 2568 .ops = &clk_stm32_pll1_ops,\ 2569 .priv = &(struct clk_stm32_pll_cfg){\ 2570 .mux_id = (_mux_id),\ 2571 },\ 2572 .name = #_name,\ 2573 .flags = (_flags),\ 2574 .num_parents = PLL_NUM_PATENTS,\ 2575 .parents = PLL_PARENTS,\ 2576 } 2577 2578 #define STM32_PLL2(_name, _flags, _reg, _gate_id, _mux_id)\ 2579 struct clk _name = {\ 2580 .ops = &clk_stm32_pll_ops,\ 2581 .priv = &(struct clk_stm32_pll_cfg){\ 2582 .pll_offset = (_reg),\ 2583 .gate_id = (_gate_id),\ 2584 .mux_id = (_mux_id),\ 2585 },\ 2586 .name = #_name,\ 2587 .flags = (_flags),\ 2588 .num_parents = PLL_NUM_PATENTS,\ 2589 .parents = PLL_PARENTS,\ 2590 } 2591 2592 #define STM32_PLL3(_name, _flags, _reg, _gate_id, _mux_id)\ 2593 struct clk _name = {\ 2594 .ops = &clk_stm32_pll3_ops,\ 2595 .priv = &(struct clk_stm32_pll_cfg){\ 2596 .pll_offset = (_reg),\ 2597 .gate_id = (_gate_id),\ 2598 .mux_id = (_mux_id),\ 2599 },\ 2600 .name = #_name,\ 2601 .flags = (_flags),\ 2602 .num_parents = PLL_NUM_PATENTS,\ 2603 .parents = PLL_PARENTS,\ 2604 } 2605 2606 #define STM32_PLLS(_name, _flags, _reg, _gate_id, _mux_id)\ 2607 struct clk _name = {\ 2608 .ops = &clk_stm32_pll_ops,\ 2609 .priv = &(struct clk_stm32_pll_cfg){\ 2610 .pll_offset = (_reg),\ 2611 .gate_id = (_gate_id),\ 2612 .mux_id = (_mux_id),\ 2613 },\ 2614 .name = #_name,\ 2615 .flags = (_flags),\ 2616 .num_parents = PLL_NUM_PATENTS,\ 2617 .parents = PLL_PARENTS,\ 2618 } 2619 2620 static STM32_FIXED_RATE(ck_off, RCC_0_MHZ); 2621 2622 static STM32_FIXED_RATE(ck_obser0, 0); 2623 static STM32_FIXED_RATE(ck_obser1, 0); 2624 static STM32_FIXED_RATE(spdifsymb, 0); 2625 static STM32_FIXED_RATE(txbyteclk, 27000000); 2626 2627 /* Oscillator clocks */ 2628 static STM32_OSC(ck_hsi, 0, GATE_HSI); 2629 static STM32_OSC(ck_hse, 0, GATE_HSE); 2630 static STM32_OSC_MSI(ck_msi, 0, GATE_MSI); 2631 static STM32_OSC(ck_lsi, 0, GATE_LSI); 2632 static STM32_OSC(ck_lse, 0, GATE_LSE); 2633 2634 static STM32_HSE_DIV2(ck_hse_div2, &ck_hse, 0, GATE_HSEDIV2); 2635 static STM32_HSE_RTC(ck_hse_rtc, &ck_hse, 0, DIV_RTC); 2636 2637 static STM32_FIXED_FACTOR(i2sckin, NULL, 0, 1, 1); 2638 2639 static STM32_PLL1(ck_pll1, 0, MUX_MUXSEL5); 2640 static STM32_PLL2(ck_pll2, 0, RCC_PLL2CFGR1, GATE_PLL2, MUX_MUXSEL6); 2641 static STM32_PLL3(ck_pll3, 0, RCC_PLL3CFGR1, GATE_PLL3, MUX_MUXSEL7); 2642 static STM32_PLLS(ck_pll4, 0, RCC_PLL4CFGR1, GATE_PLL4, MUX_MUXSEL0); 2643 static STM32_PLLS(ck_pll5, 0, RCC_PLL5CFGR1, GATE_PLL5, MUX_MUXSEL1); 2644 static STM32_PLLS(ck_pll6, 0, RCC_PLL6CFGR1, GATE_PLL6, MUX_MUXSEL2); 2645 static STM32_PLLS(ck_pll7, 0, RCC_PLL7CFGR1, GATE_PLL7, MUX_MUXSEL3); 2646 static STM32_PLLS(ck_pll8, 0, RCC_PLL8CFGR1, GATE_PLL8, MUX_MUXSEL4); 2647 2648 #define STM32_FLEXGEN(_name, _flags, _flex_id)\ 2649 struct clk _name = {\ 2650 .ops = &clk_stm32_flexgen_ops,\ 2651 .priv = &(struct clk_stm32_flexgen_cfg){\ 2652 .flex_id = (_flex_id),\ 2653 },\ 2654 .name = #_name,\ 2655 .flags = (_flags) | CLK_SET_RATE_UNGATE,\ 2656 .num_parents = 15,\ 2657 .parents = {\ 2658 &ck_pll4, &ck_pll5, &ck_pll6, &ck_pll7, &ck_pll8,\ 2659 &ck_hsi, &ck_hse, &ck_msi, &ck_hsi, &ck_hse, &ck_msi,\ 2660 &spdifsymb, &i2sckin, &ck_lsi, &ck_lse\ 2661 },\ 2662 } 2663 2664 static STM32_FLEXGEN(ck_icn_hs_mcu, 0, 0); 2665 static STM32_FLEXGEN(ck_icn_sdmmc, 0, 1); 2666 static STM32_FLEXGEN(ck_icn_ddr, 0, 2); 2667 static STM32_FLEXGEN(ck_icn_display, 0, 3); 2668 static STM32_FLEXGEN(ck_icn_hsl, 0, 4); 2669 static STM32_FLEXGEN(ck_icn_nic, 0, 5); 2670 static STM32_FLEXGEN(ck_icn_vid, 0, 6); 2671 2672 static STM32_DIVIDER(ck_icn_ls_mcu, &ck_icn_hs_mcu, 0, DIV_LSMCU); 2673 2674 static STM32_FLEXGEN(ck_flexgen_07, 0, 7); 2675 static STM32_FLEXGEN(ck_flexgen_08, 0, 8); 2676 static STM32_FLEXGEN(ck_flexgen_09, 0, 9); 2677 static STM32_FLEXGEN(ck_flexgen_10, 0, 10); 2678 static STM32_FLEXGEN(ck_flexgen_11, 0, 11); 2679 static STM32_FLEXGEN(ck_flexgen_12, 0, 12); 2680 static STM32_FLEXGEN(ck_flexgen_13, 0, 13); 2681 static STM32_FLEXGEN(ck_flexgen_14, 0, 14); 2682 static STM32_FLEXGEN(ck_flexgen_15, 0, 15); 2683 static STM32_FLEXGEN(ck_flexgen_16, 0, 16); 2684 static STM32_FLEXGEN(ck_flexgen_17, 0, 17); 2685 static STM32_FLEXGEN(ck_flexgen_18, 0, 18); 2686 static STM32_FLEXGEN(ck_flexgen_19, 0, 19); 2687 static STM32_FLEXGEN(ck_flexgen_20, 0, 20); 2688 static STM32_FLEXGEN(ck_flexgen_21, 0, 21); 2689 static STM32_FLEXGEN(ck_flexgen_22, 0, 22); 2690 static STM32_FLEXGEN(ck_flexgen_23, 0, 23); 2691 static STM32_FLEXGEN(ck_flexgen_24, 0, 24); 2692 static STM32_FLEXGEN(ck_flexgen_25, 0, 25); 2693 static STM32_FLEXGEN(ck_flexgen_26, 0, 26); 2694 static STM32_FLEXGEN(ck_flexgen_27, 0, 27); 2695 static STM32_FLEXGEN(ck_flexgen_28, 0, 28); 2696 static STM32_FLEXGEN(ck_flexgen_29, 0, 29); 2697 static STM32_FLEXGEN(ck_flexgen_30, 0, 30); 2698 static STM32_FLEXGEN(ck_flexgen_31, 0, 31); 2699 static STM32_FLEXGEN(ck_flexgen_32, 0, 32); 2700 static STM32_FLEXGEN(ck_flexgen_33, 0, 33); 2701 static STM32_FLEXGEN(ck_flexgen_34, 0, 34); 2702 static STM32_FLEXGEN(ck_flexgen_35, 0, 35); 2703 static STM32_FLEXGEN(ck_flexgen_36, 0, 36); 2704 static STM32_FLEXGEN(ck_flexgen_37, 0, 37); 2705 static STM32_FLEXGEN(ck_flexgen_38, 0, 38); 2706 static STM32_FLEXGEN(ck_flexgen_39, 0, 39); 2707 static STM32_FLEXGEN(ck_flexgen_40, 0, 40); 2708 static STM32_FLEXGEN(ck_flexgen_41, 0, 41); 2709 static STM32_FLEXGEN(ck_flexgen_42, 0, 42); 2710 static STM32_FLEXGEN(ck_flexgen_43, 0, 43); 2711 static STM32_FLEXGEN(ck_flexgen_44, 0, 44); 2712 static STM32_FLEXGEN(ck_flexgen_45, 0, 45); 2713 static STM32_FLEXGEN(ck_flexgen_46, 0, 46); 2714 static STM32_FLEXGEN(ck_flexgen_47, 0, 47); 2715 static STM32_FLEXGEN(ck_flexgen_48, 0, 48); 2716 static STM32_FLEXGEN(ck_flexgen_49, 0, 49); 2717 static STM32_FLEXGEN(ck_flexgen_50, 0, 50); 2718 static STM32_FLEXGEN(ck_flexgen_51, 0, 51); 2719 static STM32_FLEXGEN(ck_flexgen_52, 0, 52); 2720 static STM32_FLEXGEN(ck_flexgen_53, 0, 53); 2721 static STM32_FLEXGEN(ck_flexgen_54, 0, 54); 2722 static STM32_FLEXGEN(ck_flexgen_55, 0, 55); 2723 static STM32_FLEXGEN(ck_flexgen_56, 0, 56); 2724 static STM32_FLEXGEN(ck_flexgen_57, 0, 57); 2725 static STM32_FLEXGEN(ck_flexgen_58, 0, 58); 2726 static STM32_FLEXGEN(ck_flexgen_59, 0, 59); 2727 static STM32_FLEXGEN(ck_flexgen_60, 0, 60); 2728 static STM32_FLEXGEN(ck_flexgen_61, 0, 61); 2729 static STM32_FLEXGEN(ck_flexgen_62, 0, 62); 2730 static STM32_FLEXGEN(ck_flexgen_63, 0, 63); 2731 2732 static struct clk ck_cpu1 = { 2733 .ops = &clk_stm32_cpu1_ops, 2734 .name = "ck_cpu1", 2735 .flags = CLK_SET_RATE_PARENT, 2736 .num_parents = 2, 2737 .parents = { &ck_pll1, &ck_flexgen_63 }, 2738 }; 2739 2740 static STM32_DIVIDER(ck_icn_apb1, &ck_icn_ls_mcu, 0, DIV_APB1); 2741 static STM32_DIVIDER(ck_icn_apb2, &ck_icn_ls_mcu, 0, DIV_APB2); 2742 static STM32_DIVIDER(ck_icn_apb3, &ck_icn_ls_mcu, 0, DIV_APB3); 2743 static STM32_DIVIDER(ck_icn_apb4, &ck_icn_ls_mcu, 0, DIV_APB4); 2744 static STM32_COMPOSITE(ck_icn_apbdbg, 1, { &ck_icn_ls_mcu }, 0, 2745 GATE_DBG, DIV_APBDBG, NO_MUX); 2746 2747 #define STM32_TIMER(_name, _parent, _flags, _apbdiv, _timpre)\ 2748 struct clk _name = {\ 2749 .ops = &ck_timer_ops,\ 2750 .priv = &(struct clk_stm32_timer_cfg){\ 2751 .apbdiv = (_apbdiv),\ 2752 .timpre = (_timpre),\ 2753 },\ 2754 .name = #_name,\ 2755 .flags = (_flags),\ 2756 .num_parents = 1,\ 2757 .parents = { _parent },\ 2758 } 2759 2760 /* Kernel Timers */ 2761 static STM32_TIMER(ck_timg1, &ck_icn_apb1, 0, RCC_APB1DIVR, RCC_TIMG1PRER); 2762 static STM32_TIMER(ck_timg2, &ck_icn_apb2, 0, RCC_APB2DIVR, RCC_TIMG2PRER); 2763 2764 /* Clocks under RCC RIF protection */ 2765 static STM32_GATE(ck_sys_dbg, &ck_icn_apbdbg, 0, GATE_DBG); 2766 static STM32_GATE(ck_icn_p_stm, &ck_icn_apbdbg, 0, GATE_STM); 2767 static STM32_GATE(ck_icn_s_stm, &ck_icn_ls_mcu, 0, GATE_STM); 2768 static STM32_GATE(ck_ker_tsdbg, &ck_flexgen_43, 0, GATE_DBG); 2769 static STM32_GATE(ck_ker_tpiu, &ck_flexgen_44, 0, GATE_TRACE); 2770 static STM32_GATE(ck_icn_p_etr, &ck_icn_apbdbg, 0, GATE_ETR); 2771 static STM32_GATE(ck_icn_m_etr, &ck_flexgen_45, 0, GATE_ETR); 2772 static STM32_GATE(ck_sys_atb, &ck_flexgen_45, 0, GATE_DBG); 2773 2774 static STM32_GATE(ck_icn_s_sysram, &ck_icn_hs_mcu, 0, GATE_SYSRAM); 2775 static STM32_GATE(ck_icn_s_vderam, &ck_icn_hs_mcu, 0, GATE_VDERAM); 2776 static STM32_GATE(ck_icn_s_retram, &ck_icn_hs_mcu, 0, GATE_RETRAM); 2777 static STM32_GATE(ck_icn_s_bkpsram, &ck_icn_ls_mcu, 0, GATE_BKPSRAM); 2778 static STM32_GATE(ck_icn_s_sram1, &ck_icn_hs_mcu, 0, GATE_SRAM1); 2779 static STM32_GATE(ck_icn_s_sram2, &ck_icn_hs_mcu, 0, GATE_SRAM2); 2780 static STM32_GATE(ck_icn_s_lpsram1, &ck_icn_ls_mcu, 0, GATE_LPSRAM1); 2781 static STM32_GATE(ck_icn_s_lpsram2, &ck_icn_ls_mcu, 0, GATE_LPSRAM2); 2782 static STM32_GATE(ck_icn_s_lpsram3, &ck_icn_ls_mcu, 0, GATE_LPSRAM3); 2783 static STM32_GATE(ck_icn_p_hpdma1, &ck_icn_ls_mcu, 0, GATE_HPDMA1); 2784 static STM32_GATE(ck_icn_p_hpdma2, &ck_icn_ls_mcu, 0, GATE_HPDMA2); 2785 static STM32_GATE(ck_icn_p_hpdma3, &ck_icn_ls_mcu, 0, GATE_HPDMA3); 2786 static STM32_GATE(ck_icn_p_lpdma, &ck_icn_ls_mcu, 0, GATE_LPDMA); 2787 static STM32_GATE(ck_icn_p_ipcc1, &ck_icn_ls_mcu, 0, GATE_IPCC1); 2788 static STM32_GATE(ck_icn_p_ipcc2, &ck_icn_ls_mcu, 0, GATE_IPCC2); 2789 static STM32_GATE(ck_icn_p_hsem, &ck_icn_ls_mcu, 0, GATE_HSEM); 2790 static STM32_GATE(ck_icn_p_gpioa, &ck_icn_ls_mcu, 0, GATE_GPIOA); 2791 static STM32_GATE(ck_icn_p_gpiob, &ck_icn_ls_mcu, 0, GATE_GPIOB); 2792 static STM32_GATE(ck_icn_p_gpioc, &ck_icn_ls_mcu, 0, GATE_GPIOC); 2793 static STM32_GATE(ck_icn_p_gpiod, &ck_icn_ls_mcu, 0, GATE_GPIOD); 2794 static STM32_GATE(ck_icn_p_gpioe, &ck_icn_ls_mcu, 0, GATE_GPIOE); 2795 static STM32_GATE(ck_icn_p_gpiof, &ck_icn_ls_mcu, 0, GATE_GPIOF); 2796 static STM32_GATE(ck_icn_p_gpiog, &ck_icn_ls_mcu, 0, GATE_GPIOG); 2797 static STM32_GATE(ck_icn_p_gpioh, &ck_icn_ls_mcu, 0, GATE_GPIOH); 2798 static STM32_GATE(ck_icn_p_gpioi, &ck_icn_ls_mcu, 0, GATE_GPIOI); 2799 static STM32_GATE(ck_icn_p_gpioj, &ck_icn_ls_mcu, 0, GATE_GPIOJ); 2800 static STM32_GATE(ck_icn_p_gpiok, &ck_icn_ls_mcu, 0, GATE_GPIOK); 2801 static STM32_GATE(ck_icn_p_gpioz, &ck_icn_ls_mcu, 0, GATE_GPIOZ); 2802 static STM32_GATE(ck_icn_p_rtc, &ck_icn_ls_mcu, 0, GATE_RTC); 2803 static STM32_COMPOSITE(ck_rtc, 4, 2804 PARENT(&ck_off, &ck_lse, &ck_lsi, &ck_hse_rtc), 2805 0, GATE_RTCCK, NO_DIV, MUX_RTC); 2806 static STM32_GATE(ck_icn_p_bsec, &ck_icn_apb3, 0, GATE_BSEC); 2807 static STM32_GATE(ck_icn_p_ddrphyc, &ck_icn_ls_mcu, 0, GATE_DDRPHYCAPB); 2808 static STM32_GATE(ck_icn_p_risaf4, &ck_icn_ls_mcu, 0, GATE_DDRCP); 2809 static STM32_GATE(ck_icn_s_ddr, &ck_icn_ddr, 0, GATE_DDRCP); 2810 static STM32_GATE(ck_icn_p_ddrc, &ck_icn_apb4, 0, GATE_DDRCAPB); 2811 static STM32_GATE(ck_icn_p_ddrcfg, &ck_icn_apb4, 0, GATE_DDRCFG); 2812 static STM32_GATE(ck_icn_p_syscpu1, &ck_icn_ls_mcu, 0, GATE_SYSCPU1); 2813 static STM32_GATE(ck_icn_p_is2m, &ck_icn_apb3, 0, GATE_IS2M); 2814 static STM32_COMPOSITE(ck_mco1, 2, PARENT(&ck_flexgen_61, &ck_obser0), 0, 2815 GATE_MCO1, NO_DIV, MUX_MCO1); 2816 static STM32_COMPOSITE(ck_mco2, 2, PARENT(&ck_flexgen_62, &ck_obser1), 0, 2817 GATE_MCO2, NO_DIV, MUX_MCO2); 2818 static STM32_GATE(ck_icn_s_ospi1, &ck_icn_hs_mcu, 0, GATE_OSPI1); 2819 static STM32_GATE(ck_ker_ospi1, &ck_flexgen_48, 0, GATE_OSPI1); 2820 static STM32_GATE(ck_icn_s_ospi2, &ck_icn_hs_mcu, 0, GATE_OSPI2); 2821 static STM32_GATE(ck_ker_ospi2, &ck_flexgen_49, 0, GATE_OSPI2); 2822 static STM32_GATE(ck_icn_p_fmc, &ck_icn_ls_mcu, 0, GATE_FMC); 2823 static STM32_GATE(ck_ker_fmc, &ck_flexgen_50, 0, GATE_FMC); 2824 2825 /* Kernel Clocks */ 2826 static STM32_GATE(ck_icn_p_cci, &ck_icn_ls_mcu, 0, GATE_CCI); 2827 static STM32_GATE(ck_icn_p_crc, &ck_icn_ls_mcu, 0, GATE_CRC); 2828 static STM32_GATE(ck_icn_p_ospiiom, &ck_icn_ls_mcu, 0, GATE_OSPIIOM); 2829 static STM32_GATE(ck_icn_p_hash, &ck_icn_ls_mcu, 0, GATE_HASH); 2830 static STM32_GATE(ck_icn_p_rng, &ck_icn_ls_mcu, 0, GATE_RNG); 2831 static STM32_GATE(ck_icn_p_cryp1, &ck_icn_ls_mcu, 0, GATE_CRYP1); 2832 static STM32_GATE(ck_icn_p_cryp2, &ck_icn_ls_mcu, 0, GATE_CRYP2); 2833 static STM32_GATE(ck_icn_p_saes, &ck_icn_ls_mcu, 0, GATE_SAES); 2834 static STM32_GATE(ck_icn_p_pka, &ck_icn_ls_mcu, 0, GATE_PKA); 2835 static STM32_GATE(ck_icn_p_adf1, &ck_icn_ls_mcu, 0, GATE_ADF1); 2836 static STM32_GATE(ck_icn_p_iwdg5, &ck_icn_ls_mcu, 0, GATE_IWDG5); 2837 static STM32_GATE(ck_icn_p_wwdg2, &ck_icn_ls_mcu, 0, GATE_WWDG2); 2838 static STM32_GATE(ck_icn_p_eth1, &ck_icn_ls_mcu, 0, GATE_ETH1); 2839 static STM32_GATE(ck_icn_p_ethsw, &ck_icn_ls_mcu, 0, GATE_ETHSWMAC); 2840 static STM32_GATE(ck_icn_p_eth2, &ck_icn_ls_mcu, 0, GATE_ETH2); 2841 static STM32_GATE(ck_icn_p_pcie, &ck_icn_ls_mcu, 0, GATE_PCIE); 2842 static STM32_GATE(ck_icn_p_adc12, &ck_icn_ls_mcu, 0, GATE_ADC12); 2843 static STM32_GATE(ck_icn_p_adc3, &ck_icn_ls_mcu, 0, GATE_ADC3); 2844 static STM32_GATE(ck_icn_p_mdf1, &ck_icn_ls_mcu, 0, GATE_MDF1); 2845 static STM32_GATE(ck_icn_p_spi8, &ck_icn_ls_mcu, 0, GATE_SPI8); 2846 static STM32_GATE(ck_icn_p_lpuart1, &ck_icn_ls_mcu, 0, GATE_LPUART1); 2847 static STM32_GATE(ck_icn_p_i2c8, &ck_icn_ls_mcu, 0, GATE_I2C8); 2848 static STM32_GATE(ck_icn_p_lptim3, &ck_icn_ls_mcu, 0, GATE_LPTIM3); 2849 static STM32_GATE(ck_icn_p_lptim4, &ck_icn_ls_mcu, 0, GATE_LPTIM4); 2850 static STM32_GATE(ck_icn_p_lptim5, &ck_icn_ls_mcu, 0, GATE_LPTIM5); 2851 static STM32_GATE(ck_icn_m_sdmmc1, &ck_icn_sdmmc, 0, GATE_SDMMC1); 2852 static STM32_GATE(ck_icn_m_sdmmc2, &ck_icn_sdmmc, 0, GATE_SDMMC2); 2853 static STM32_GATE(ck_icn_m_sdmmc3, &ck_icn_sdmmc, 0, GATE_SDMMC3); 2854 static STM32_GATE(ck_icn_m_usb2ohci, &ck_icn_hsl, 0, GATE_USB2); 2855 static STM32_GATE(ck_icn_m_usb2ehci, &ck_icn_hsl, 0, GATE_USB2); 2856 static STM32_GATE(ck_icn_m_usb3dr, &ck_icn_hsl, 0, GATE_USB3DR); 2857 2858 static STM32_GATE(ck_icn_p_tim2, &ck_icn_apb1, 0, GATE_TIM2); 2859 static STM32_GATE(ck_icn_p_tim3, &ck_icn_apb1, 0, GATE_TIM3); 2860 static STM32_GATE(ck_icn_p_tim4, &ck_icn_apb1, 0, GATE_TIM4); 2861 static STM32_GATE(ck_icn_p_tim5, &ck_icn_apb1, 0, GATE_TIM5); 2862 static STM32_GATE(ck_icn_p_tim6, &ck_icn_apb1, 0, GATE_TIM6); 2863 static STM32_GATE(ck_icn_p_tim7, &ck_icn_apb1, 0, GATE_TIM7); 2864 static STM32_GATE(ck_icn_p_tim10, &ck_icn_apb1, 0, GATE_TIM10); 2865 static STM32_GATE(ck_icn_p_tim11, &ck_icn_apb1, 0, GATE_TIM11); 2866 static STM32_GATE(ck_icn_p_tim12, &ck_icn_apb1, 0, GATE_TIM12); 2867 static STM32_GATE(ck_icn_p_tim13, &ck_icn_apb1, 0, GATE_TIM13); 2868 static STM32_GATE(ck_icn_p_tim14, &ck_icn_apb1, 0, GATE_TIM14); 2869 static STM32_GATE(ck_icn_p_lptim1, &ck_icn_apb1, 0, GATE_LPTIM1); 2870 static STM32_GATE(ck_icn_p_lptim2, &ck_icn_apb1, 0, GATE_LPTIM2); 2871 static STM32_GATE(ck_icn_p_spi2, &ck_icn_apb1, 0, GATE_SPI2); 2872 static STM32_GATE(ck_icn_p_spi3, &ck_icn_apb1, 0, GATE_SPI3); 2873 static STM32_GATE(ck_icn_p_spdifrx, &ck_icn_apb1, 0, GATE_SPDIFRX); 2874 static STM32_GATE(ck_icn_p_usart2, &ck_icn_apb1, 0, GATE_USART2); 2875 static STM32_GATE(ck_icn_p_usart3, &ck_icn_apb1, 0, GATE_USART3); 2876 static STM32_GATE(ck_icn_p_uart4, &ck_icn_apb1, 0, GATE_UART4); 2877 static STM32_GATE(ck_icn_p_uart5, &ck_icn_apb1, 0, GATE_UART5); 2878 static STM32_GATE(ck_icn_p_i2c1, &ck_icn_apb1, 0, GATE_I2C1); 2879 static STM32_GATE(ck_icn_p_i2c2, &ck_icn_apb1, 0, GATE_I2C2); 2880 static STM32_GATE(ck_icn_p_i2c3, &ck_icn_apb1, 0, GATE_I2C3); 2881 static STM32_GATE(ck_icn_p_i2c4, &ck_icn_apb1, 0, GATE_I2C4); 2882 static STM32_GATE(ck_icn_p_i2c5, &ck_icn_apb1, 0, GATE_I2C5); 2883 static STM32_GATE(ck_icn_p_i2c6, &ck_icn_apb1, 0, GATE_I2C6); 2884 static STM32_GATE(ck_icn_p_i2c7, &ck_icn_apb1, 0, GATE_I2C7); 2885 static STM32_GATE(ck_icn_p_i3c1, &ck_icn_apb1, 0, GATE_I3C1); 2886 static STM32_GATE(ck_icn_p_i3c2, &ck_icn_apb1, 0, GATE_I3C2); 2887 static STM32_GATE(ck_icn_p_i3c3, &ck_icn_apb1, 0, GATE_I3C3); 2888 2889 static STM32_GATE(ck_icn_p_i3c4, &ck_icn_ls_mcu, 0, GATE_I3C4); 2890 2891 static STM32_GATE(ck_icn_p_tim1, &ck_icn_apb2, 0, GATE_TIM1); 2892 static STM32_GATE(ck_icn_p_tim8, &ck_icn_apb2, 0, GATE_TIM8); 2893 static STM32_GATE(ck_icn_p_tim15, &ck_icn_apb2, 0, GATE_TIM15); 2894 static STM32_GATE(ck_icn_p_tim16, &ck_icn_apb2, 0, GATE_TIM16); 2895 static STM32_GATE(ck_icn_p_tim17, &ck_icn_apb2, 0, GATE_TIM17); 2896 static STM32_GATE(ck_icn_p_tim20, &ck_icn_apb2, 0, GATE_TIM20); 2897 static STM32_GATE(ck_icn_p_sai1, &ck_icn_apb2, 0, GATE_SAI1); 2898 static STM32_GATE(ck_icn_p_sai2, &ck_icn_apb2, 0, GATE_SAI2); 2899 static STM32_GATE(ck_icn_p_sai3, &ck_icn_apb2, 0, GATE_SAI3); 2900 static STM32_GATE(ck_icn_p_sai4, &ck_icn_apb2, 0, GATE_SAI4); 2901 static STM32_GATE(ck_icn_p_usart1, &ck_icn_apb2, 0, GATE_USART1); 2902 static STM32_GATE(ck_icn_p_usart6, &ck_icn_apb2, 0, GATE_USART6); 2903 static STM32_GATE(ck_icn_p_uart7, &ck_icn_apb2, 0, GATE_UART7); 2904 static STM32_GATE(ck_icn_p_uart8, &ck_icn_apb2, 0, GATE_UART8); 2905 static STM32_GATE(ck_icn_p_uart9, &ck_icn_apb2, 0, GATE_UART9); 2906 static STM32_GATE(ck_icn_p_fdcan, &ck_icn_apb2, 0, GATE_FDCAN); 2907 static STM32_GATE(ck_icn_p_spi1, &ck_icn_apb2, 0, GATE_SPI1); 2908 static STM32_GATE(ck_icn_p_spi4, &ck_icn_apb2, 0, GATE_SPI4); 2909 static STM32_GATE(ck_icn_p_spi5, &ck_icn_apb2, 0, GATE_SPI5); 2910 static STM32_GATE(ck_icn_p_spi6, &ck_icn_apb2, 0, GATE_SPI6); 2911 static STM32_GATE(ck_icn_p_spi7, &ck_icn_apb2, 0, GATE_SPI7); 2912 static STM32_GATE(ck_icn_p_iwdg1, &ck_icn_apb3, 0, GATE_IWDG1); 2913 static STM32_GATE(ck_icn_p_iwdg2, &ck_icn_apb3, 0, GATE_IWDG2); 2914 static STM32_GATE(ck_icn_p_iwdg3, &ck_icn_apb3, 0, GATE_IWDG3); 2915 static STM32_GATE(ck_icn_p_iwdg4, &ck_icn_apb3, 0, GATE_IWDG4); 2916 static STM32_GATE(ck_icn_p_wwdg1, &ck_icn_apb3, 0, GATE_WWDG1); 2917 static STM32_GATE(ck_icn_p_vref, &ck_icn_apb3, 0, GATE_VREF); 2918 static STM32_GATE(ck_icn_p_dts, &ck_icn_apb3, 0, GATE_DTS); 2919 static STM32_GATE(ck_icn_p_serc, &ck_icn_apb3, 0, GATE_SERC); 2920 static STM32_GATE(ck_icn_p_hdp, &ck_icn_apb3, 0, GATE_HDP); 2921 static STM32_GATE(ck_icn_p_dsi, &ck_icn_apb4, 0, GATE_DSI); 2922 static STM32_GATE(ck_icn_p_ltdc, &ck_icn_apb4, 0, GATE_LTDC); 2923 static STM32_GATE(ck_icn_p_csi, &ck_icn_apb4, 0, GATE_CSI); 2924 static STM32_GATE(ck_icn_p_dcmipp, &ck_icn_apb4, 0, GATE_DCMIPP); 2925 static STM32_GATE(ck_icn_p_lvds, &ck_icn_apb4, 0, GATE_LVDS); 2926 static STM32_GATE(ck_icn_p_gicv2m, &ck_icn_apb4, 0, GATE_GICV2M); 2927 static STM32_GATE(ck_icn_p_usbtc, &ck_icn_apb4, 0, GATE_USBTC); 2928 static STM32_GATE(ck_icn_p_usb3pciephy, &ck_icn_apb4, 0, GATE_USB3PCIEPHY); 2929 static STM32_GATE(ck_icn_p_stgen, &ck_icn_apb4, 0, GATE_STGEN); 2930 static STM32_GATE(ck_icn_p_vdec, &ck_icn_apb4, 0, GATE_VDEC); 2931 static STM32_GATE(ck_icn_p_venc, &ck_icn_apb4, 0, GATE_VENC); 2932 2933 static STM32_GATE(ck_ker_tim2, &ck_timg1, 0, GATE_TIM2); 2934 static STM32_GATE(ck_ker_tim3, &ck_timg1, 0, GATE_TIM3); 2935 static STM32_GATE(ck_ker_tim4, &ck_timg1, 0, GATE_TIM4); 2936 static STM32_GATE(ck_ker_tim5, &ck_timg1, 0, GATE_TIM5); 2937 static STM32_GATE(ck_ker_tim6, &ck_timg1, 0, GATE_TIM6); 2938 static STM32_GATE(ck_ker_tim7, &ck_timg1, 0, GATE_TIM7); 2939 static STM32_GATE(ck_ker_tim10, &ck_timg1, 0, GATE_TIM10); 2940 static STM32_GATE(ck_ker_tim11, &ck_timg1, 0, GATE_TIM11); 2941 static STM32_GATE(ck_ker_tim12, &ck_timg1, 0, GATE_TIM12); 2942 static STM32_GATE(ck_ker_tim13, &ck_timg1, 0, GATE_TIM13); 2943 static STM32_GATE(ck_ker_tim14, &ck_timg1, 0, GATE_TIM14); 2944 static STM32_GATE(ck_ker_tim1, &ck_timg2, 0, GATE_TIM1); 2945 static STM32_GATE(ck_ker_tim8, &ck_timg2, 0, GATE_TIM8); 2946 static STM32_GATE(ck_ker_tim15, &ck_timg2, 0, GATE_TIM15); 2947 static STM32_GATE(ck_ker_tim16, &ck_timg2, 0, GATE_TIM16); 2948 static STM32_GATE(ck_ker_tim17, &ck_timg2, 0, GATE_TIM17); 2949 static STM32_GATE(ck_ker_tim20, &ck_timg2, 0, GATE_TIM20); 2950 static STM32_GATE(ck_ker_lptim1, &ck_flexgen_07, 0, GATE_LPTIM1); 2951 static STM32_GATE(ck_ker_lptim2, &ck_flexgen_07, 0, GATE_LPTIM2); 2952 static STM32_GATE(ck_ker_usart2, &ck_flexgen_08, 0, GATE_USART2); 2953 static STM32_GATE(ck_ker_uart4, &ck_flexgen_08, 0, GATE_UART4); 2954 static STM32_GATE(ck_ker_usart3, &ck_flexgen_09, 0, GATE_USART3); 2955 static STM32_GATE(ck_ker_uart5, &ck_flexgen_09, 0, GATE_UART5); 2956 static STM32_GATE(ck_ker_spi2, &ck_flexgen_10, 0, GATE_SPI2); 2957 static STM32_GATE(ck_ker_spi3, &ck_flexgen_10, 0, GATE_SPI3); 2958 static STM32_GATE(ck_ker_spdifrx, &ck_flexgen_11, 0, GATE_SPDIFRX); 2959 static STM32_GATE(ck_ker_i2c1, &ck_flexgen_12, 0, GATE_I2C1); 2960 static STM32_GATE(ck_ker_i2c2, &ck_flexgen_12, 0, GATE_I2C2); 2961 static STM32_GATE(ck_ker_i3c1, &ck_flexgen_12, 0, GATE_I3C1); 2962 static STM32_GATE(ck_ker_i3c2, &ck_flexgen_12, 0, GATE_I3C2); 2963 static STM32_GATE(ck_ker_i2c3, &ck_flexgen_13, 0, GATE_I2C3); 2964 static STM32_GATE(ck_ker_i2c5, &ck_flexgen_13, 0, GATE_I2C5); 2965 static STM32_GATE(ck_ker_i3c3, &ck_flexgen_13, 0, GATE_I3C3); 2966 static STM32_GATE(ck_ker_i2c4, &ck_flexgen_14, 0, GATE_I2C4); 2967 static STM32_GATE(ck_ker_i2c6, &ck_flexgen_14, 0, GATE_I2C6); 2968 static STM32_GATE(ck_ker_i2c7, &ck_flexgen_15, 0, GATE_I2C7); 2969 static STM32_GATE(ck_ker_spi1, &ck_flexgen_16, 0, GATE_SPI1); 2970 static STM32_GATE(ck_ker_spi4, &ck_flexgen_17, 0, GATE_SPI4); 2971 static STM32_GATE(ck_ker_spi5, &ck_flexgen_17, 0, GATE_SPI5); 2972 static STM32_GATE(ck_ker_spi6, &ck_flexgen_18, 0, GATE_SPI6); 2973 static STM32_GATE(ck_ker_spi7, &ck_flexgen_18, 0, GATE_SPI7); 2974 static STM32_GATE(ck_ker_usart1, &ck_flexgen_19, 0, GATE_USART1); 2975 static STM32_GATE(ck_ker_usart6, &ck_flexgen_20, 0, GATE_USART6); 2976 static STM32_GATE(ck_ker_uart7, &ck_flexgen_21, 0, GATE_UART7); 2977 static STM32_GATE(ck_ker_uart8, &ck_flexgen_21, 0, GATE_UART8); 2978 static STM32_GATE(ck_ker_uart9, &ck_flexgen_22, 0, GATE_UART9); 2979 static STM32_GATE(ck_ker_mdf1, &ck_flexgen_23, 0, GATE_MDF1); 2980 static STM32_GATE(ck_ker_sai1, &ck_flexgen_23, 0, GATE_SAI1); 2981 static STM32_GATE(ck_ker_sai2, &ck_flexgen_24, 0, GATE_SAI2); 2982 static STM32_GATE(ck_ker_sai3, &ck_flexgen_25, 0, GATE_SAI3); 2983 static STM32_GATE(ck_ker_sai4, &ck_flexgen_25, 0, GATE_SAI4); 2984 static STM32_GATE(ck_ker_fdcan, &ck_flexgen_26, 0, GATE_FDCAN); 2985 static STM32_GATE(ck_ker_csi, &ck_flexgen_29, 0, GATE_CSI); 2986 static STM32_GATE(ck_ker_csitxesc, &ck_flexgen_30, 0, GATE_CSI); 2987 static STM32_GATE(ck_ker_csiphy, &ck_flexgen_31, 0, GATE_CSI); 2988 static STM32_GATE(ck_ker_stgen, &ck_flexgen_33, CLK_SET_RATE_PARENT, 2989 GATE_STGEN); 2990 static STM32_GATE(ck_ker_usbtc, &ck_flexgen_35, 0, GATE_USBTC); 2991 static STM32_GATE(ck_ker_i3c4, &ck_flexgen_36, 0, GATE_I3C4); 2992 static STM32_GATE(ck_ker_spi8, &ck_flexgen_37, 0, GATE_SPI8); 2993 static STM32_GATE(ck_ker_i2c8, &ck_flexgen_38, 0, GATE_I2C8); 2994 static STM32_GATE(ck_ker_lpuart1, &ck_flexgen_39, 0, GATE_LPUART1); 2995 static STM32_GATE(ck_ker_lptim3, &ck_flexgen_40, 0, GATE_LPTIM3); 2996 static STM32_GATE(ck_ker_lptim4, &ck_flexgen_41, 0, GATE_LPTIM4); 2997 static STM32_GATE(ck_ker_lptim5, &ck_flexgen_41, 0, GATE_LPTIM5); 2998 static STM32_GATE(ck_ker_adf1, &ck_flexgen_42, 0, GATE_ADF1); 2999 static STM32_GATE(ck_ker_sdmmc1, &ck_flexgen_51, 0, GATE_SDMMC1); 3000 static STM32_GATE(ck_ker_sdmmc2, &ck_flexgen_52, 0, GATE_SDMMC2); 3001 static STM32_GATE(ck_ker_sdmmc3, &ck_flexgen_53, 0, GATE_SDMMC3); 3002 static STM32_GATE(ck_ker_eth1, &ck_flexgen_54, 0, GATE_ETH1); 3003 static STM32_GATE(ck_ker_ethsw, &ck_flexgen_54, 0, GATE_ETHSW); 3004 static STM32_GATE(ck_ker_eth2, &ck_flexgen_55, 0, GATE_ETH2); 3005 static STM32_GATE(ck_ker_eth1ptp, &ck_flexgen_56, 0, GATE_ETH1); 3006 static STM32_GATE(ck_ker_eth2ptp, &ck_flexgen_56, 0, GATE_ETH2); 3007 static STM32_GATE(ck_ker_usb2phy2, &ck_flexgen_58, 0, GATE_USB3DR); 3008 static STM32_GATE(ck_icn_m_gpu, &ck_flexgen_59, 0, GATE_GPU); 3009 static STM32_GATE(ck_ker_gpu, &ck_pll3, 0, GATE_GPU); 3010 static STM32_GATE(ck_ker_ethswref, &ck_flexgen_60, 0, GATE_ETHSWREF); 3011 3012 static STM32_GATE(ck_ker_eth1stp, &ck_icn_ls_mcu, 0, GATE_ETH1STP); 3013 static STM32_GATE(ck_ker_eth2stp, &ck_icn_ls_mcu, 0, GATE_ETH2STP); 3014 3015 static STM32_GATE(ck_ker_ltdc, &ck_flexgen_27, CLK_SET_RATE_PARENT, 3016 GATE_LTDC); 3017 3018 static STM32_COMPOSITE(ck_ker_adc12, 2, PARENT(&ck_flexgen_46, &ck_icn_ls_mcu), 3019 0, GATE_ADC12, NO_DIV, MUX_ADC12); 3020 3021 static STM32_COMPOSITE(ck_ker_adc3, 3, PARENT(&ck_flexgen_47, &ck_icn_ls_mcu, 3022 &ck_flexgen_46), 3023 0, GATE_ADC3, NO_DIV, MUX_ADC3); 3024 3025 static STM32_COMPOSITE(ck_ker_usb2phy1, 2, PARENT(&ck_flexgen_57, 3026 &ck_hse_div2), 3027 0, GATE_USB2PHY1, NO_DIV, MUX_USB2PHY1); 3028 3029 static STM32_COMPOSITE(ck_ker_usb2phy2_en, 2, PARENT(&ck_flexgen_58, 3030 &ck_hse_div2), 3031 0, GATE_USB2PHY2, NO_DIV, MUX_USB2PHY2); 3032 3033 static STM32_COMPOSITE(ck_ker_usb3pciephy, 2, PARENT(&ck_flexgen_34, 3034 &ck_hse_div2), 3035 0, GATE_USB3PCIEPHY, NO_DIV, MUX_USB3PCIEPHY); 3036 3037 static STM32_COMPOSITE(clk_lanebyte, 2, PARENT(&txbyteclk, &ck_ker_ltdc), 3038 0, GATE_DSI, NO_DIV, MUX_DSIBLANE); 3039 3040 static STM32_COMPOSITE(ck_phy_dsi, 2, PARENT(&ck_flexgen_28, &ck_hse), 3041 0, GATE_DSI, NO_DIV, MUX_DSIPHY); 3042 3043 static STM32_COMPOSITE(ck_ker_lvdsphy, 2, PARENT(&ck_flexgen_32, &ck_hse), 3044 0, GATE_LVDS, NO_DIV, MUX_LVDSPHY); 3045 3046 static STM32_COMPOSITE(ck_ker_dts, 3, PARENT(&ck_hsi, &ck_hse, &ck_msi), 3047 0, GATE_DTS, NO_DIV, MUX_DTS); 3048 3049 enum { 3050 CK_OFF = STM32MP25_LAST_CLK, 3051 I2SCKIN, 3052 SPDIFSYMB, 3053 CK_HSE_RTC, 3054 TXBYTECLK, 3055 CK_OBSER0, 3056 CK_OBSER1, 3057 STM32MP25_ALL_CLK_NB 3058 }; 3059 3060 static STM32_GATE(ck_ker_eth1mac, &ck_icn_ls_mcu, 0, GATE_ETH1MAC); 3061 static STM32_GATE(ck_ker_eth1tx, &ck_icn_ls_mcu, 0, GATE_ETH1TX); 3062 static STM32_GATE(ck_ker_eth1rx, &ck_icn_ls_mcu, 0, GATE_ETH1RX); 3063 static STM32_GATE(ck_ker_eth2mac, &ck_icn_ls_mcu, 0, GATE_ETH2MAC); 3064 static STM32_GATE(ck_ker_eth2tx, &ck_icn_ls_mcu, 0, GATE_ETH2TX); 3065 static STM32_GATE(ck_ker_eth2rx, &ck_icn_ls_mcu, 0, GATE_ETH2RX); 3066 3067 static struct clk *stm32mp25_clk_provided[STM32MP25_ALL_CLK_NB] = { 3068 [HSI_CK] = &ck_hsi, 3069 [HSE_CK] = &ck_hse, 3070 [MSI_CK] = &ck_msi, 3071 [LSI_CK] = &ck_lsi, 3072 [LSE_CK] = &ck_lse, 3073 3074 [HSE_DIV2_CK] = &ck_hse_div2, 3075 3076 [PLL1_CK] = &ck_pll1, 3077 [PLL2_CK] = &ck_pll2, 3078 [PLL3_CK] = &ck_pll3, 3079 [PLL4_CK] = &ck_pll4, 3080 [PLL5_CK] = &ck_pll5, 3081 [PLL6_CK] = &ck_pll6, 3082 [PLL7_CK] = &ck_pll7, 3083 [PLL8_CK] = &ck_pll8, 3084 3085 [CK_ICN_HS_MCU] = &ck_icn_hs_mcu, 3086 [CK_ICN_LS_MCU] = &ck_icn_ls_mcu, 3087 3088 [CK_ICN_SDMMC] = &ck_icn_sdmmc, 3089 [CK_ICN_DDR] = &ck_icn_ddr, 3090 [CK_ICN_DISPLAY] = &ck_icn_display, 3091 [CK_ICN_HSL] = &ck_icn_hsl, 3092 [CK_ICN_NIC] = &ck_icn_nic, 3093 [CK_ICN_VID] = &ck_icn_vid, 3094 [CK_FLEXGEN_07] = &ck_flexgen_07, 3095 [CK_FLEXGEN_08] = &ck_flexgen_08, 3096 [CK_FLEXGEN_09] = &ck_flexgen_09, 3097 [CK_FLEXGEN_10] = &ck_flexgen_10, 3098 [CK_FLEXGEN_11] = &ck_flexgen_11, 3099 [CK_FLEXGEN_12] = &ck_flexgen_12, 3100 [CK_FLEXGEN_13] = &ck_flexgen_13, 3101 [CK_FLEXGEN_14] = &ck_flexgen_14, 3102 [CK_FLEXGEN_15] = &ck_flexgen_15, 3103 [CK_FLEXGEN_16] = &ck_flexgen_16, 3104 [CK_FLEXGEN_17] = &ck_flexgen_17, 3105 [CK_FLEXGEN_18] = &ck_flexgen_18, 3106 [CK_FLEXGEN_19] = &ck_flexgen_19, 3107 [CK_FLEXGEN_20] = &ck_flexgen_20, 3108 [CK_FLEXGEN_21] = &ck_flexgen_21, 3109 [CK_FLEXGEN_22] = &ck_flexgen_22, 3110 [CK_FLEXGEN_23] = &ck_flexgen_23, 3111 [CK_FLEXGEN_24] = &ck_flexgen_24, 3112 [CK_FLEXGEN_25] = &ck_flexgen_25, 3113 [CK_FLEXGEN_26] = &ck_flexgen_26, 3114 [CK_FLEXGEN_27] = &ck_flexgen_27, 3115 [CK_FLEXGEN_28] = &ck_flexgen_28, 3116 [CK_FLEXGEN_29] = &ck_flexgen_29, 3117 [CK_FLEXGEN_30] = &ck_flexgen_30, 3118 [CK_FLEXGEN_31] = &ck_flexgen_31, 3119 [CK_FLEXGEN_32] = &ck_flexgen_32, 3120 [CK_FLEXGEN_33] = &ck_flexgen_33, 3121 [CK_FLEXGEN_34] = &ck_flexgen_34, 3122 [CK_FLEXGEN_35] = &ck_flexgen_35, 3123 [CK_FLEXGEN_36] = &ck_flexgen_36, 3124 [CK_FLEXGEN_37] = &ck_flexgen_37, 3125 [CK_FLEXGEN_38] = &ck_flexgen_38, 3126 [CK_FLEXGEN_39] = &ck_flexgen_39, 3127 [CK_FLEXGEN_40] = &ck_flexgen_40, 3128 [CK_FLEXGEN_41] = &ck_flexgen_41, 3129 [CK_FLEXGEN_42] = &ck_flexgen_42, 3130 [CK_FLEXGEN_43] = &ck_flexgen_43, 3131 [CK_FLEXGEN_44] = &ck_flexgen_44, 3132 [CK_FLEXGEN_45] = &ck_flexgen_45, 3133 [CK_FLEXGEN_46] = &ck_flexgen_46, 3134 [CK_FLEXGEN_47] = &ck_flexgen_47, 3135 [CK_FLEXGEN_48] = &ck_flexgen_48, 3136 [CK_FLEXGEN_49] = &ck_flexgen_49, 3137 [CK_FLEXGEN_50] = &ck_flexgen_50, 3138 [CK_FLEXGEN_51] = &ck_flexgen_51, 3139 [CK_FLEXGEN_52] = &ck_flexgen_52, 3140 [CK_FLEXGEN_53] = &ck_flexgen_53, 3141 [CK_FLEXGEN_54] = &ck_flexgen_54, 3142 [CK_FLEXGEN_55] = &ck_flexgen_55, 3143 [CK_FLEXGEN_56] = &ck_flexgen_56, 3144 [CK_FLEXGEN_57] = &ck_flexgen_57, 3145 [CK_FLEXGEN_58] = &ck_flexgen_58, 3146 [CK_FLEXGEN_59] = &ck_flexgen_59, 3147 [CK_FLEXGEN_60] = &ck_flexgen_60, 3148 [CK_FLEXGEN_61] = &ck_flexgen_61, 3149 [CK_FLEXGEN_62] = &ck_flexgen_62, 3150 [CK_FLEXGEN_63] = &ck_flexgen_63, 3151 3152 [CK_CPU1] = &ck_cpu1, 3153 3154 [CK_ICN_APB1] = &ck_icn_apb1, 3155 [CK_ICN_APB2] = &ck_icn_apb2, 3156 [CK_ICN_APB3] = &ck_icn_apb3, 3157 [CK_ICN_APB4] = &ck_icn_apb4, 3158 [CK_ICN_APBDBG] = &ck_icn_apbdbg, 3159 3160 [TIMG1_CK] = &ck_timg1, 3161 [TIMG2_CK] = &ck_timg2, 3162 3163 [CK_BUS_SYSRAM] = &ck_icn_s_sysram, 3164 [CK_BUS_VDERAM] = &ck_icn_s_vderam, 3165 [CK_BUS_RETRAM] = &ck_icn_s_retram, 3166 [CK_BUS_SRAM1] = &ck_icn_s_sram1, 3167 [CK_BUS_SRAM2] = &ck_icn_s_sram2, 3168 [CK_BUS_OSPI1] = &ck_icn_s_ospi1, 3169 [CK_BUS_OSPI2] = &ck_icn_s_ospi2, 3170 [CK_BUS_BKPSRAM] = &ck_icn_s_bkpsram, 3171 [CK_BUS_DDRPHYC] = &ck_icn_p_ddrphyc, 3172 [CK_BUS_SYSCPU1] = &ck_icn_p_syscpu1, 3173 [CK_BUS_HPDMA1] = &ck_icn_p_hpdma1, 3174 [CK_BUS_HPDMA2] = &ck_icn_p_hpdma2, 3175 [CK_BUS_HPDMA3] = &ck_icn_p_hpdma3, 3176 [CK_BUS_IPCC1] = &ck_icn_p_ipcc1, 3177 [CK_BUS_IPCC2] = &ck_icn_p_ipcc2, 3178 [CK_BUS_CCI] = &ck_icn_p_cci, 3179 [CK_BUS_CRC] = &ck_icn_p_crc, 3180 [CK_BUS_OSPIIOM] = &ck_icn_p_ospiiom, 3181 [CK_BUS_HASH] = &ck_icn_p_hash, 3182 [CK_BUS_RNG] = &ck_icn_p_rng, 3183 [CK_BUS_CRYP1] = &ck_icn_p_cryp1, 3184 [CK_BUS_CRYP2] = &ck_icn_p_cryp2, 3185 [CK_BUS_SAES] = &ck_icn_p_saes, 3186 [CK_BUS_PKA] = &ck_icn_p_pka, 3187 [CK_BUS_GPIOA] = &ck_icn_p_gpioa, 3188 [CK_BUS_GPIOB] = &ck_icn_p_gpiob, 3189 [CK_BUS_GPIOC] = &ck_icn_p_gpioc, 3190 [CK_BUS_GPIOD] = &ck_icn_p_gpiod, 3191 [CK_BUS_GPIOE] = &ck_icn_p_gpioe, 3192 [CK_BUS_GPIOF] = &ck_icn_p_gpiof, 3193 [CK_BUS_GPIOG] = &ck_icn_p_gpiog, 3194 [CK_BUS_GPIOH] = &ck_icn_p_gpioh, 3195 [CK_BUS_GPIOI] = &ck_icn_p_gpioi, 3196 [CK_BUS_GPIOJ] = &ck_icn_p_gpioj, 3197 [CK_BUS_GPIOK] = &ck_icn_p_gpiok, 3198 [CK_BUS_LPSRAM1] = &ck_icn_s_lpsram1, 3199 [CK_BUS_LPSRAM2] = &ck_icn_s_lpsram2, 3200 [CK_BUS_LPSRAM3] = &ck_icn_s_lpsram3, 3201 [CK_BUS_GPIOZ] = &ck_icn_p_gpioz, 3202 [CK_BUS_LPDMA] = &ck_icn_p_lpdma, 3203 [CK_BUS_ADF1] = &ck_icn_p_adf1, 3204 [CK_BUS_HSEM] = &ck_icn_p_hsem, 3205 [CK_BUS_RTC] = &ck_icn_p_rtc, 3206 [CK_BUS_IWDG5] = &ck_icn_p_iwdg5, 3207 [CK_BUS_WWDG2] = &ck_icn_p_wwdg2, 3208 [CK_BUS_STM] = &ck_icn_p_stm, 3209 [CK_KER_STM] = &ck_icn_s_stm, 3210 [CK_BUS_FMC] = &ck_icn_p_fmc, 3211 [CK_BUS_ETH1] = &ck_icn_p_eth1, 3212 [CK_BUS_ETHSW] = &ck_icn_p_ethsw, 3213 [CK_BUS_ETH2] = &ck_icn_p_eth2, 3214 [CK_BUS_PCIE] = &ck_icn_p_pcie, 3215 [CK_BUS_ADC12] = &ck_icn_p_adc12, 3216 [CK_BUS_ADC3] = &ck_icn_p_adc3, 3217 [CK_BUS_MDF1] = &ck_icn_p_mdf1, 3218 [CK_BUS_SPI8] = &ck_icn_p_spi8, 3219 [CK_BUS_LPUART1] = &ck_icn_p_lpuart1, 3220 [CK_BUS_I2C8] = &ck_icn_p_i2c8, 3221 [CK_BUS_LPTIM3] = &ck_icn_p_lptim3, 3222 [CK_BUS_LPTIM4] = &ck_icn_p_lptim4, 3223 [CK_BUS_LPTIM5] = &ck_icn_p_lptim5, 3224 [CK_BUS_RISAF4] = &ck_icn_p_risaf4, 3225 [CK_BUS_SDMMC1] = &ck_icn_m_sdmmc1, 3226 [CK_BUS_SDMMC2] = &ck_icn_m_sdmmc2, 3227 [CK_BUS_SDMMC3] = &ck_icn_m_sdmmc3, 3228 [CK_BUS_DDR] = &ck_icn_s_ddr, 3229 [CK_BUS_USB2OHCI] = &ck_icn_m_usb2ohci, 3230 [CK_BUS_USB2EHCI] = &ck_icn_m_usb2ehci, 3231 [CK_BUS_USB3DR] = &ck_icn_m_usb3dr, 3232 [CK_BUS_TIM2] = &ck_icn_p_tim2, 3233 [CK_BUS_TIM3] = &ck_icn_p_tim3, 3234 [CK_BUS_TIM4] = &ck_icn_p_tim4, 3235 [CK_BUS_TIM5] = &ck_icn_p_tim5, 3236 [CK_BUS_TIM6] = &ck_icn_p_tim6, 3237 [CK_BUS_TIM7] = &ck_icn_p_tim7, 3238 [CK_BUS_TIM10] = &ck_icn_p_tim10, 3239 [CK_BUS_TIM11] = &ck_icn_p_tim11, 3240 [CK_BUS_TIM12] = &ck_icn_p_tim12, 3241 [CK_BUS_TIM13] = &ck_icn_p_tim13, 3242 [CK_BUS_TIM14] = &ck_icn_p_tim14, 3243 [CK_BUS_LPTIM1] = &ck_icn_p_lptim1, 3244 [CK_BUS_LPTIM2] = &ck_icn_p_lptim2, 3245 [CK_BUS_SPI2] = &ck_icn_p_spi2, 3246 [CK_BUS_SPI3] = &ck_icn_p_spi3, 3247 [CK_BUS_SPDIFRX] = &ck_icn_p_spdifrx, 3248 [CK_BUS_USART2] = &ck_icn_p_usart2, 3249 [CK_BUS_USART3] = &ck_icn_p_usart3, 3250 [CK_BUS_UART4] = &ck_icn_p_uart4, 3251 [CK_BUS_UART5] = &ck_icn_p_uart5, 3252 [CK_BUS_I2C1] = &ck_icn_p_i2c1, 3253 [CK_BUS_I2C2] = &ck_icn_p_i2c2, 3254 [CK_BUS_I2C3] = &ck_icn_p_i2c3, 3255 [CK_BUS_I2C4] = &ck_icn_p_i2c4, 3256 [CK_BUS_I2C5] = &ck_icn_p_i2c5, 3257 [CK_BUS_I2C6] = &ck_icn_p_i2c6, 3258 [CK_BUS_I2C7] = &ck_icn_p_i2c7, 3259 [CK_BUS_I3C1] = &ck_icn_p_i3c1, 3260 [CK_BUS_I3C2] = &ck_icn_p_i3c2, 3261 [CK_BUS_I3C3] = &ck_icn_p_i3c3, 3262 [CK_BUS_I3C4] = &ck_icn_p_i3c4, 3263 [CK_BUS_TIM1] = &ck_icn_p_tim1, 3264 [CK_BUS_TIM8] = &ck_icn_p_tim8, 3265 [CK_BUS_TIM15] = &ck_icn_p_tim15, 3266 [CK_BUS_TIM16] = &ck_icn_p_tim16, 3267 [CK_BUS_TIM17] = &ck_icn_p_tim17, 3268 [CK_BUS_TIM20] = &ck_icn_p_tim20, 3269 [CK_BUS_SAI1] = &ck_icn_p_sai1, 3270 [CK_BUS_SAI2] = &ck_icn_p_sai2, 3271 [CK_BUS_SAI3] = &ck_icn_p_sai3, 3272 [CK_BUS_SAI4] = &ck_icn_p_sai4, 3273 [CK_BUS_USART1] = &ck_icn_p_usart1, 3274 [CK_BUS_USART6] = &ck_icn_p_usart6, 3275 [CK_BUS_UART7] = &ck_icn_p_uart7, 3276 [CK_BUS_UART8] = &ck_icn_p_uart8, 3277 [CK_BUS_UART9] = &ck_icn_p_uart9, 3278 [CK_BUS_FDCAN] = &ck_icn_p_fdcan, 3279 [CK_BUS_SPI1] = &ck_icn_p_spi1, 3280 [CK_BUS_SPI4] = &ck_icn_p_spi4, 3281 [CK_BUS_SPI5] = &ck_icn_p_spi5, 3282 [CK_BUS_SPI6] = &ck_icn_p_spi6, 3283 [CK_BUS_SPI7] = &ck_icn_p_spi7, 3284 [CK_BUS_BSEC] = &ck_icn_p_bsec, 3285 [CK_BUS_IWDG1] = &ck_icn_p_iwdg1, 3286 [CK_BUS_IWDG2] = &ck_icn_p_iwdg2, 3287 [CK_BUS_IWDG3] = &ck_icn_p_iwdg3, 3288 [CK_BUS_IWDG4] = &ck_icn_p_iwdg4, 3289 [CK_BUS_WWDG1] = &ck_icn_p_wwdg1, 3290 [CK_BUS_VREF] = &ck_icn_p_vref, 3291 [CK_BUS_SERC] = &ck_icn_p_serc, 3292 [CK_BUS_DTS] = &ck_icn_p_dts, 3293 [CK_BUS_HDP] = &ck_icn_p_hdp, 3294 [CK_BUS_IS2M] = &ck_icn_p_is2m, 3295 [CK_BUS_DSI] = &ck_icn_p_dsi, 3296 [CK_BUS_LTDC] = &ck_icn_p_ltdc, 3297 [CK_BUS_CSI] = &ck_icn_p_csi, 3298 [CK_BUS_DCMIPP] = &ck_icn_p_dcmipp, 3299 [CK_BUS_DDRC] = &ck_icn_p_ddrc, 3300 [CK_BUS_DDRCFG] = &ck_icn_p_ddrcfg, 3301 [CK_BUS_LVDS] = &ck_icn_p_lvds, 3302 [CK_BUS_GICV2M] = &ck_icn_p_gicv2m, 3303 [CK_BUS_USBTC] = &ck_icn_p_usbtc, 3304 [CK_BUS_USB3PCIEPHY] = &ck_icn_p_usb3pciephy, 3305 [CK_BUS_STGEN] = &ck_icn_p_stgen, 3306 [CK_BUS_VDEC] = &ck_icn_p_vdec, 3307 [CK_BUS_VENC] = &ck_icn_p_venc, 3308 [CK_SYSDBG] = &ck_sys_dbg, 3309 [CK_KER_TIM2] = &ck_ker_tim2, 3310 [CK_KER_TIM3] = &ck_ker_tim3, 3311 [CK_KER_TIM4] = &ck_ker_tim4, 3312 [CK_KER_TIM5] = &ck_ker_tim5, 3313 [CK_KER_TIM6] = &ck_ker_tim6, 3314 [CK_KER_TIM7] = &ck_ker_tim7, 3315 [CK_KER_TIM10] = &ck_ker_tim10, 3316 [CK_KER_TIM11] = &ck_ker_tim11, 3317 [CK_KER_TIM12] = &ck_ker_tim12, 3318 [CK_KER_TIM13] = &ck_ker_tim13, 3319 [CK_KER_TIM14] = &ck_ker_tim14, 3320 [CK_KER_TIM1] = &ck_ker_tim1, 3321 [CK_KER_TIM8] = &ck_ker_tim8, 3322 [CK_KER_TIM15] = &ck_ker_tim15, 3323 [CK_KER_TIM16] = &ck_ker_tim16, 3324 [CK_KER_TIM17] = &ck_ker_tim17, 3325 [CK_KER_TIM20] = &ck_ker_tim20, 3326 [CK_KER_LPTIM1] = &ck_ker_lptim1, 3327 [CK_KER_LPTIM2] = &ck_ker_lptim2, 3328 [CK_KER_USART2] = &ck_ker_usart2, 3329 [CK_KER_UART4] = &ck_ker_uart4, 3330 [CK_KER_USART3] = &ck_ker_usart3, 3331 [CK_KER_UART5] = &ck_ker_uart5, 3332 [CK_KER_SPI2] = &ck_ker_spi2, 3333 [CK_KER_SPI3] = &ck_ker_spi3, 3334 [CK_KER_SPDIFRX] = &ck_ker_spdifrx, 3335 [CK_KER_I2C1] = &ck_ker_i2c1, 3336 [CK_KER_I2C2] = &ck_ker_i2c2, 3337 [CK_KER_I3C1] = &ck_ker_i3c1, 3338 [CK_KER_I3C2] = &ck_ker_i3c2, 3339 [CK_KER_I2C3] = &ck_ker_i2c3, 3340 [CK_KER_I2C5] = &ck_ker_i2c5, 3341 [CK_KER_I3C3] = &ck_ker_i3c3, 3342 [CK_KER_I2C4] = &ck_ker_i2c4, 3343 [CK_KER_I2C6] = &ck_ker_i2c6, 3344 [CK_KER_I2C7] = &ck_ker_i2c7, 3345 [CK_KER_SPI1] = &ck_ker_spi1, 3346 [CK_KER_SPI4] = &ck_ker_spi4, 3347 [CK_KER_SPI5] = &ck_ker_spi5, 3348 [CK_KER_SPI6] = &ck_ker_spi6, 3349 [CK_KER_SPI7] = &ck_ker_spi7, 3350 [CK_KER_USART1] = &ck_ker_usart1, 3351 [CK_KER_USART6] = &ck_ker_usart6, 3352 [CK_KER_UART7] = &ck_ker_uart7, 3353 [CK_KER_UART8] = &ck_ker_uart8, 3354 [CK_KER_UART9] = &ck_ker_uart9, 3355 [CK_KER_MDF1] = &ck_ker_mdf1, 3356 [CK_KER_SAI1] = &ck_ker_sai1, 3357 [CK_KER_SAI2] = &ck_ker_sai2, 3358 [CK_KER_SAI3] = &ck_ker_sai3, 3359 [CK_KER_SAI4] = &ck_ker_sai4, 3360 [CK_KER_FDCAN] = &ck_ker_fdcan, 3361 [CK_KER_CSI] = &ck_ker_csi, 3362 [CK_KER_CSITXESC] = &ck_ker_csitxesc, 3363 [CK_KER_CSIPHY] = &ck_ker_csiphy, 3364 [CK_KER_STGEN] = &ck_ker_stgen, 3365 [CK_KER_USBTC] = &ck_ker_usbtc, 3366 [CK_KER_I3C4] = &ck_ker_i3c4, 3367 [CK_KER_SPI8] = &ck_ker_spi8, 3368 [CK_KER_I2C8] = &ck_ker_i2c8, 3369 [CK_KER_LPUART1] = &ck_ker_lpuart1, 3370 [CK_KER_LPTIM3] = &ck_ker_lptim3, 3371 [CK_KER_LPTIM4] = &ck_ker_lptim4, 3372 [CK_KER_LPTIM5] = &ck_ker_lptim5, 3373 [CK_KER_ADF1] = &ck_ker_adf1, 3374 [CK_KER_TSDBG] = &ck_ker_tsdbg, 3375 [CK_KER_TPIU] = &ck_ker_tpiu, 3376 [CK_BUS_ETR] = &ck_icn_p_etr, 3377 [CK_KER_ETR] = &ck_icn_m_etr, 3378 [CK_BUS_SYSATB] = &ck_sys_atb, 3379 [CK_KER_OSPI1] = &ck_ker_ospi1, 3380 [CK_KER_OSPI2] = &ck_ker_ospi2, 3381 [CK_KER_FMC] = &ck_ker_fmc, 3382 [CK_KER_SDMMC1] = &ck_ker_sdmmc1, 3383 [CK_KER_SDMMC2] = &ck_ker_sdmmc2, 3384 [CK_KER_SDMMC3] = &ck_ker_sdmmc3, 3385 [CK_KER_ETH1] = &ck_ker_eth1, 3386 [CK_ETH1_STP] = &ck_ker_eth1stp, 3387 [CK_KER_ETHSW] = &ck_ker_ethsw, 3388 [CK_KER_ETH2] = &ck_ker_eth2, 3389 [CK_ETH2_STP] = &ck_ker_eth2stp, 3390 [CK_KER_ETH1PTP] = &ck_ker_eth1ptp, 3391 [CK_KER_ETH2PTP] = &ck_ker_eth2ptp, 3392 [CK_BUS_GPU] = &ck_icn_m_gpu, 3393 [CK_KER_GPU] = &ck_ker_gpu, 3394 [CK_KER_ETHSWREF] = &ck_ker_ethswref, 3395 3396 [CK_MCO1] = &ck_mco1, 3397 [CK_MCO2] = &ck_mco2, 3398 [CK_KER_ADC12] = &ck_ker_adc12, 3399 [CK_KER_ADC3] = &ck_ker_adc3, 3400 [CK_KER_USB2PHY1] = &ck_ker_usb2phy1, 3401 [CK_KER_USB2PHY2] = &ck_ker_usb2phy2, 3402 [CK_KER_USB2PHY2EN] = &ck_ker_usb2phy2_en, 3403 [CK_KER_USB3PCIEPHY] = &ck_ker_usb3pciephy, 3404 [CK_KER_LTDC] = &ck_ker_ltdc, 3405 [CK_KER_DSIBLANE] = &clk_lanebyte, 3406 [CK_KER_DSIPHY] = &ck_phy_dsi, 3407 [CK_KER_LVDSPHY] = &ck_ker_lvdsphy, 3408 [CK_KER_DTS] = &ck_ker_dts, 3409 [RTC_CK] = &ck_rtc, 3410 3411 [CK_ETH1_MAC] = &ck_ker_eth1mac, 3412 [CK_ETH1_TX] = &ck_ker_eth1tx, 3413 [CK_ETH1_RX] = &ck_ker_eth1rx, 3414 [CK_ETH2_MAC] = &ck_ker_eth2mac, 3415 [CK_ETH2_TX] = &ck_ker_eth2tx, 3416 [CK_ETH2_RX] = &ck_ker_eth2rx, 3417 3418 [CK_HSE_RTC] = &ck_hse_rtc, 3419 [CK_OBSER0] = &ck_obser0, 3420 [CK_OBSER1] = &ck_obser1, 3421 [CK_OFF] = &ck_off, 3422 [I2SCKIN] = &i2sckin, 3423 [SPDIFSYMB] = &spdifsymb, 3424 [TXBYTECLK] = &txbyteclk, 3425 }; 3426 3427 static bool clk_stm32_clock_is_critical(struct clk *clk) 3428 { 3429 struct clk *clk_criticals[] = { 3430 &ck_hsi, 3431 &ck_hse, 3432 &ck_msi, 3433 &ck_lsi, 3434 &ck_lse, 3435 &ck_cpu1, 3436 &ck_icn_p_syscpu1, 3437 &ck_icn_s_ddr, 3438 &ck_icn_p_ddrc, 3439 &ck_icn_p_ddrcfg, 3440 &ck_icn_p_ddrphyc, 3441 &ck_icn_s_sysram, 3442 &ck_icn_s_bkpsram, 3443 &ck_ker_fmc, 3444 &ck_ker_ospi1, 3445 &ck_ker_ospi2, 3446 &ck_icn_s_vderam, 3447 &ck_icn_s_lpsram1, 3448 &ck_icn_s_lpsram2, 3449 &ck_icn_s_lpsram3, 3450 &ck_icn_p_hpdma1, 3451 &ck_icn_p_hpdma2, 3452 &ck_icn_p_hpdma3, 3453 &ck_icn_p_gpioa, 3454 &ck_icn_p_gpiob, 3455 &ck_icn_p_gpioc, 3456 &ck_icn_p_gpiod, 3457 &ck_icn_p_gpioe, 3458 &ck_icn_p_gpiof, 3459 &ck_icn_p_gpiog, 3460 &ck_icn_p_gpioh, 3461 &ck_icn_p_gpioi, 3462 &ck_icn_p_gpioj, 3463 &ck_icn_p_gpiok, 3464 &ck_icn_p_gpioz, 3465 &ck_icn_p_ipcc1, 3466 &ck_icn_p_ipcc2, 3467 &ck_icn_p_gicv2m, 3468 &ck_icn_p_rtc 3469 }; 3470 size_t i = 0; 3471 3472 for (i = 0; i < ARRAY_SIZE(clk_criticals); i++) 3473 if (clk == clk_criticals[i]) 3474 return true; 3475 return false; 3476 } 3477 3478 static void clk_stm32_init_oscillators(const void *fdt, int node) 3479 { 3480 size_t i = 0; 3481 static const char * const name[] = { 3482 "clk-hse", "clk-hsi", "clk-lse", 3483 "clk-lsi", "clk-msi", "clk-i2sin" 3484 }; 3485 struct clk *clks[ARRAY_SIZE(name)] = { 3486 &ck_hse, &ck_hsi, &ck_lse, 3487 &ck_lsi, &ck_msi, &i2sckin 3488 }; 3489 3490 for (i = 0; i < ARRAY_SIZE(clks); i++) { 3491 struct clk *clk = NULL; 3492 3493 if (clk_dt_get_by_name(fdt, node, name[i], &clk)) 3494 panic(); 3495 3496 clks[i]->parents[0] = clk; 3497 } 3498 } 3499 3500 static TEE_Result clk_stm32_apply_rcc_config(struct stm32_clk_platdata *pdata) 3501 { 3502 if (pdata->safe_rst) 3503 stm32mp25_syscfg_set_safe_reset(true); 3504 3505 return TEE_SUCCESS; 3506 } 3507 3508 static struct stm32_pll_dt_cfg mp25_pll[PLL_NB]; 3509 static struct stm32_clk_opp_dt_cfg mp25_clk_opp; 3510 static struct stm32_osci_dt_cfg mp25_osci[NB_OSCILLATOR]; 3511 3512 #define DT_FLEXGEN_CLK_MAX 64 3513 static uint32_t mp25_flexgen[DT_FLEXGEN_CLK_MAX]; 3514 3515 #define DT_BUS_CLK_MAX 6 3516 static uint32_t mp25_busclk[DT_BUS_CLK_MAX]; 3517 3518 #define DT_KERNEL_CLK_MAX 20 3519 static uint32_t mp25_kernelclk[DT_KERNEL_CLK_MAX]; 3520 3521 static struct stm32_clk_platdata stm32mp25_clock_pdata = { 3522 .osci = mp25_osci, 3523 .nosci = NB_OSCILLATOR, 3524 .pll = mp25_pll, 3525 .npll = PLL_NB, 3526 .opp = &mp25_clk_opp, 3527 .busclk = mp25_busclk, 3528 .nbusclk = DT_BUS_CLK_MAX, 3529 .kernelclk = mp25_kernelclk, 3530 .nkernelclk = DT_KERNEL_CLK_MAX, 3531 .flexgen = mp25_flexgen, 3532 .nflexgen = DT_FLEXGEN_CLK_MAX, 3533 }; 3534 3535 static struct clk_stm32_priv stm32mp25_clock_data = { 3536 .muxes = parent_mp25, 3537 .nb_muxes = ARRAY_SIZE(parent_mp25), 3538 .gates = gates_mp25, 3539 .nb_gates = ARRAY_SIZE(gates_mp25), 3540 .div = dividers_mp25, 3541 .nb_div = ARRAY_SIZE(dividers_mp25), 3542 .pdata = &stm32mp25_clock_pdata, 3543 .nb_clk_refs = STM32MP25_ALL_CLK_NB, 3544 .clk_refs = stm32mp25_clk_provided, 3545 .is_critical = clk_stm32_clock_is_critical, 3546 }; 3547 3548 static TEE_Result handle_available_semaphores(void) 3549 { 3550 struct stm32_clk_platdata *pdata = &stm32mp25_clock_pdata; 3551 TEE_Result res = TEE_ERROR_GENERIC; 3552 unsigned int index = 0; 3553 uint32_t cidcfgr = 0; 3554 unsigned int i = 0; 3555 3556 for (i = 0; i < RCC_NB_RIF_RES; i++) { 3557 vaddr_t reg_offset = pdata->rcc_base + RCC_SEMCR(i); 3558 3559 index = i / 32; 3560 3561 if (!(BIT(i % 32) & pdata->conf_data.access_mask[index])) 3562 continue; 3563 3564 cidcfgr = io_read32(pdata->rcc_base + RCC_CIDCFGR(i)); 3565 3566 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1)) 3567 continue; 3568 3569 if (!(io_read32(pdata->rcc_base + RCC_SECCFGR(index)) & 3570 BIT(i % 32))) { 3571 res = stm32_rif_release_semaphore(reg_offset, 3572 MAX_CID_SUPPORTED); 3573 if (res) { 3574 EMSG("Cannot release semaphore for res %u", i); 3575 return res; 3576 } 3577 } else { 3578 res = stm32_rif_acquire_semaphore(reg_offset, 3579 MAX_CID_SUPPORTED); 3580 if (res) { 3581 EMSG("Cannot acquire semaphore for res %u", i); 3582 return res; 3583 } 3584 } 3585 } 3586 3587 return TEE_SUCCESS; 3588 } 3589 3590 static TEE_Result apply_rcc_rif_config(bool is_tdcid) 3591 { 3592 TEE_Result res = TEE_ERROR_ACCESS_DENIED; 3593 struct stm32_clk_platdata *pdata = &stm32mp25_clock_pdata; 3594 unsigned int i = 0; 3595 unsigned int index = 0; 3596 3597 if (is_tdcid) { 3598 /* 3599 * When TDCID, OP-TEE should be the one to set the CID 3600 * filtering configuration. Clearing previous configuration 3601 * prevents undesired events during the only legitimate 3602 * configuration. 3603 */ 3604 for (i = 0; i < RCC_NB_RIF_RES; i++) { 3605 if (BIT(i % 32) & pdata->conf_data.access_mask[i / 32]) 3606 io_clrbits32(pdata->rcc_base + RCC_CIDCFGR(i), 3607 RCC_CIDCFGR_CONF_MASK); 3608 } 3609 } else { 3610 res = handle_available_semaphores(); 3611 if (res) 3612 panic(); 3613 } 3614 3615 /* Security and privilege RIF configuration */ 3616 for (index = 0; index < RCC_NB_CONFS; index++) { 3617 io_clrsetbits32(pdata->rcc_base + RCC_PRIVCFGR(index), 3618 pdata->conf_data.access_mask[index], 3619 pdata->conf_data.priv_conf[index]); 3620 io_clrsetbits32(pdata->rcc_base + RCC_SECCFGR(index), 3621 pdata->conf_data.access_mask[index], 3622 pdata->conf_data.sec_conf[index]); 3623 } 3624 3625 if (!is_tdcid) 3626 goto end; 3627 3628 for (i = 0; i < RCC_NB_RIF_RES; i++) { 3629 if (BIT(i % 32) & pdata->conf_data.access_mask[i / 32]) 3630 io_clrsetbits32(pdata->rcc_base + RCC_CIDCFGR(i), 3631 RCC_CIDCFGR_CONF_MASK, 3632 pdata->conf_data.cid_confs[i]); 3633 } 3634 3635 for (index = 0; index < RCC_NB_CONFS; index++) 3636 io_setbits32(pdata->rcc_base + RCC_RCFGLOCKR(index), 3637 pdata->conf_data.lock_conf[index]); 3638 3639 res = handle_available_semaphores(); 3640 if (res) 3641 panic(); 3642 end: 3643 if (IS_ENABLED(CFG_TEE_CORE_DEBUG)) { 3644 for (index = 0; index < RCC_NB_CONFS; index++) { 3645 /* Check that RIF config are applied, panic otherwise */ 3646 if ((io_read32(pdata->rcc_base + RCC_PRIVCFGR(index)) & 3647 pdata->conf_data.access_mask[index]) != 3648 pdata->conf_data.priv_conf[index]) 3649 panic("rcc resource prv conf is incorrect"); 3650 3651 if ((io_read32(pdata->rcc_base + RCC_SECCFGR(index)) & 3652 pdata->conf_data.access_mask[index]) != 3653 pdata->conf_data.sec_conf[index]) 3654 panic("rcc resource sec conf is incorrect"); 3655 } 3656 } 3657 3658 return TEE_SUCCESS; 3659 } 3660 3661 static TEE_Result stm32_rcc_rif_pm_suspend(void) 3662 { 3663 struct stm32_clk_platdata *pdata = &stm32mp25_clock_pdata; 3664 unsigned int i = 0; 3665 3666 if (!pdata->nb_res) 3667 return TEE_SUCCESS; 3668 3669 for (i = 0; i < RCC_NB_RIF_RES; i++) 3670 pdata->conf_data.cid_confs[i] = io_read32(pdata->rcc_base + 3671 RCC_CIDCFGR(i)); 3672 3673 for (i = 0; i < RCC_NB_CONFS; i++) { 3674 pdata->conf_data.priv_conf[i] = io_read32(pdata->rcc_base + 3675 RCC_PRIVCFGR(i)); 3676 pdata->conf_data.sec_conf[i] = io_read32(pdata->rcc_base + 3677 RCC_SECCFGR(i)); 3678 pdata->conf_data.lock_conf[i] = io_read32(pdata->rcc_base + 3679 RCC_RCFGLOCKR(i)); 3680 pdata->conf_data.access_mask[i] = GENMASK_32(31, 0); 3681 } 3682 3683 return TEE_SUCCESS; 3684 } 3685 3686 static TEE_Result stm32_rcc_rif_pm(enum pm_op op, unsigned int pm_hint, 3687 const struct pm_callback_handle *h __unused) 3688 { 3689 TEE_Result res = TEE_ERROR_GENERIC; 3690 bool is_tdcid = false; 3691 3692 if (!PM_HINT_IS_STATE(pm_hint, CONTEXT)) 3693 return TEE_SUCCESS; 3694 3695 res = stm32_rifsc_check_tdcid(&is_tdcid); 3696 if (res) 3697 return res; 3698 3699 if (op == PM_OP_RESUME) { 3700 if (is_tdcid) 3701 res = apply_rcc_rif_config(true); 3702 else 3703 res = handle_available_semaphores(); 3704 } else { 3705 if (!is_tdcid) 3706 return TEE_SUCCESS; 3707 3708 res = stm32_rcc_rif_pm_suspend(); 3709 } 3710 3711 return res; 3712 } 3713 3714 static TEE_Result rcc_rif_config(void) 3715 { 3716 TEE_Result res = TEE_ERROR_ACCESS_DENIED; 3717 bool is_tdcid = false; 3718 3719 /* Not expected to fail at this stage */ 3720 res = stm32_rifsc_check_tdcid(&is_tdcid); 3721 if (res) 3722 panic(); 3723 3724 res = apply_rcc_rif_config(is_tdcid); 3725 if (res) 3726 panic(); 3727 3728 register_pm_core_service_cb(stm32_rcc_rif_pm, NULL, "stm32-rcc-rif"); 3729 3730 return TEE_SUCCESS; 3731 } 3732 3733 driver_init_late(rcc_rif_config); 3734 3735 static TEE_Result stm32mp2_clk_probe(const void *fdt, int node, 3736 const void *compat_data __unused) 3737 { 3738 TEE_Result res = TEE_ERROR_GENERIC; 3739 int fdt_rc = 0; 3740 int rc = 0; 3741 struct clk_stm32_priv *priv = &stm32mp25_clock_data; 3742 struct stm32_clk_platdata *pdata = &stm32mp25_clock_pdata; 3743 3744 fdt_rc = stm32_clk_parse_fdt(fdt, node, pdata); 3745 if (fdt_rc) { 3746 EMSG("Failed to parse clock node %s: %d", 3747 fdt_get_name(fdt, node, NULL), fdt_rc); 3748 return TEE_ERROR_GENERIC; 3749 } 3750 3751 rc = clk_stm32_init(priv, stm32_rcc_base()); 3752 if (rc) 3753 return TEE_ERROR_GENERIC; 3754 3755 stm32mp2_init_clock_tree(priv, pdata); 3756 3757 clk_stm32_init_oscillators(fdt, node); 3758 3759 res = clk_stm32_apply_rcc_config(pdata); 3760 if (res) 3761 panic("Error when applying RCC config"); 3762 3763 stm32mp_clk_provider_probe_final(fdt, node, priv); 3764 3765 if (IS_ENABLED(CFG_STM32_CLK_DEBUG)) 3766 clk_print_tree(); 3767 3768 return TEE_SUCCESS; 3769 } 3770 3771 CLK_DT_DECLARE(stm32mp25_clk, "st,stm32mp25-rcc", stm32mp2_clk_probe); 3772