1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2 /* 3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved 4 */ 5 6 #include <assert.h> 7 #include <drivers/clk.h> 8 #include <drivers/clk_dt.h> 9 #include <drivers/stm32mp_dt_bindings.h> 10 #include <drivers/stm32mp13_rcc.h> 11 #include <io.h> 12 #include <kernel/boot.h> 13 #include <libfdt.h> 14 #include <stdio.h> 15 16 #include "clk-stm32-core.h" 17 18 #define MAX_HSI_HZ 64000000 19 #define USB_PHY_48_MHZ 48000000 20 21 #define TIMEOUT_US_200MS U(200000) 22 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS 23 24 #define MAX_OPP CFG_STM32MP_OPP_COUNT 25 26 #define RCC_PLL_NAME_SIZE 12 27 28 struct stm32_osci_dt_cfg { 29 unsigned long freq; 30 bool bypass; 31 bool digbyp; 32 bool css; 33 uint32_t drive; 34 }; 35 36 enum pll_mn { 37 PLL_CFG_M, 38 PLL_CFG_N, 39 PLL_DIV_MN_NB 40 }; 41 42 enum pll_pqr { 43 PLL_CFG_P, 44 PLL_CFG_Q, 45 PLL_CFG_R, 46 PLL_DIV_PQR_NB 47 }; 48 49 enum pll_csg { 50 PLL_CSG_MOD_PER, 51 PLL_CSG_INC_STEP, 52 PLL_CSG_SSCG_MODE, 53 PLL_CSG_NB 54 }; 55 56 struct stm32_pll_vco { 57 uint32_t status; 58 uint32_t src; 59 uint32_t div_mn[PLL_DIV_MN_NB]; 60 uint32_t frac; 61 bool csg_enabled; 62 uint32_t csg[PLL_CSG_NB]; 63 }; 64 65 struct stm32_pll_output { 66 uint32_t output[PLL_DIV_PQR_NB]; 67 }; 68 69 struct stm32_pll_dt_cfg { 70 struct stm32_pll_vco vco; 71 struct stm32_pll_output output; 72 }; 73 74 struct stm32_clk_opp_cfg { 75 uint32_t frq; 76 uint32_t src; 77 uint32_t div; 78 struct stm32_pll_dt_cfg pll_cfg; 79 }; 80 81 struct stm32_clk_opp_dt_cfg { 82 struct stm32_clk_opp_cfg mpu_opp[MAX_OPP]; 83 struct stm32_clk_opp_cfg axi_opp[MAX_OPP]; 84 struct stm32_clk_opp_cfg mlahbs_opp[MAX_OPP]; 85 }; 86 87 struct stm32_clk_platdata { 88 uintptr_t rcc_base; 89 uint32_t nosci; 90 struct stm32_osci_dt_cfg *osci; 91 uint32_t npll; 92 struct stm32_pll_dt_cfg *pll; 93 struct stm32_clk_opp_dt_cfg *opp; 94 uint32_t nclksrc; 95 uint32_t *clksrc; 96 uint32_t nclkdiv; 97 uint32_t *clkdiv; 98 }; 99 100 /* 101 * GATE CONFIG 102 */ 103 104 /* Warning GATE_XXX_RDY must follow GATE_XXX */ 105 enum enum_gate_cfg { 106 GATE_LSE, 107 GATE_LSE_RDY, 108 GATE_LSI, 109 GATE_LSI_RDY, 110 GATE_HSI, 111 GATE_HSI_RDY, 112 GATE_CSI, 113 GATE_CSI_RDY, 114 GATE_HSE, 115 GATE_HSE_RDY, 116 GATE_PLL1, 117 GATE_PLL1_RDY, 118 GATE_PLL2, 119 GATE_PLL2_RDY, 120 GATE_PLL3, 121 GATE_PLL3_RDY, 122 GATE_PLL4, 123 GATE_PLL4_RDY, 124 GATE_HSIDIVRDY, 125 GATE_MPUSRCRDY, 126 GATE_AXISSRCRDY, 127 GATE_MCUSSRCRDY, 128 GATE_PLL12SRCRDY, 129 GATE_PLL3SRCRDY, 130 GATE_PLL4SRCRDY, 131 GATE_MPUDIVRDY, 132 GATE_AXIDIVRDY, 133 GATE_MLAHBDIVRDY, 134 GATE_APB1DIVRDY, 135 GATE_APB2DIVRDY, 136 GATE_APB3DIVRDY, 137 GATE_APB4DIVRDY, 138 GATE_APB5DIVRDY, 139 GATE_APB6DIVRDY, 140 GATE_RTCCK, 141 GATE_MCO1, 142 GATE_MCO2, 143 GATE_DBGCK, 144 GATE_TRACECK, 145 GATE_PLL1_DIVP, 146 GATE_PLL1_DIVQ, 147 GATE_PLL1_DIVR, 148 GATE_PLL2_DIVP, 149 GATE_PLL2_DIVQ, 150 GATE_PLL2_DIVR, 151 GATE_PLL3_DIVP, 152 GATE_PLL3_DIVQ, 153 GATE_PLL3_DIVR, 154 GATE_PLL4_DIVP, 155 GATE_PLL4_DIVQ, 156 GATE_PLL4_DIVR, 157 GATE_DDRC1, 158 GATE_DDRC1LP, 159 GATE_DDRPHYC, 160 GATE_DDRPHYCLP, 161 GATE_DDRCAPB, 162 GATE_DDRCAPBLP, 163 GATE_AXIDCG, 164 GATE_DDRPHYCAPB, 165 GATE_DDRPHYCAPBLP, 166 GATE_TIM2, 167 GATE_TIM3, 168 GATE_TIM4, 169 GATE_TIM5, 170 GATE_TIM6, 171 GATE_TIM7, 172 GATE_LPTIM1, 173 GATE_SPI2, 174 GATE_SPI3, 175 GATE_USART3, 176 GATE_UART4, 177 GATE_UART5, 178 GATE_UART7, 179 GATE_UART8, 180 GATE_I2C1, 181 GATE_I2C2, 182 GATE_SPDIF, 183 GATE_TIM1, 184 GATE_TIM8, 185 GATE_SPI1, 186 GATE_USART6, 187 GATE_SAI1, 188 GATE_SAI2, 189 GATE_DFSDM, 190 GATE_ADFSDM, 191 GATE_FDCAN, 192 GATE_LPTIM2, 193 GATE_LPTIM3, 194 GATE_LPTIM4, 195 GATE_LPTIM5, 196 GATE_VREF, 197 GATE_DTS, 198 GATE_PMBCTRL, 199 GATE_HDP, 200 GATE_SYSCFG, 201 GATE_DCMIPP, 202 GATE_DDRPERFM, 203 GATE_IWDG2APB, 204 GATE_USBPHY, 205 GATE_STGENRO, 206 GATE_LTDC, 207 GATE_RTCAPB, 208 GATE_TZC, 209 GATE_ETZPC, 210 GATE_IWDG1APB, 211 GATE_BSEC, 212 GATE_STGENC, 213 GATE_USART1, 214 GATE_USART2, 215 GATE_SPI4, 216 GATE_SPI5, 217 GATE_I2C3, 218 GATE_I2C4, 219 GATE_I2C5, 220 GATE_TIM12, 221 GATE_TIM13, 222 GATE_TIM14, 223 GATE_TIM15, 224 GATE_TIM16, 225 GATE_TIM17, 226 GATE_DMA1, 227 GATE_DMA2, 228 GATE_DMAMUX1, 229 GATE_DMA3, 230 GATE_DMAMUX2, 231 GATE_ADC1, 232 GATE_ADC2, 233 GATE_USBO, 234 GATE_TSC, 235 GATE_GPIOA, 236 GATE_GPIOB, 237 GATE_GPIOC, 238 GATE_GPIOD, 239 GATE_GPIOE, 240 GATE_GPIOF, 241 GATE_GPIOG, 242 GATE_GPIOH, 243 GATE_GPIOI, 244 GATE_PKA, 245 GATE_SAES, 246 GATE_CRYP1, 247 GATE_HASH1, 248 GATE_RNG1, 249 GATE_BKPSRAM, 250 GATE_AXIMC, 251 GATE_MCE, 252 GATE_ETH1CK, 253 GATE_ETH1TX, 254 GATE_ETH1RX, 255 GATE_ETH1MAC, 256 GATE_FMC, 257 GATE_QSPI, 258 GATE_SDMMC1, 259 GATE_SDMMC2, 260 GATE_CRC1, 261 GATE_USBH, 262 GATE_ETH2CK, 263 GATE_ETH2TX, 264 GATE_ETH2RX, 265 GATE_ETH2MAC, 266 GATE_MDMA, 267 GATE_NB 268 }; 269 270 #define GATE_CFG(_id, _offset, _bit_idx, _offset_clr)\ 271 [(_id)] = {\ 272 .offset = (_offset),\ 273 .bit_idx = (_bit_idx),\ 274 .set_clr = (_offset_clr),\ 275 } 276 277 static const struct gate_cfg gates_mp13[GATE_NB] = { 278 GATE_CFG(GATE_LSE, RCC_BDCR, 0, 0), 279 GATE_CFG(GATE_LSE_RDY, RCC_BDCR, 2, 0), 280 GATE_CFG(GATE_RTCCK, RCC_BDCR, 20, 0), 281 GATE_CFG(GATE_LSI, RCC_RDLSICR, 0, 0), 282 GATE_CFG(GATE_LSI_RDY, RCC_RDLSICR, 1, 0), 283 GATE_CFG(GATE_HSI, RCC_OCENSETR, 0, 1), 284 GATE_CFG(GATE_HSI_RDY, RCC_OCRDYR, 0, 0), 285 GATE_CFG(GATE_CSI, RCC_OCENSETR, 4, 1), 286 GATE_CFG(GATE_CSI_RDY, RCC_OCRDYR, 4, 0), 287 GATE_CFG(GATE_HSE, RCC_OCENSETR, 8, 1), 288 GATE_CFG(GATE_HSE_RDY, RCC_OCRDYR, 8, 0), 289 GATE_CFG(GATE_HSIDIVRDY, RCC_OCRDYR, 2, 0), 290 GATE_CFG(GATE_MPUSRCRDY, RCC_MPCKSELR, 31, 0), 291 GATE_CFG(GATE_AXISSRCRDY, RCC_ASSCKSELR, 31, 0), 292 GATE_CFG(GATE_MCUSSRCRDY, RCC_MSSCKSELR, 31, 0), 293 GATE_CFG(GATE_PLL12SRCRDY, RCC_RCK12SELR, 31, 0), 294 GATE_CFG(GATE_PLL3SRCRDY, RCC_RCK3SELR, 31, 0), 295 GATE_CFG(GATE_PLL4SRCRDY, RCC_RCK4SELR, 31, 0), 296 GATE_CFG(GATE_MPUDIVRDY, RCC_MPCKDIVR, 31, 0), 297 GATE_CFG(GATE_AXIDIVRDY, RCC_AXIDIVR, 31, 0), 298 GATE_CFG(GATE_MLAHBDIVRDY, RCC_MLAHBDIVR, 31, 0), 299 GATE_CFG(GATE_APB1DIVRDY, RCC_APB1DIVR, 31, 0), 300 GATE_CFG(GATE_APB2DIVRDY, RCC_APB2DIVR, 31, 0), 301 GATE_CFG(GATE_APB3DIVRDY, RCC_APB3DIVR, 31, 0), 302 GATE_CFG(GATE_APB4DIVRDY, RCC_APB4DIVR, 31, 0), 303 GATE_CFG(GATE_APB5DIVRDY, RCC_APB5DIVR, 31, 0), 304 GATE_CFG(GATE_APB6DIVRDY, RCC_APB6DIVR, 31, 0), 305 GATE_CFG(GATE_MCO1, RCC_MCO1CFGR, 12, 0), 306 GATE_CFG(GATE_MCO2, RCC_MCO2CFGR, 12, 0), 307 GATE_CFG(GATE_DBGCK, RCC_DBGCFGR, 8, 0), 308 GATE_CFG(GATE_TRACECK, RCC_DBGCFGR, 9, 0), 309 GATE_CFG(GATE_PLL1, RCC_PLL1CR, 0, 0), 310 GATE_CFG(GATE_PLL1_RDY, RCC_PLL1CR, 1, 0), 311 GATE_CFG(GATE_PLL1_DIVP, RCC_PLL1CR, 4, 0), 312 GATE_CFG(GATE_PLL1_DIVQ, RCC_PLL1CR, 5, 0), 313 GATE_CFG(GATE_PLL1_DIVR, RCC_PLL1CR, 6, 0), 314 GATE_CFG(GATE_PLL2, RCC_PLL2CR, 0, 0), 315 GATE_CFG(GATE_PLL2_RDY, RCC_PLL2CR, 1, 0), 316 GATE_CFG(GATE_PLL2_DIVP, RCC_PLL2CR, 4, 0), 317 GATE_CFG(GATE_PLL2_DIVQ, RCC_PLL2CR, 5, 0), 318 GATE_CFG(GATE_PLL2_DIVR, RCC_PLL2CR, 6, 0), 319 GATE_CFG(GATE_PLL3, RCC_PLL3CR, 0, 0), 320 GATE_CFG(GATE_PLL3_RDY, RCC_PLL3CR, 1, 0), 321 GATE_CFG(GATE_PLL3_DIVP, RCC_PLL3CR, 4, 0), 322 GATE_CFG(GATE_PLL3_DIVQ, RCC_PLL3CR, 5, 0), 323 GATE_CFG(GATE_PLL3_DIVR, RCC_PLL3CR, 6, 0), 324 GATE_CFG(GATE_PLL4, RCC_PLL4CR, 0, 0), 325 GATE_CFG(GATE_PLL4_RDY, RCC_PLL4CR, 1, 0), 326 GATE_CFG(GATE_PLL4_DIVP, RCC_PLL4CR, 4, 0), 327 GATE_CFG(GATE_PLL4_DIVQ, RCC_PLL4CR, 5, 0), 328 GATE_CFG(GATE_PLL4_DIVR, RCC_PLL4CR, 6, 0), 329 GATE_CFG(GATE_DDRC1, RCC_DDRITFCR, 0, 0), 330 GATE_CFG(GATE_DDRC1LP, RCC_DDRITFCR, 1, 0), 331 GATE_CFG(GATE_DDRPHYC, RCC_DDRITFCR, 4, 0), 332 GATE_CFG(GATE_DDRPHYCLP, RCC_DDRITFCR, 5, 0), 333 GATE_CFG(GATE_DDRCAPB, RCC_DDRITFCR, 6, 0), 334 GATE_CFG(GATE_DDRCAPBLP, RCC_DDRITFCR, 7, 0), 335 GATE_CFG(GATE_AXIDCG, RCC_DDRITFCR, 8, 0), 336 GATE_CFG(GATE_DDRPHYCAPB, RCC_DDRITFCR, 9, 0), 337 GATE_CFG(GATE_DDRPHYCAPBLP, RCC_DDRITFCR, 10, 0), 338 GATE_CFG(GATE_TIM2, RCC_MP_APB1ENSETR, 0, 1), 339 GATE_CFG(GATE_TIM3, RCC_MP_APB1ENSETR, 1, 1), 340 GATE_CFG(GATE_TIM4, RCC_MP_APB1ENSETR, 2, 1), 341 GATE_CFG(GATE_TIM5, RCC_MP_APB1ENSETR, 3, 1), 342 GATE_CFG(GATE_TIM6, RCC_MP_APB1ENSETR, 4, 1), 343 GATE_CFG(GATE_TIM7, RCC_MP_APB1ENSETR, 5, 1), 344 GATE_CFG(GATE_LPTIM1, RCC_MP_APB1ENSETR, 9, 1), 345 GATE_CFG(GATE_SPI2, RCC_MP_APB1ENSETR, 11, 1), 346 GATE_CFG(GATE_SPI3, RCC_MP_APB1ENSETR, 12, 1), 347 GATE_CFG(GATE_USART3, RCC_MP_APB1ENSETR, 15, 1), 348 GATE_CFG(GATE_UART4, RCC_MP_APB1ENSETR, 16, 1), 349 GATE_CFG(GATE_UART5, RCC_MP_APB1ENSETR, 17, 1), 350 GATE_CFG(GATE_UART7, RCC_MP_APB1ENSETR, 18, 1), 351 GATE_CFG(GATE_UART8, RCC_MP_APB1ENSETR, 19, 1), 352 GATE_CFG(GATE_I2C1, RCC_MP_APB1ENSETR, 21, 1), 353 GATE_CFG(GATE_I2C2, RCC_MP_APB1ENSETR, 22, 1), 354 GATE_CFG(GATE_SPDIF, RCC_MP_APB1ENSETR, 26, 1), 355 GATE_CFG(GATE_TIM1, RCC_MP_APB2ENSETR, 0, 1), 356 GATE_CFG(GATE_TIM8, RCC_MP_APB2ENSETR, 1, 1), 357 GATE_CFG(GATE_SPI1, RCC_MP_APB2ENSETR, 8, 1), 358 GATE_CFG(GATE_USART6, RCC_MP_APB2ENSETR, 13, 1), 359 GATE_CFG(GATE_SAI1, RCC_MP_APB2ENSETR, 16, 1), 360 GATE_CFG(GATE_SAI2, RCC_MP_APB2ENSETR, 17, 1), 361 GATE_CFG(GATE_DFSDM, RCC_MP_APB2ENSETR, 20, 1), 362 GATE_CFG(GATE_ADFSDM, RCC_MP_APB2ENSETR, 21, 1), 363 GATE_CFG(GATE_FDCAN, RCC_MP_APB2ENSETR, 24, 1), 364 GATE_CFG(GATE_LPTIM2, RCC_MP_APB3ENSETR, 0, 1), 365 GATE_CFG(GATE_LPTIM3, RCC_MP_APB3ENSETR, 1, 1), 366 GATE_CFG(GATE_LPTIM4, RCC_MP_APB3ENSETR, 2, 1), 367 GATE_CFG(GATE_LPTIM5, RCC_MP_APB3ENSETR, 3, 1), 368 GATE_CFG(GATE_VREF, RCC_MP_APB3ENSETR, 13, 1), 369 GATE_CFG(GATE_DTS, RCC_MP_APB3ENSETR, 16, 1), 370 GATE_CFG(GATE_PMBCTRL, RCC_MP_APB3ENSETR, 17, 1), 371 GATE_CFG(GATE_HDP, RCC_MP_APB3ENSETR, 20, 1), 372 GATE_CFG(GATE_SYSCFG, RCC_MP_S_APB3ENSETR, 0, 1), 373 GATE_CFG(GATE_DCMIPP, RCC_MP_APB4ENSETR, 1, 1), 374 GATE_CFG(GATE_DDRPERFM, RCC_MP_APB4ENSETR, 8, 1), 375 GATE_CFG(GATE_IWDG2APB, RCC_MP_APB4ENSETR, 15, 1), 376 GATE_CFG(GATE_USBPHY, RCC_MP_APB4ENSETR, 16, 1), 377 GATE_CFG(GATE_STGENRO, RCC_MP_APB4ENSETR, 20, 1), 378 GATE_CFG(GATE_LTDC, RCC_MP_S_APB4ENSETR, 0, 1), 379 GATE_CFG(GATE_RTCAPB, RCC_MP_APB5ENSETR, 8, 1), 380 GATE_CFG(GATE_TZC, RCC_MP_APB5ENSETR, 11, 1), 381 GATE_CFG(GATE_ETZPC, RCC_MP_APB5ENSETR, 13, 1), 382 GATE_CFG(GATE_IWDG1APB, RCC_MP_APB5ENSETR, 15, 1), 383 GATE_CFG(GATE_BSEC, RCC_MP_APB5ENSETR, 16, 1), 384 GATE_CFG(GATE_STGENC, RCC_MP_APB5ENSETR, 20, 1), 385 GATE_CFG(GATE_USART1, RCC_MP_APB6ENSETR, 0, 1), 386 GATE_CFG(GATE_USART2, RCC_MP_APB6ENSETR, 1, 1), 387 GATE_CFG(GATE_SPI4, RCC_MP_APB6ENSETR, 2, 1), 388 GATE_CFG(GATE_SPI5, RCC_MP_APB6ENSETR, 3, 1), 389 GATE_CFG(GATE_I2C3, RCC_MP_APB6ENSETR, 4, 1), 390 GATE_CFG(GATE_I2C4, RCC_MP_APB6ENSETR, 5, 1), 391 GATE_CFG(GATE_I2C5, RCC_MP_APB6ENSETR, 6, 1), 392 GATE_CFG(GATE_TIM12, RCC_MP_APB6ENSETR, 7, 1), 393 GATE_CFG(GATE_TIM13, RCC_MP_APB6ENSETR, 8, 1), 394 GATE_CFG(GATE_TIM14, RCC_MP_APB6ENSETR, 9, 1), 395 GATE_CFG(GATE_TIM15, RCC_MP_APB6ENSETR, 10, 1), 396 GATE_CFG(GATE_TIM16, RCC_MP_APB6ENSETR, 11, 1), 397 GATE_CFG(GATE_TIM17, RCC_MP_APB6ENSETR, 12, 1), 398 GATE_CFG(GATE_DMA1, RCC_MP_AHB2ENSETR, 0, 1), 399 GATE_CFG(GATE_DMA2, RCC_MP_AHB2ENSETR, 1, 1), 400 GATE_CFG(GATE_DMAMUX1, RCC_MP_AHB2ENSETR, 2, 1), 401 GATE_CFG(GATE_DMA3, RCC_MP_AHB2ENSETR, 3, 1), 402 GATE_CFG(GATE_DMAMUX2, RCC_MP_AHB2ENSETR, 4, 1), 403 GATE_CFG(GATE_ADC1, RCC_MP_AHB2ENSETR, 5, 1), 404 GATE_CFG(GATE_ADC2, RCC_MP_AHB2ENSETR, 6, 1), 405 GATE_CFG(GATE_USBO, RCC_MP_AHB2ENSETR, 8, 1), 406 GATE_CFG(GATE_TSC, RCC_MP_AHB4ENSETR, 15, 1), 407 GATE_CFG(GATE_GPIOA, RCC_MP_S_AHB4ENSETR, 0, 1), 408 GATE_CFG(GATE_GPIOB, RCC_MP_S_AHB4ENSETR, 1, 1), 409 GATE_CFG(GATE_GPIOC, RCC_MP_S_AHB4ENSETR, 2, 1), 410 GATE_CFG(GATE_GPIOD, RCC_MP_S_AHB4ENSETR, 3, 1), 411 GATE_CFG(GATE_GPIOE, RCC_MP_S_AHB4ENSETR, 4, 1), 412 GATE_CFG(GATE_GPIOF, RCC_MP_S_AHB4ENSETR, 5, 1), 413 GATE_CFG(GATE_GPIOG, RCC_MP_S_AHB4ENSETR, 6, 1), 414 GATE_CFG(GATE_GPIOH, RCC_MP_S_AHB4ENSETR, 7, 1), 415 GATE_CFG(GATE_GPIOI, RCC_MP_S_AHB4ENSETR, 8, 1), 416 GATE_CFG(GATE_PKA, RCC_MP_AHB5ENSETR, 2, 1), 417 GATE_CFG(GATE_SAES, RCC_MP_AHB5ENSETR, 3, 1), 418 GATE_CFG(GATE_CRYP1, RCC_MP_AHB5ENSETR, 4, 1), 419 GATE_CFG(GATE_HASH1, RCC_MP_AHB5ENSETR, 5, 1), 420 GATE_CFG(GATE_RNG1, RCC_MP_AHB5ENSETR, 6, 1), 421 GATE_CFG(GATE_BKPSRAM, RCC_MP_AHB5ENSETR, 8, 1), 422 GATE_CFG(GATE_AXIMC, RCC_MP_AHB5ENSETR, 16, 1), 423 GATE_CFG(GATE_MCE, RCC_MP_AHB6ENSETR, 1, 1), 424 GATE_CFG(GATE_ETH1CK, RCC_MP_AHB6ENSETR, 7, 1), 425 GATE_CFG(GATE_ETH1TX, RCC_MP_AHB6ENSETR, 8, 1), 426 GATE_CFG(GATE_ETH1RX, RCC_MP_AHB6ENSETR, 9, 1), 427 GATE_CFG(GATE_ETH1MAC, RCC_MP_AHB6ENSETR, 10, 1), 428 GATE_CFG(GATE_FMC, RCC_MP_AHB6ENSETR, 12, 1), 429 GATE_CFG(GATE_QSPI, RCC_MP_AHB6ENSETR, 14, 1), 430 GATE_CFG(GATE_SDMMC1, RCC_MP_AHB6ENSETR, 16, 1), 431 GATE_CFG(GATE_SDMMC2, RCC_MP_AHB6ENSETR, 17, 1), 432 GATE_CFG(GATE_CRC1, RCC_MP_AHB6ENSETR, 20, 1), 433 GATE_CFG(GATE_USBH, RCC_MP_AHB6ENSETR, 24, 1), 434 GATE_CFG(GATE_ETH2CK, RCC_MP_AHB6ENSETR, 27, 1), 435 GATE_CFG(GATE_ETH2TX, RCC_MP_AHB6ENSETR, 28, 1), 436 GATE_CFG(GATE_ETH2RX, RCC_MP_AHB6ENSETR, 29, 1), 437 GATE_CFG(GATE_ETH2MAC, RCC_MP_AHB6ENSETR, 30, 1), 438 GATE_CFG(GATE_MDMA, RCC_MP_S_AHB6ENSETR, 0, 1), 439 }; 440 441 /* 442 * MUX CONFIG 443 */ 444 #define MUXRDY_CFG(_id, _offset, _shift, _witdh, _rdy)\ 445 [(_id)] = {\ 446 .offset = (_offset),\ 447 .shift = (_shift),\ 448 .width = (_witdh),\ 449 .ready = (_rdy),\ 450 } 451 452 #define MUX_CFG(_id, _offset, _shift, _witdh)\ 453 MUXRDY_CFG(_id, _offset, _shift, _witdh, MUX_NO_RDY) 454 455 static const struct mux_cfg parent_mp13[MUX_NB] = { 456 MUXRDY_CFG(MUX_MPU, RCC_MPCKSELR, 0, 2, GATE_MPUSRCRDY), 457 MUXRDY_CFG(MUX_AXI, RCC_ASSCKSELR, 0, 3, GATE_AXISSRCRDY), 458 MUXRDY_CFG(MUX_MLAHB, RCC_MSSCKSELR, 0, 2, GATE_MCUSSRCRDY), 459 MUXRDY_CFG(MUX_PLL12, RCC_RCK12SELR, 0, 2, GATE_PLL12SRCRDY), 460 MUXRDY_CFG(MUX_PLL3, RCC_RCK3SELR, 0, 2, GATE_PLL3SRCRDY), 461 MUXRDY_CFG(MUX_PLL4, RCC_RCK4SELR, 0, 2, GATE_PLL4SRCRDY), 462 MUX_CFG(MUX_ADC1, RCC_ADC12CKSELR, 0, 2), 463 MUX_CFG(MUX_ADC2, RCC_ADC12CKSELR, 2, 2), 464 MUX_CFG(MUX_CKPER, RCC_CPERCKSELR, 0, 2), 465 MUX_CFG(MUX_DCMIPP, RCC_DCMIPPCKSELR, 0, 2), 466 MUX_CFG(MUX_ETH1, RCC_ETH12CKSELR, 0, 2), 467 MUX_CFG(MUX_ETH2, RCC_ETH12CKSELR, 8, 2), 468 MUX_CFG(MUX_FDCAN, RCC_FDCANCKSELR, 0, 2), 469 MUX_CFG(MUX_FMC, RCC_FMCCKSELR, 0, 2), 470 MUX_CFG(MUX_I2C12, RCC_I2C12CKSELR, 0, 3), 471 MUX_CFG(MUX_I2C3, RCC_I2C345CKSELR, 0, 3), 472 MUX_CFG(MUX_I2C4, RCC_I2C345CKSELR, 3, 3), 473 MUX_CFG(MUX_I2C5, RCC_I2C345CKSELR, 6, 3), 474 MUX_CFG(MUX_LPTIM1, RCC_LPTIM1CKSELR, 0, 3), 475 MUX_CFG(MUX_LPTIM2, RCC_LPTIM23CKSELR, 0, 3), 476 MUX_CFG(MUX_LPTIM3, RCC_LPTIM23CKSELR, 3, 3), 477 MUX_CFG(MUX_LPTIM45, RCC_LPTIM45CKSELR, 0, 3), 478 MUX_CFG(MUX_MCO1, RCC_MCO1CFGR, 0, 3), 479 MUX_CFG(MUX_MCO2, RCC_MCO2CFGR, 0, 3), 480 MUX_CFG(MUX_QSPI, RCC_QSPICKSELR, 0, 2), 481 MUX_CFG(MUX_RNG1, RCC_RNG1CKSELR, 0, 2), 482 MUX_CFG(MUX_RTC, RCC_BDCR, 16, 2), 483 MUX_CFG(MUX_SAES, RCC_SAESCKSELR, 0, 2), 484 MUX_CFG(MUX_SAI1, RCC_SAI1CKSELR, 0, 3), 485 MUX_CFG(MUX_SAI2, RCC_SAI2CKSELR, 0, 3), 486 MUX_CFG(MUX_SDMMC1, RCC_SDMMC12CKSELR, 0, 3), 487 MUX_CFG(MUX_SDMMC2, RCC_SDMMC12CKSELR, 3, 3), 488 MUX_CFG(MUX_SPDIF, RCC_SPDIFCKSELR, 0, 2), 489 MUX_CFG(MUX_SPI1, RCC_SPI2S1CKSELR, 0, 3), 490 MUX_CFG(MUX_SPI23, RCC_SPI2S23CKSELR, 0, 3), 491 MUX_CFG(MUX_SPI4, RCC_SPI45CKSELR, 0, 3), 492 MUX_CFG(MUX_SPI5, RCC_SPI45CKSELR, 3, 3), 493 MUX_CFG(MUX_STGEN, RCC_STGENCKSELR, 0, 2), 494 MUX_CFG(MUX_UART1, RCC_UART12CKSELR, 0, 3), 495 MUX_CFG(MUX_UART2, RCC_UART12CKSELR, 3, 3), 496 MUX_CFG(MUX_UART35, RCC_UART35CKSELR, 0, 3), 497 MUX_CFG(MUX_UART4, RCC_UART4CKSELR, 0, 3), 498 MUX_CFG(MUX_UART6, RCC_UART6CKSELR, 0, 3), 499 MUX_CFG(MUX_UART78, RCC_UART78CKSELR, 0, 3), 500 MUX_CFG(MUX_USBO, RCC_USBCKSELR, 4, 1), 501 MUX_CFG(MUX_USBPHY, RCC_USBCKSELR, 0, 2), 502 }; 503 504 /* 505 * DIV CONFIG 506 */ 507 static const struct div_table_cfg axi_div_table[] = { 508 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, 509 { 4, 4 }, { 5, 4 }, { 6, 4 }, { 7, 4 }, 510 { 0 }, 511 }; 512 513 static const struct div_table_cfg mlahb_div_table[] = { 514 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, 515 { 4, 16 }, { 5, 32 }, { 6, 64 }, { 7, 128 }, 516 { 8, 256 }, { 9, 512 }, { 10, 512}, { 11, 512 }, 517 { 12, 512 }, { 13, 512 }, { 14, 512}, { 15, 512 }, 518 { 0 }, 519 }; 520 521 static const struct div_table_cfg apb_div_table[] = { 522 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, 523 { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 }, 524 { 0 }, 525 }; 526 527 #define DIVRDY_CFG(_id, _offset, _shift, _width, _flags, _table, _ready)\ 528 [(_id)] = {\ 529 .offset = (_offset),\ 530 .shift = (_shift),\ 531 .width = (_width),\ 532 .flags = (_flags),\ 533 .table = (_table),\ 534 .ready = (_ready),\ 535 } 536 537 #define DIV_CFG(_id, _offset, _shift, _width, _flags, _table)\ 538 DIVRDY_CFG(_id, _offset, _shift, _width, _flags, _table, DIV_NO_RDY) 539 540 static const struct div_cfg dividers_mp13[] = { 541 DIVRDY_CFG(DIV_MPU, RCC_MPCKDIVR, 0, 4, 0, NULL, 542 GATE_MPUDIVRDY), 543 DIVRDY_CFG(DIV_AXI, RCC_AXIDIVR, 0, 3, 0, axi_div_table, 544 GATE_AXIDIVRDY), 545 DIVRDY_CFG(DIV_MLAHB, RCC_MLAHBDIVR, 0, 4, 0, mlahb_div_table, 546 GATE_MLAHBDIVRDY), 547 DIVRDY_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 0, apb_div_table, 548 GATE_APB1DIVRDY), 549 DIVRDY_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 0, apb_div_table, 550 GATE_APB2DIVRDY), 551 DIVRDY_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 0, apb_div_table, 552 GATE_APB3DIVRDY), 553 DIVRDY_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 0, apb_div_table, 554 GATE_APB4DIVRDY), 555 DIVRDY_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 0, apb_div_table, 556 GATE_APB5DIVRDY), 557 DIVRDY_CFG(DIV_APB6, RCC_APB6DIVR, 0, 3, 0, apb_div_table, 558 GATE_APB6DIVRDY), 559 DIVRDY_CFG(DIV_HSI, RCC_HSICFGR, 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL, 560 GATE_HSIDIVRDY), 561 DIV_CFG(DIV_PLL1DIVP, RCC_PLL1CFGR2, 0, 7, 0, NULL), 562 DIV_CFG(DIV_PLL2DIVP, RCC_PLL2CFGR2, 0, 7, 0, NULL), 563 DIV_CFG(DIV_PLL2DIVQ, RCC_PLL2CFGR2, 8, 7, 0, NULL), 564 DIV_CFG(DIV_PLL2DIVR, RCC_PLL2CFGR2, 16, 7, 0, NULL), 565 DIV_CFG(DIV_PLL3DIVP, RCC_PLL3CFGR2, 0, 7, 0, NULL), 566 DIV_CFG(DIV_PLL3DIVQ, RCC_PLL3CFGR2, 8, 7, 0, NULL), 567 DIV_CFG(DIV_PLL3DIVR, RCC_PLL3CFGR2, 16, 7, 0, NULL), 568 DIV_CFG(DIV_PLL4DIVP, RCC_PLL4CFGR2, 0, 7, 0, NULL), 569 DIV_CFG(DIV_PLL4DIVQ, RCC_PLL4CFGR2, 8, 7, 0, NULL), 570 DIV_CFG(DIV_PLL4DIVR, RCC_PLL4CFGR2, 16, 7, 0, NULL), 571 DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL), 572 DIV_CFG(DIV_MCO1, RCC_MCO1CFGR, 4, 4, 0, NULL), 573 DIV_CFG(DIV_MCO2, RCC_MCO2CFGR, 4, 4, 0, NULL), 574 DIV_CFG(DIV_TRACE, RCC_DBGCFGR, 0, 3, CLK_DIVIDER_POWER_OF_TWO, NULL), 575 DIV_CFG(DIV_ETH1PTP, RCC_ETH12CKSELR, 4, 4, 0, NULL), 576 DIV_CFG(DIV_ETH2PTP, RCC_ETH12CKSELR, 12, 4, 0, NULL), 577 }; 578 579 enum stm32_osc { 580 OSC_HSI, 581 OSC_HSE, 582 OSC_CSI, 583 OSC_LSI, 584 OSC_LSE, 585 NB_OSCILLATOR 586 }; 587 588 struct stm32_osc_cfg { 589 int osc_id; 590 }; 591 592 struct clk_stm32_bypass { 593 uint16_t offset; 594 uint8_t bit_byp; 595 uint8_t bit_digbyp; 596 }; 597 598 struct clk_stm32_css { 599 uint16_t offset; 600 uint8_t bit_css; 601 }; 602 603 struct clk_stm32_drive { 604 uint16_t offset; 605 uint8_t drv_shift; 606 uint8_t drv_width; 607 uint8_t drv_default; 608 }; 609 610 struct clk_oscillator_data { 611 const char *name; 612 unsigned long frequency; 613 uint16_t gate_id; 614 struct clk_stm32_bypass *bypass; 615 struct clk_stm32_css *css; 616 struct clk_stm32_drive *drive; 617 }; 618 619 #define BYPASS(_offset, _bit_byp, _bit_digbyp) (&(struct clk_stm32_bypass){\ 620 .offset = (_offset),\ 621 .bit_byp = (_bit_byp),\ 622 .bit_digbyp = (_bit_digbyp),\ 623 }) 624 625 #define CSS(_offset, _bit_css) (&(struct clk_stm32_css){\ 626 .offset = (_offset),\ 627 .bit_css = (_bit_css),\ 628 }) 629 630 #define DRIVE(_offset, _shift, _width, _default) (&(struct clk_stm32_drive){\ 631 .offset = (_offset),\ 632 .drv_shift = (_shift),\ 633 .drv_width = (_width),\ 634 .drv_default = (_default),\ 635 }) 636 637 #define OSCILLATOR(idx_osc, _name, _gate_id, _bypass, _css, _drive) \ 638 [(idx_osc)] = (struct clk_oscillator_data){\ 639 .name = (_name),\ 640 .gate_id = (_gate_id),\ 641 .bypass = (_bypass),\ 642 .css = (_css),\ 643 .drive = (_drive),\ 644 } 645 646 static struct clk_oscillator_data stm32mp13_osc_data[NB_OSCILLATOR] = { 647 OSCILLATOR(OSC_HSI, "clk-hsi", GATE_HSI, 648 NULL, NULL, NULL), 649 650 OSCILLATOR(OSC_LSI, "clk-lsi", GATE_LSI, 651 NULL, NULL, NULL), 652 653 OSCILLATOR(OSC_CSI, "clk-csi", GATE_CSI, 654 NULL, NULL, NULL), 655 656 OSCILLATOR(OSC_LSE, "clk-lse", GATE_LSE, 657 BYPASS(RCC_BDCR, 1, 3), 658 CSS(RCC_BDCR, 8), 659 DRIVE(RCC_BDCR, 4, 2, 2)), 660 661 OSCILLATOR(OSC_HSE, "clk-hse", GATE_HSE, 662 BYPASS(RCC_OCENSETR, 10, 7), 663 CSS(RCC_OCENSETR, 11), 664 NULL), 665 }; 666 667 static struct clk_oscillator_data *clk_oscillator_get_data(int osc_id) 668 { 669 assert(osc_id >= 0 && osc_id < (int)ARRAY_SIZE(stm32mp13_osc_data)); 670 671 return &stm32mp13_osc_data[osc_id]; 672 } 673 674 static unsigned long clk_stm32_get_rate_oscillateur(int osc_id) 675 { 676 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 677 struct stm32_clk_platdata *pdata = priv->pdata; 678 struct stm32_osci_dt_cfg *osci = &pdata->osci[osc_id]; 679 680 return osci->freq; 681 } 682 683 static void clk_oscillator_set_bypass(struct clk_stm32_priv *priv, 684 struct clk_oscillator_data *osc_data, 685 bool digbyp, bool bypass) 686 { 687 struct clk_stm32_bypass *bypass_data = osc_data->bypass; 688 uintptr_t address = 0; 689 690 if (!bypass_data) 691 return; 692 693 address = priv->base + bypass_data->offset; 694 695 if (digbyp) 696 io_setbits32(address, BIT(bypass_data->bit_digbyp)); 697 698 if (bypass || digbyp) 699 io_setbits32(address, BIT(bypass_data->bit_byp)); 700 } 701 702 static void clk_oscillator_set_css(struct clk_stm32_priv *priv, 703 struct clk_oscillator_data *osc_data, 704 bool css) 705 { 706 struct clk_stm32_css *css_data = osc_data->css; 707 uintptr_t address = 0; 708 709 if (!css_data) 710 return; 711 712 address = priv->base + css_data->offset; 713 714 if (css) 715 io_setbits32(address, BIT(css_data->bit_css)); 716 } 717 718 static void clk_oscillator_set_drive(struct clk_stm32_priv *priv, 719 struct clk_oscillator_data *osc_data, 720 uint8_t lsedrv) 721 { 722 struct clk_stm32_drive *drive_data = osc_data->drive; 723 uintptr_t address = 0; 724 uint32_t mask = 0; 725 uint32_t value = 0; 726 727 if (!drive_data) 728 return; 729 730 address = priv->base + drive_data->offset; 731 732 mask = (BIT(drive_data->drv_width) - 1U) << drive_data->drv_shift; 733 734 /* 735 * Warning: not recommended to switch directly from "high drive" 736 * to "medium low drive", and vice-versa. 737 */ 738 value = (io_read32(address) & mask) >> drive_data->drv_shift; 739 740 while (value != lsedrv) { 741 if (value > lsedrv) 742 value--; 743 else 744 value++; 745 746 io_clrsetbits32(address, mask, value << drive_data->drv_shift); 747 } 748 } 749 750 static void stm32_enable_oscillator_hse(struct clk_stm32_priv *priv, 751 struct stm32_clk_platdata *pdata) 752 { 753 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_HSE); 754 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_HSE]; 755 756 if (osci->freq == 0U) 757 return; 758 759 clk_oscillator_set_bypass(priv, osc_data, osci->digbyp, osci->bypass); 760 761 /* Enable clock and wait ready bit */ 762 if (stm32_gate_rdy_enable(osc_data->gate_id)) { 763 EMSG("timeout to enable hse clock"); 764 panic(); 765 } 766 767 clk_oscillator_set_css(priv, osc_data, osci->css); 768 } 769 770 static void stm32_enable_oscillator_lse(struct clk_stm32_priv *priv, 771 struct stm32_clk_platdata *pdata) 772 { 773 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_LSE); 774 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE]; 775 776 if (osci->freq == 0U) 777 return; 778 779 clk_oscillator_set_bypass(priv, osc_data, osci->digbyp, osci->bypass); 780 781 clk_oscillator_set_drive(priv, osc_data, osci->drive); 782 783 /* Enable lse clock, but don't wait ready bit */ 784 stm32_gate_enable(osc_data->gate_id); 785 } 786 787 static void 788 stm32_enable_oscillator_lsi(struct clk_stm32_priv *priv __maybe_unused, 789 struct stm32_clk_platdata *pdata) 790 { 791 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_LSI); 792 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSI]; 793 794 if (osci->freq == 0U) 795 return; 796 797 /* Enable clock and wait ready bit */ 798 if (stm32_gate_rdy_enable(osc_data->gate_id)) { 799 EMSG("timeout to enable lsi clock"); 800 panic(); 801 } 802 } 803 804 static void 805 stm32_enable_oscillator_csi(struct clk_stm32_priv *priv __maybe_unused, 806 struct stm32_clk_platdata *pdata) 807 { 808 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_CSI); 809 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_CSI]; 810 811 if (osci->freq == 0U) 812 return; 813 814 /* Enable clock and wait ready bit */ 815 if (stm32_gate_rdy_enable(osc_data->gate_id)) { 816 EMSG("timeout to enable csi clock"); 817 panic(); 818 } 819 } 820 821 static int stm32_clk_oscillators_lse_set_css(struct clk_stm32_priv *priv, 822 struct stm32_clk_platdata *pdata) 823 824 { 825 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_LSE); 826 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE]; 827 828 clk_oscillator_set_css(priv, osc_data, osci->css); 829 830 return 0; 831 } 832 833 static int 834 stm32_clk_oscillators_wait_lse_ready(struct clk_stm32_priv *priv __maybe_unused, 835 struct stm32_clk_platdata *pdata) 836 { 837 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_LSE); 838 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE]; 839 840 if (osci->freq == 0U) 841 return 0; 842 843 if (stm32_gate_wait_ready(osc_data->gate_id, true)) 844 return -1; 845 846 return 0; 847 } 848 849 static void stm32_clk_oscillators_enable(struct clk_stm32_priv *priv, 850 struct stm32_clk_platdata *pdata) 851 { 852 stm32_enable_oscillator_hse(priv, pdata); 853 stm32_enable_oscillator_lse(priv, pdata); 854 stm32_enable_oscillator_lsi(priv, pdata); 855 stm32_enable_oscillator_csi(priv, pdata); 856 } 857 858 enum stm32_pll_id { 859 PLL1_ID, 860 PLL2_ID, 861 PLL3_ID, 862 PLL4_ID, 863 PLL_NB 864 }; 865 866 enum stm32mp1_plltype { 867 PLL_800, 868 PLL_1600, 869 PLL_2000, 870 PLL_TYPE_NB 871 }; 872 873 #define RCC_OFFSET_PLLXCR 0 874 #define RCC_OFFSET_PLLXCFGR1 4 875 #define RCC_OFFSET_PLLXCFGR2 8 876 #define RCC_OFFSET_PLLXFRACR 12 877 #define RCC_OFFSET_PLLXCSGR 16 878 879 struct stm32_clk_pll { 880 enum stm32mp1_plltype plltype; 881 uint16_t gate_id; 882 uint16_t mux_id; 883 uint16_t reg_pllxcr; 884 }; 885 886 struct stm32mp1_pll { 887 uint8_t refclk_min; 888 uint8_t refclk_max; 889 }; 890 891 /* Define characteristic of PLL according type */ 892 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 893 [PLL_800] = { 894 .refclk_min = 4, 895 .refclk_max = 16, 896 }, 897 [PLL_1600] = { 898 .refclk_min = 8, 899 .refclk_max = 16, 900 }, 901 [PLL_2000] = { 902 .refclk_min = 8, 903 .refclk_max = 16, 904 } 905 }; 906 907 #define CLK_PLL_CFG(_idx, _type, _gate_id, _mux_id, _reg)\ 908 [(_idx)] = {\ 909 .gate_id = (_gate_id),\ 910 .mux_id = (_mux_id),\ 911 .plltype = (_type),\ 912 .reg_pllxcr = (_reg),\ 913 } 914 915 static const struct stm32_clk_pll stm32_mp13_clk_pll[PLL_NB] = { 916 CLK_PLL_CFG(PLL1_ID, PLL_2000, GATE_PLL1, MUX_PLL12, RCC_PLL1CR), 917 CLK_PLL_CFG(PLL2_ID, PLL_1600, GATE_PLL2, MUX_PLL12, RCC_PLL2CR), 918 CLK_PLL_CFG(PLL3_ID, PLL_800, GATE_PLL3, MUX_PLL3, RCC_PLL3CR), 919 CLK_PLL_CFG(PLL4_ID, PLL_800, GATE_PLL4, MUX_PLL4, RCC_PLL4CR), 920 }; 921 922 static const struct stm32_clk_pll *clk_stm32_pll_data(unsigned int idx) 923 { 924 return &stm32_mp13_clk_pll[idx]; 925 } 926 927 /* Clock TREE configuration */ 928 929 static unsigned int stm32_clk_configure_clk_get_binding_id(uint32_t data) 930 { 931 return (data & CLK_ID_MASK) >> CLK_ID_SHIFT; 932 } 933 934 static int stm32_clk_configure_clk(struct clk_stm32_priv *priv __maybe_unused, 935 uint32_t data) 936 { 937 int sel = (data & CLK_SEL_MASK) >> CLK_SEL_SHIFT; 938 int enable = (data & CLK_ON_MASK) >> CLK_ON_SHIFT; 939 int clk_id = 0; 940 int ret = 0; 941 int mux = -1; 942 int gate = -1; 943 944 clk_id = stm32_clk_configure_clk_get_binding_id(data); 945 946 switch (clk_id) { 947 case CK_MCO1: 948 mux = MUX_MCO1; 949 gate = GATE_MCO1; 950 break; 951 952 case CK_MCO2: 953 mux = MUX_MCO2; 954 gate = GATE_MCO2; 955 break; 956 default: 957 ret = -1; 958 break; 959 } 960 961 if (ret != 0) 962 return ret; 963 964 if (stm32_mux_set_parent(mux, sel)) 965 return -1; 966 967 if (enable) 968 stm32_gate_enable(gate); 969 else 970 stm32_gate_disable(gate); 971 972 return 0; 973 } 974 975 static int stm32_clk_configure_mux(__unused struct clk_stm32_priv *priv, 976 uint32_t data) 977 { 978 int mux = (data & MUX_ID_MASK) >> MUX_ID_SHIFT; 979 int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT; 980 981 if (mux == MUX_RTC) { 982 /* Mux RTC clock only is selector is valid and RTC not yet 983 * enabled 984 */ 985 if (sel == 0) 986 return 0; 987 988 if (stm32_gate_is_enabled(GATE_RTCCK)) 989 return 0; 990 } 991 992 if (stm32_mux_set_parent(mux, sel)) 993 return -1; 994 995 return 0; 996 } 997 998 static TEE_Result 999 stm32_clk_configure_div(struct clk_stm32_priv *priv __maybe_unused, 1000 uint32_t data) 1001 { 1002 int div_id = (data & DIV_ID_MASK) >> DIV_ID_SHIFT; 1003 int div_n = (data & DIV_DIVN_MASK) >> DIV_DIVN_SHIFT; 1004 1005 return stm32_div_set_value(div_id, div_n); 1006 } 1007 1008 static int stm32_clk_dividers_configure(struct clk_stm32_priv *priv) 1009 { 1010 struct stm32_clk_platdata *pdata = priv->pdata; 1011 unsigned int i = 0; 1012 1013 for (i = 0; i < pdata->nclkdiv; i++) { 1014 if (stm32_clk_configure_div(priv, pdata->clkdiv[i])) 1015 return -1; 1016 } 1017 1018 return 0; 1019 } 1020 1021 static int stm32_clk_source_configure(struct clk_stm32_priv *priv) 1022 { 1023 struct stm32_clk_platdata *pdata = priv->pdata; 1024 bool ckper_disabled = false; 1025 int ret = 0; 1026 size_t i = 0; 1027 1028 for (i = 0; i < pdata->nclksrc; i++) { 1029 uint32_t val = pdata->clksrc[i]; 1030 uint32_t cmd = 0; 1031 uint32_t cmd_data = 0; 1032 1033 if (val == (uint32_t)CLK_CKPER_DISABLED) { 1034 ckper_disabled = true; 1035 continue; 1036 } 1037 1038 cmd = (val & CMD_MASK) >> CMD_SHIFT; 1039 cmd_data = val & ~CMD_MASK; 1040 1041 switch (cmd) { 1042 case CMD_MUX: 1043 ret = stm32_clk_configure_mux(priv, cmd_data); 1044 break; 1045 1046 case CMD_CLK: 1047 ret = stm32_clk_configure_clk(priv, cmd_data); 1048 break; 1049 default: 1050 ret = -1; 1051 break; 1052 } 1053 1054 if (ret != 0) 1055 return ret; 1056 } 1057 1058 /* 1059 * CKPER is source for some peripheral clocks 1060 * (FMC-NAND / QPSI-NOR) and switching source is allowed 1061 * only if previous clock is still ON 1062 * => deactivate CKPER only after switching clock 1063 */ 1064 if (ckper_disabled) { 1065 ret = stm32_clk_configure_mux(priv, 1066 CLK_CKPER_DISABLED & CMD_MASK); 1067 if (ret != 0) 1068 return ret; 1069 } 1070 1071 return 0; 1072 } 1073 1074 static unsigned long clk_stm32_pll_get_oscillator_rate(int sel) 1075 { 1076 const int osc[] = { OSC_HSI, OSC_HSE, OSC_CSI }; 1077 1078 assert(sel >= 0 && sel < (int)ARRAY_SIZE(osc)); 1079 1080 return clk_stm32_get_rate_oscillateur(osc[sel]); 1081 } 1082 1083 static int clk_stm32_pll_compute_cfgr1(const struct stm32_clk_pll *pll, 1084 struct stm32_pll_vco *vco, 1085 uint32_t *value) 1086 { 1087 int sel = (vco->src & MUX_SEL_MASK) >> MUX_SEL_SHIFT; 1088 uint32_t divm = vco->div_mn[PLL_CFG_M]; 1089 uint32_t divn = vco->div_mn[PLL_CFG_N]; 1090 unsigned long refclk = 0UL; 1091 1092 refclk = clk_stm32_pll_get_oscillator_rate(sel) / (divm + 1U); 1093 1094 if ((refclk < (stm32mp1_pll[pll->plltype].refclk_min * 1000000U)) || 1095 (refclk > (stm32mp1_pll[pll->plltype].refclk_max * 1000000U))) 1096 return -1; 1097 1098 *value = 0; 1099 1100 if (pll->plltype == PLL_800 && refclk >= 8000000U) 1101 *value = 1U << RCC_PLLNCFGR1_IFRGE_SHIFT; 1102 1103 *value |= (divn << RCC_PLLNCFGR1_DIVN_SHIFT) & RCC_PLLNCFGR1_DIVN_MASK; 1104 *value |= (divm << RCC_PLLNCFGR1_DIVM_SHIFT) & RCC_PLLNCFGR1_DIVM_MASK; 1105 1106 return 0; 1107 } 1108 1109 static uint32_t clk_stm32_pll_compute_cfgr2(struct stm32_pll_output *out) 1110 { 1111 uint32_t value = 0; 1112 1113 value |= (out->output[PLL_CFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1114 RCC_PLLNCFGR2_DIVP_MASK; 1115 value |= (out->output[PLL_CFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1116 RCC_PLLNCFGR2_DIVQ_MASK; 1117 value |= (out->output[PLL_CFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1118 RCC_PLLNCFGR2_DIVR_MASK; 1119 1120 return value; 1121 } 1122 1123 /* 1124 * Check if PLL1 can be configured on the fly. 1125 * @result (-1) => config on the fly is not possible. 1126 * (0) => config on the fly is possible. 1127 * (+1) => same parameters, no need to reconfigure. 1128 * Return value is 0 if no error. 1129 */ 1130 static int clk_stm32_is_pll_config_on_the_fly(struct clk_stm32_priv *priv, 1131 const struct stm32_clk_pll *pll, 1132 struct stm32_pll_dt_cfg *pll_conf, 1133 int *result) 1134 { 1135 uintptr_t pll_base = priv->base + pll->reg_pllxcr; 1136 struct stm32_pll_vco *vco = &pll_conf->vco; 1137 struct stm32_pll_output *out = &pll_conf->output; 1138 uint32_t fracr = 0; 1139 uint32_t value = 0; 1140 int ret = 0; 1141 size_t sel = 0; 1142 1143 ret = clk_stm32_pll_compute_cfgr1(pll, vco, &value); 1144 if (ret != 0) 1145 return ret; 1146 1147 sel = (vco->src & MUX_SEL_MASK) >> MUX_SEL_SHIFT; 1148 if (sel != stm32_mux_get_parent(pll->mux_id)) { 1149 /* Clock source of the PLL is different */ 1150 *result = -1; 1151 return 0; 1152 } 1153 1154 if (io_read32(pll_base + RCC_OFFSET_PLLXCFGR1) != value) { 1155 /* Different DIVN/DIVM, can't config on the fly */ 1156 *result = -1; 1157 return 0; 1158 } 1159 1160 *result = 1; 1161 1162 fracr = vco->frac << RCC_PLLNFRACR_FRACV_SHIFT; 1163 fracr |= RCC_PLLNCFGR1_DIVM_MASK; 1164 value = clk_stm32_pll_compute_cfgr2(out); 1165 1166 if ((io_read32(pll_base + RCC_OFFSET_PLLXFRACR) == fracr) && 1167 (io_read32(pll_base + RCC_OFFSET_PLLXCFGR2) == value)) { 1168 /* Same parameters, no need to config */ 1169 *result = 1; 1170 } else { 1171 *result = 0; 1172 } 1173 1174 return 0; 1175 } 1176 1177 static int stm32_clk_hsidiv_configure(struct clk_stm32_priv *priv) 1178 { 1179 struct stm32_clk_platdata *pdata = priv->pdata; 1180 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_HSI]; 1181 1182 return stm32_div_set_rate(DIV_HSI, osci->freq, MAX_HSI_HZ); 1183 } 1184 1185 static void clk_stm32_pll_config_vco(struct clk_stm32_priv *priv, 1186 const struct stm32_clk_pll *pll, 1187 struct stm32_pll_vco *vco) 1188 { 1189 uintptr_t pll_base = priv->base + pll->reg_pllxcr; 1190 uint32_t value = 0; 1191 1192 if (clk_stm32_pll_compute_cfgr1(pll, vco, &value) != 0) { 1193 EMSG("Invalid Vref clock"); 1194 panic(); 1195 } 1196 1197 /* Write N / M / IFREGE fields */ 1198 io_write32(pll_base + RCC_OFFSET_PLLXCFGR1, value); 1199 1200 /* Fractional configuration */ 1201 io_write32(pll_base + RCC_OFFSET_PLLXFRACR, 0); 1202 1203 /* Frac must be enabled only once its configuration is loaded */ 1204 io_write32(pll_base + RCC_OFFSET_PLLXFRACR, 1205 vco->frac << RCC_PLLNFRACR_FRACV_SHIFT); 1206 1207 io_setbits32(pll_base + RCC_OFFSET_PLLXFRACR, RCC_PLLNFRACR_FRACLE); 1208 } 1209 1210 static void clk_stm32_pll_config_csg(struct clk_stm32_priv *priv, 1211 const struct stm32_clk_pll *pll, 1212 struct stm32_pll_vco *vco) 1213 { 1214 uintptr_t pll_base = priv->base + pll->reg_pllxcr; 1215 uint32_t mod_per = 0; 1216 uint32_t inc_step = 0; 1217 uint32_t sscg_mode = 0; 1218 uint32_t value = 0; 1219 1220 if (!vco->csg_enabled) 1221 return; 1222 1223 mod_per = vco->csg[PLL_CSG_MOD_PER]; 1224 inc_step = vco->csg[PLL_CSG_INC_STEP]; 1225 sscg_mode = vco->csg[PLL_CSG_SSCG_MODE]; 1226 1227 value |= (mod_per << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1228 RCC_PLLNCSGR_MOD_PER_MASK; 1229 value |= (inc_step << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1230 RCC_PLLNCSGR_INC_STEP_MASK; 1231 value |= (sscg_mode << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1232 RCC_PLLNCSGR_SSCG_MODE_MASK; 1233 1234 io_write32(pll_base + RCC_OFFSET_PLLXCSGR, value); 1235 io_setbits32(pll_base + RCC_OFFSET_PLLXCR, RCC_PLLNCR_SSCG_CTRL); 1236 } 1237 1238 static void clk_stm32_pll_config_out(struct clk_stm32_priv *priv, 1239 const struct stm32_clk_pll *pll, 1240 struct stm32_pll_output *out) 1241 { 1242 uintptr_t pll_base = priv->base + pll->reg_pllxcr; 1243 uint32_t value = 0; 1244 1245 value = clk_stm32_pll_compute_cfgr2(out); 1246 1247 io_write32(pll_base + RCC_OFFSET_PLLXCFGR2, value); 1248 } 1249 1250 static struct stm32_pll_dt_cfg *clk_stm32_pll_get_pdata(int pll_idx) 1251 { 1252 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 1253 struct stm32_clk_platdata *pdata = priv->pdata; 1254 1255 return &pdata->pll[pll_idx]; 1256 } 1257 1258 static int clk_stm32_pll_init_switch_to_hsi_clk_system(int mux_sys) 1259 { 1260 int sel = 0; 1261 1262 if (mux_sys == -1) 1263 return -1; 1264 1265 /* Make a backup to the current parent */ 1266 sel = stm32_mux_get_parent(mux_sys); 1267 1268 /* Switch to HSI */ 1269 if (stm32_mux_set_parent(mux_sys, 0)) 1270 return -1; 1271 1272 return sel; 1273 } 1274 1275 static uint32_t 1276 clk_stm32_pll_backup_output_diven(const struct stm32_clk_pll *pll) 1277 { 1278 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 1279 uintptr_t addr = priv->base + pll->reg_pllxcr; 1280 1281 return io_read32(addr + RCC_OFFSET_PLLXCR) & 1282 (RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1283 RCC_PLLNCR_DIVREN); 1284 } 1285 1286 static void clk_stm32_pll_restore_output_diven(const struct stm32_clk_pll *pll, 1287 uint32_t value) 1288 { 1289 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 1290 uintptr_t addr = priv->base + pll->reg_pllxcr; 1291 const uint32_t mask = RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1292 RCC_PLLNCR_DIVREN; 1293 1294 io_clrsetbits32(addr, mask, value & mask); 1295 } 1296 1297 static int clk_stm32_pll_init(struct clk_stm32_priv *priv, int pll_idx, 1298 struct stm32_pll_dt_cfg *pll_conf) 1299 { 1300 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_idx); 1301 int config_on_the_fly = -1; 1302 int ret = 0; 1303 uint8_t sel = 0; 1304 uint32_t save_div_pqr_en = 0; 1305 int mux_system[] = { MUX_MPU, MUX_AXI, MUX_MLAHB, -1 }; 1306 int mux_sys = mux_system[pll_idx]; 1307 1308 ret = clk_stm32_is_pll_config_on_the_fly(priv, pll, pll_conf, 1309 &config_on_the_fly); 1310 if (ret != 0) 1311 return ret; 1312 1313 /* Backup status of DIV DIVPEN / DIVQEN / DIVREN */ 1314 save_div_pqr_en = clk_stm32_pll_backup_output_diven(pll); 1315 1316 if (config_on_the_fly == -1) { 1317 /* Make a backup to the current parent and switch to HSI */ 1318 sel = clk_stm32_pll_init_switch_to_hsi_clk_system(mux_sys); 1319 1320 /* Stop the PLL before */ 1321 if (stm32_gate_is_enabled(pll->gate_id)) { 1322 io_clrbits32(priv->base + pll->reg_pllxcr, 1323 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1324 RCC_PLLNCR_DIVREN); 1325 1326 if (stm32_gate_rdy_disable(pll->gate_id)) 1327 return -1; 1328 } 1329 1330 /* Configure PLLs source */ 1331 ret = stm32_clk_configure_mux(priv, pll_conf->vco.src); 1332 if (ret) 1333 return ret; 1334 1335 clk_stm32_pll_config_vco(priv, pll, &pll_conf->vco); 1336 } 1337 1338 if (config_on_the_fly != 1) { 1339 clk_stm32_pll_config_out(priv, pll, &pll_conf->output); 1340 clk_stm32_pll_config_csg(priv, pll, &pll_conf->vco); 1341 } 1342 1343 if (!stm32_gate_is_enabled(pll->gate_id)) { 1344 if (stm32_gate_rdy_enable(pll->gate_id)) 1345 return -1; 1346 1347 clk_stm32_pll_restore_output_diven(pll, save_div_pqr_en); 1348 } 1349 1350 if ((config_on_the_fly == -1) && (mux_sys != -1)) { 1351 /* Restore to backup parent */ 1352 if (stm32_mux_set_parent(mux_sys, sel)) 1353 return -1; 1354 } 1355 1356 return 0; 1357 } 1358 1359 static int stm32_clk_pll_configure(struct clk_stm32_priv *priv) 1360 { 1361 struct stm32_pll_dt_cfg *pll_conf = NULL; 1362 size_t i = 0; 1363 const int plls[] = { PLL1_ID, PLL3_ID, PLL4_ID }; 1364 1365 for (i = 0; i < ARRAY_SIZE(plls); i++) { 1366 pll_conf = clk_stm32_pll_get_pdata(plls[i]); 1367 1368 if (pll_conf->vco.status) { 1369 int err = 0; 1370 1371 err = clk_stm32_pll_init(priv, plls[i], pll_conf); 1372 if (err) 1373 return err; 1374 } 1375 } 1376 1377 return 0; 1378 } 1379 1380 static int stm32mp1_init_clock_tree(struct clk_stm32_priv *priv, 1381 struct stm32_clk_platdata *pdata) 1382 { 1383 int ret = 0; 1384 1385 /* 1386 * Switch ON oscillators found in device-tree. 1387 * Note: HSI already ON after BootROM stage. 1388 */ 1389 stm32_clk_oscillators_enable(priv, pdata); 1390 1391 ret = stm32_clk_hsidiv_configure(priv); 1392 if (ret != 0) 1393 return ret; 1394 1395 ret = stm32_clk_dividers_configure(priv); 1396 if (ret != 0) 1397 panic(); 1398 1399 ret = stm32_clk_pll_configure(priv); 1400 if (ret != 0) 1401 panic(); 1402 1403 /* Wait LSE ready before to use it */ 1404 ret = stm32_clk_oscillators_wait_lse_ready(priv, pdata); 1405 if (ret != 0) 1406 panic(); 1407 1408 /* Configure with expected clock source */ 1409 ret = stm32_clk_source_configure(priv); 1410 if (ret != 0) 1411 panic(); 1412 1413 /* Configure LSE CSS after RTC source configuration */ 1414 ret = stm32_clk_oscillators_lse_set_css(priv, pdata); 1415 if (ret != 0) 1416 panic(); 1417 1418 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 1419 io_clrsetbits32(priv->base + RCC_DDRITFCR, RCC_DDRITFCR_DDRCKMOD_MASK, 1420 RCC_DDRITFCR_DDRCKMOD_SSR << 1421 RCC_DDRITFCR_DDRCKMOD_SHIFT); 1422 1423 return 0; 1424 } 1425 1426 static int clk_stm32_parse_oscillator_fdt(const void *fdt, int node, 1427 const char *name, 1428 struct stm32_osci_dt_cfg *osci) 1429 { 1430 int subnode = 0; 1431 1432 fdt_for_each_subnode(subnode, fdt, node) { 1433 const char *cchar = NULL; 1434 const fdt32_t *cuint = NULL; 1435 int ret = 0; 1436 1437 cchar = fdt_get_name(fdt, subnode, &ret); 1438 if (!cchar) 1439 return ret; 1440 1441 if (strncmp(cchar, name, (size_t)ret) || 1442 fdt_get_status(fdt, subnode) == DT_STATUS_DISABLED) 1443 continue; 1444 1445 cuint = fdt_getprop(fdt, subnode, "clock-frequency", &ret); 1446 if (!cuint) 1447 panic(); 1448 1449 osci->freq = fdt32_to_cpu(*cuint); 1450 1451 if (fdt_getprop(fdt, subnode, "st,bypass", NULL)) 1452 osci->bypass = true; 1453 1454 if (fdt_getprop(fdt, subnode, "st,digbypass", NULL)) 1455 osci->digbyp = true; 1456 1457 if (fdt_getprop(fdt, subnode, "st,css", NULL)) 1458 osci->css = true; 1459 1460 osci->drive = fdt_read_uint32_default(fdt, subnode, "st,drive", 1461 LSEDRV_MEDIUM_HIGH); 1462 1463 return 0; 1464 } 1465 1466 return -FDT_ERR_NOTFOUND; 1467 } 1468 1469 static int stm32_clk_parse_fdt_all_oscillator(const void *fdt, 1470 int node __maybe_unused, 1471 struct stm32_clk_platdata *pdata) 1472 { 1473 int fdt_err = 0; 1474 size_t i = 0; 1475 int osc_node = 0; 1476 1477 osc_node = fdt_path_offset(fdt, "/clocks"); 1478 if (osc_node < 0) 1479 return -FDT_ERR_NOTFOUND; 1480 1481 for (i = 0; i < NB_OSCILLATOR; i++) { 1482 struct stm32_osci_dt_cfg *osci = &pdata->osci[i]; 1483 struct clk_oscillator_data *osc_data = NULL; 1484 1485 osc_data = clk_oscillator_get_data(i); 1486 1487 fdt_err = clk_stm32_parse_oscillator_fdt(fdt, osc_node, 1488 osc_data->name, osci); 1489 if (fdt_err < 0) 1490 panic(); 1491 } 1492 1493 return 0; 1494 } 1495 1496 static int clk_stm32_load_vco_config_fdt(const void *fdt, int subnode, 1497 struct stm32_pll_vco *vco) 1498 { 1499 int ret = 0; 1500 1501 ret = fdt_read_uint32_array(fdt, subnode, "divmn", vco->div_mn, 1502 PLL_DIV_MN_NB); 1503 if (ret != 0) 1504 return ret; 1505 1506 ret = fdt_read_uint32_array(fdt, subnode, "csg", vco->csg, 1507 PLL_CSG_NB); 1508 1509 vco->csg_enabled = (ret == 0); 1510 1511 if (ret == -FDT_ERR_NOTFOUND) 1512 ret = 0; 1513 1514 if (ret != 0) 1515 return ret; 1516 1517 vco->status = RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1518 RCC_PLLNCR_DIVREN | RCC_PLLNCR_PLLON; 1519 1520 vco->frac = fdt_read_uint32_default(fdt, subnode, "frac", 0); 1521 1522 vco->src = fdt_read_uint32_default(fdt, subnode, "src", UINT32_MAX); 1523 1524 return 0; 1525 } 1526 1527 static int clk_stm32_load_output_config_fdt(const void *fdt, int subnode, 1528 struct stm32_pll_output *output) 1529 { 1530 return fdt_read_uint32_array(fdt, subnode, "st,pll_div_pqr", 1531 output->output, (int)PLL_DIV_PQR_NB); 1532 } 1533 1534 static int clk_stm32_parse_pll_fdt(const void *fdt, int subnode, 1535 struct stm32_pll_dt_cfg *pll) 1536 { 1537 const fdt32_t *cuint = NULL; 1538 int subnode_pll = 0; 1539 int subnode_vco = 0; 1540 int err = 0; 1541 1542 cuint = fdt_getprop(fdt, subnode, "st,pll", NULL); 1543 if (!cuint) 1544 return -FDT_ERR_NOTFOUND; 1545 1546 subnode_pll = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 1547 if (subnode_pll < 0) 1548 return -FDT_ERR_NOTFOUND; 1549 1550 cuint = fdt_getprop(fdt, subnode_pll, "st,pll_vco", NULL); 1551 if (!cuint) 1552 return -FDT_ERR_NOTFOUND; 1553 1554 subnode_vco = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 1555 if (subnode_vco < 0) 1556 return -FDT_ERR_NOTFOUND; 1557 1558 err = clk_stm32_load_vco_config_fdt(fdt, subnode_vco, &pll->vco); 1559 if (err != 0) 1560 return err; 1561 1562 err = clk_stm32_load_output_config_fdt(fdt, subnode_pll, &pll->output); 1563 if (err != 0) 1564 return err; 1565 1566 return 0; 1567 } 1568 1569 static int stm32_clk_parse_fdt_all_pll(const void *fdt, int node, 1570 struct stm32_clk_platdata *pdata) 1571 { 1572 size_t i = 0; 1573 1574 for (i = PLL1_ID; i < pdata->npll; i++) { 1575 struct stm32_pll_dt_cfg *pll = pdata->pll + i; 1576 char name[RCC_PLL_NAME_SIZE] = { 0 }; 1577 int subnode = 0; 1578 int err = 0; 1579 1580 snprintf(name, sizeof(name), "st,pll@%d", i); 1581 1582 subnode = fdt_subnode_offset(fdt, node, name); 1583 if (subnode < 0) 1584 continue; 1585 1586 err = clk_stm32_parse_pll_fdt(fdt, subnode, pll); 1587 if (err != 0) 1588 panic(); 1589 } 1590 1591 return 0; 1592 } 1593 1594 static int stm32_clk_parse_fdt_opp(const void *fdt, int node, 1595 const char *opp_name, 1596 struct stm32_clk_opp_cfg *opp_cfg) 1597 { 1598 int subnode = 0; 1599 int nb_opp = 0; 1600 int ret = 0; 1601 1602 node = fdt_subnode_offset(fdt, node, opp_name); 1603 if (node == -FDT_ERR_NOTFOUND) 1604 return 0; 1605 if (node < 0) 1606 return node; 1607 1608 fdt_for_each_subnode(subnode, fdt, node) { 1609 if (nb_opp >= MAX_OPP) { 1610 EMSG("%d MAX opp in %s", MAX_OPP, opp_name); 1611 panic(); 1612 } 1613 1614 opp_cfg->frq = fdt_read_uint32_default(fdt, subnode, 1615 "hz", 1616 UINT32_MAX); 1617 1618 opp_cfg->src = fdt_read_uint32_default(fdt, subnode, 1619 "st,clksrc", 1620 UINT32_MAX); 1621 1622 opp_cfg->div = fdt_read_uint32_default(fdt, subnode, 1623 "st,clkdiv", 1624 UINT32_MAX); 1625 1626 ret = clk_stm32_parse_pll_fdt(fdt, subnode, &opp_cfg->pll_cfg); 1627 if (ret) 1628 return ret; 1629 1630 opp_cfg++; 1631 nb_opp++; 1632 } 1633 1634 return 0; 1635 } 1636 1637 static int stm32_clk_parse_fdt_all_opp(const void *fdt, int node, 1638 struct stm32_clk_platdata *pdata) 1639 { 1640 struct stm32_clk_opp_dt_cfg *opp = pdata->opp; 1641 int ret = 0; 1642 1643 node = fdt_subnode_offset(fdt, node, "st,clk_opp"); 1644 /* No opp are defined */ 1645 if (node == -FDT_ERR_NOTFOUND) 1646 return 0; 1647 if (node < 0) 1648 return node; 1649 1650 ret = stm32_clk_parse_fdt_opp(fdt, node, "st,ck_mpu", opp->mpu_opp); 1651 if (ret) 1652 return ret; 1653 1654 ret = stm32_clk_parse_fdt_opp(fdt, node, "st,ck_axi", opp->axi_opp); 1655 if (ret) 1656 return ret; 1657 1658 ret = stm32_clk_parse_fdt_opp(fdt, node, "st,ck_mlahbs", 1659 opp->mlahbs_opp); 1660 if (ret) 1661 return ret; 1662 1663 return 0; 1664 } 1665 1666 static int stm32_clk_parse_fdt(const void *fdt, int node, 1667 struct stm32_clk_platdata *pdata) 1668 { 1669 int err = 0; 1670 1671 err = stm32_clk_parse_fdt_all_oscillator(fdt, node, pdata); 1672 if (err != 0) 1673 return err; 1674 1675 err = stm32_clk_parse_fdt_all_pll(fdt, node, pdata); 1676 if (err != 0) 1677 return err; 1678 1679 err = stm32_clk_parse_fdt_all_opp(fdt, node, pdata); 1680 if (err != 0) 1681 return err; 1682 1683 err = clk_stm32_parse_fdt_by_name(fdt, node, "st,clkdiv", pdata->clkdiv, 1684 &pdata->nclkdiv); 1685 if (err != 0) 1686 return err; 1687 1688 err = clk_stm32_parse_fdt_by_name(fdt, node, "st,clksrc", pdata->clksrc, 1689 &pdata->nclksrc); 1690 if (err != 0) 1691 return err; 1692 1693 return 0; 1694 } 1695 1696 struct clk_stm32_pll_cfg { 1697 uint32_t reg_pllxcr; 1698 int gate_id; 1699 int mux_id; 1700 }; 1701 1702 static size_t clk_stm32_pll_get_parent(struct clk *clk) 1703 { 1704 struct clk_stm32_pll_cfg *cfg = clk->priv; 1705 1706 return stm32_mux_get_parent(cfg->mux_id); 1707 } 1708 1709 static unsigned long clk_stm32_pll_get_rate(struct clk *clk, 1710 unsigned long prate) 1711 { 1712 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 1713 struct clk_stm32_pll_cfg *cfg = clk->priv; 1714 uintptr_t pll_base = priv->base + cfg->reg_pllxcr; 1715 uint32_t cfgr1 = 0; 1716 uint32_t fracr = 0; 1717 uint32_t divm = 0; 1718 uint32_t divn = 0; 1719 unsigned long fvco = 0UL; 1720 1721 cfgr1 = io_read32(pll_base + RCC_OFFSET_PLLXCFGR1); 1722 fracr = io_read32(pll_base + RCC_OFFSET_PLLXFRACR); 1723 1724 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 1725 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 1726 1727 /* 1728 * With FRACV : 1729 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 1730 * Without FRACV 1731 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 1732 */ 1733 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 1734 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 1735 RCC_PLLNFRACR_FRACV_SHIFT; 1736 unsigned long long numerator = 0UL; 1737 unsigned long long denominator = 0UL; 1738 1739 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 1740 numerator = prate * numerator; 1741 denominator = ((unsigned long long)divm + 1U) << 13; 1742 fvco = (unsigned long)(numerator / denominator); 1743 } else { 1744 fvco = (unsigned long)(prate * (divn + 1U) / (divm + 1U)); 1745 } 1746 1747 return fvco; 1748 }; 1749 1750 static bool clk_stm32_pll_is_enabled(struct clk *clk) 1751 { 1752 struct clk_stm32_pll_cfg *cfg = clk->priv; 1753 1754 return stm32_gate_is_enabled(cfg->gate_id); 1755 } 1756 1757 static TEE_Result clk_stm32_pll_enable(struct clk *clk) 1758 { 1759 struct clk_stm32_pll_cfg *cfg = clk->priv; 1760 1761 if (clk_stm32_pll_is_enabled(clk)) 1762 return TEE_SUCCESS; 1763 1764 return stm32_gate_rdy_enable(cfg->gate_id); 1765 } 1766 1767 static void clk_stm32_pll_disable(struct clk *clk) 1768 { 1769 struct clk_stm32_pll_cfg *cfg = clk->priv; 1770 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 1771 uintptr_t pll_base = priv->base + cfg->reg_pllxcr; 1772 1773 if (!clk_stm32_pll_is_enabled(clk)) 1774 return; 1775 1776 /* Stop all output */ 1777 io_clrbits32(pll_base, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1778 RCC_PLLNCR_DIVREN); 1779 1780 stm32_gate_rdy_disable(cfg->gate_id); 1781 } 1782 1783 static const struct clk_ops clk_stm32_pll_ops = { 1784 .get_parent = clk_stm32_pll_get_parent, 1785 .get_rate = clk_stm32_pll_get_rate, 1786 .enable = clk_stm32_pll_enable, 1787 .disable = clk_stm32_pll_disable, 1788 }; 1789 1790 static struct 1791 stm32_clk_opp_cfg *clk_stm32_get_opp_config(struct stm32_clk_opp_cfg *opp_cfg, 1792 unsigned long rate) 1793 { 1794 unsigned int i = 0; 1795 1796 for (i = 0; i < MAX_OPP; i++, opp_cfg++) { 1797 if (opp_cfg->frq == 0UL) 1798 break; 1799 1800 if (opp_cfg->frq == rate) 1801 return opp_cfg; 1802 } 1803 1804 return NULL; 1805 } 1806 1807 static TEE_Result clk_stm32_pll1_set_rate(struct clk *clk __maybe_unused, 1808 unsigned long rate, 1809 unsigned long prate __maybe_unused) 1810 { 1811 const struct stm32_clk_pll *pll = clk_stm32_pll_data(PLL1_ID); 1812 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 1813 struct stm32_clk_platdata *pdata = priv->pdata; 1814 struct stm32_pll_dt_cfg *pll_conf = NULL; 1815 struct stm32_clk_opp_cfg *opp = NULL; 1816 int config_on_the_fly = -1; 1817 int err = 0; 1818 size_t sel = stm32_mux_get_parent(MUX_MPU); 1819 1820 opp = clk_stm32_get_opp_config(pdata->opp->mpu_opp, rate); 1821 if (!opp) 1822 return TEE_ERROR_GENERIC; 1823 1824 pll_conf = &opp->pll_cfg; 1825 1826 err = clk_stm32_is_pll_config_on_the_fly(priv, pll, pll_conf, 1827 &config_on_the_fly); 1828 if (err) 1829 return TEE_ERROR_GENERIC; 1830 1831 if (config_on_the_fly == 1) 1832 return TEE_SUCCESS; 1833 1834 if (config_on_the_fly == -1) { 1835 /* Switch to HSI and stop PLL1 before reconfiguration */ 1836 if (stm32_mux_set_parent(MUX_MPU, 0)) 1837 return TEE_ERROR_GENERIC; 1838 1839 stm32_gate_disable(GATE_PLL1_DIVP); 1840 stm32_gate_rdy_disable(GATE_PLL1); 1841 clk_stm32_pll_config_vco(priv, pll, &pll_conf->vco); 1842 } 1843 1844 clk_stm32_pll_config_out(priv, pll, &pll_conf->output); 1845 if (stm32_gate_rdy_enable(GATE_PLL1)) { 1846 EMSG("timeout to enable PLL1 clock"); 1847 panic(); 1848 } 1849 stm32_gate_enable(GATE_PLL1_DIVP); 1850 1851 /* Restore MPU source */ 1852 if (stm32_mux_set_parent(MUX_MPU, sel)) 1853 return TEE_ERROR_GENERIC; 1854 1855 return TEE_SUCCESS; 1856 } 1857 1858 static const struct clk_ops clk_stm32_pll1_ops = { 1859 .set_rate = clk_stm32_pll1_set_rate, 1860 .get_parent = clk_stm32_pll_get_parent, 1861 .get_rate = clk_stm32_pll_get_rate, 1862 .enable = clk_stm32_pll_enable, 1863 .disable = clk_stm32_pll_disable, 1864 }; 1865 1866 static const struct clk_ops clk_stm32_pll1p_ops = { 1867 .get_rate = clk_stm32_composite_get_rate, 1868 .enable = clk_stm32_composite_gate_enable, 1869 .disable = clk_stm32_composite_gate_disable, 1870 }; 1871 1872 static const struct clk_ops clk_stm32_mpu_ops = { 1873 .get_parent = clk_stm32_composite_get_parent, 1874 .set_parent = clk_stm32_composite_set_parent, 1875 }; 1876 1877 static const struct clk_ops clk_stm32_axi_ops = { 1878 .get_parent = clk_stm32_composite_get_parent, 1879 .set_parent = clk_stm32_composite_set_parent, 1880 .set_rate = clk_stm32_composite_set_rate, 1881 .get_rate = clk_stm32_composite_get_rate, 1882 }; 1883 1884 const struct clk_ops clk_stm32_mlahb_ops = { 1885 .get_parent = clk_stm32_composite_get_parent, 1886 .set_parent = clk_stm32_composite_set_parent, 1887 .set_rate = clk_stm32_composite_set_rate, 1888 .get_rate = clk_stm32_composite_get_rate, 1889 }; 1890 1891 #define APB_DIV_MASK GENMASK_32(2, 0) 1892 #define TIM_PRE_MASK BIT(0) 1893 1894 static unsigned long ck_timer_get_rate_ops(struct clk *clk, unsigned long prate) 1895 { 1896 struct clk_stm32_priv *priv = clk_stm32_get_priv(); 1897 struct clk_stm32_timer_cfg *cfg = clk->priv; 1898 uint32_t prescaler, timpre; 1899 uintptr_t rcc_base = priv->base; 1900 1901 prescaler = io_read32(rcc_base + cfg->apbdiv) & APB_DIV_MASK; 1902 1903 timpre = io_read32(rcc_base + cfg->timpre) & TIM_PRE_MASK; 1904 1905 if (prescaler == 0U) 1906 return prate; 1907 1908 return prate * (timpre + 1U) * 2U; 1909 }; 1910 1911 const struct clk_ops ck_timer_ops = { 1912 .get_rate = ck_timer_get_rate_ops, 1913 }; 1914 1915 #define STM32_TIMER(_name, _parent, _flags, _apbdiv, _timpre)\ 1916 struct clk _name = {\ 1917 .ops = &ck_timer_ops,\ 1918 .priv = &(struct clk_stm32_timer_cfg) {\ 1919 .apbdiv = (_apbdiv),\ 1920 .timpre = (_timpre),\ 1921 },\ 1922 .name = #_name,\ 1923 .flags = (_flags),\ 1924 .num_parents = 1,\ 1925 .parents = { _parent },\ 1926 } 1927 1928 #define STM32_KCLK(_name, _nb_parents, _parents, _flags, _gate_id, _mux_id)\ 1929 struct clk _name = {\ 1930 .ops = &clk_stm32_composite_ops,\ 1931 .priv = &(struct clk_stm32_composite_cfg) {\ 1932 .gate_id = (_gate_id),\ 1933 .div_id = (NO_DIV),\ 1934 .mux_id = (_mux_id),\ 1935 },\ 1936 .name = #_name,\ 1937 .flags = (_flags),\ 1938 .num_parents = (_nb_parents),\ 1939 .parents = _parents,\ 1940 } 1941 1942 #define STM32_PLL_VCO(_name, _nb_parents, _parents, _flags, _reg,\ 1943 _gate_id, _mux_id)\ 1944 struct clk _name = {\ 1945 .ops = &clk_stm32_pll_ops,\ 1946 .priv = &(struct clk_stm32_pll_cfg) {\ 1947 .reg_pllxcr = (_reg),\ 1948 .gate_id = (_gate_id),\ 1949 .mux_id = (_mux_id),\ 1950 },\ 1951 .name = #_name,\ 1952 .flags = (_flags),\ 1953 .num_parents = (_nb_parents),\ 1954 .parents = _parents,\ 1955 } 1956 1957 #define STM32_PLL_OUPUT(_name, _nb_parents, _parents, _flags,\ 1958 _gate_id, _div_id, _mux_id)\ 1959 struct clk _name = {\ 1960 .ops = &clk_stm32_composite_ops,\ 1961 .priv = &(struct clk_stm32_composite_cfg) {\ 1962 .gate_id = (_gate_id),\ 1963 .div_id = (_div_id),\ 1964 .mux_id = (_mux_id),\ 1965 },\ 1966 .name = #_name,\ 1967 .flags = (_flags),\ 1968 .num_parents = (_nb_parents),\ 1969 .parents = _parents,\ 1970 } 1971 1972 /* Oscillator clocks */ 1973 static STM32_GATE_READY(ck_hsi, NULL, 0, GATE_HSI); 1974 static STM32_GATE_READY(ck_hse, NULL, 0, GATE_HSE); 1975 static STM32_GATE_READY(ck_csi, NULL, 0, GATE_CSI); 1976 static STM32_GATE_READY(ck_lsi, NULL, 0, GATE_LSI); 1977 static STM32_GATE_READY(ck_lse, NULL, 0, GATE_LSE); 1978 1979 static STM32_FIXED_FACTOR(ck_i2sckin, NULL, 0, 1, 1); 1980 static STM32_FIXED_FACTOR(ck_hse_div2, &ck_hse, 0, 1, 2); 1981 1982 static STM32_FIXED_RATE(ck_off, 0UL); 1983 static STM32_FIXED_RATE(ck_usb_phy_48Mhz, USB_PHY_48_MHZ); 1984 1985 /* PLL1 clocks */ 1986 static struct clk ck_pll1_vco = { 1987 .ops = &clk_stm32_pll1_ops, 1988 .priv = &(struct clk_stm32_pll_cfg) { 1989 .reg_pllxcr = RCC_PLL1CR, 1990 .gate_id = GATE_PLL1, 1991 .mux_id = MUX_PLL12, 1992 }, 1993 .name = "ck_pll1_vco", 1994 .flags = 0, 1995 .num_parents = 2, 1996 .parents = { &ck_hsi, &ck_hse }, 1997 }; 1998 1999 static struct clk ck_pll1p = { 2000 .ops = &clk_stm32_pll1p_ops, 2001 .priv = &(struct clk_stm32_composite_cfg) { 2002 .gate_id = GATE_PLL1_DIVP, 2003 .div_id = DIV_PLL1DIVP, 2004 .mux_id = NO_MUX, 2005 }, 2006 .name = "ck_pll1p", 2007 .flags = 0, 2008 .num_parents = 1, 2009 .parents = { &ck_pll1_vco }, 2010 }; 2011 2012 const struct clk_ops clk_stm32_pll1p_div_ops = { 2013 .get_rate = clk_stm32_divider_get_rate, 2014 }; 2015 2016 static struct clk ck_pll1p_div = { 2017 .ops = &clk_stm32_pll1p_div_ops, 2018 .priv = &(struct clk_stm32_div_cfg) { 2019 .div_id = DIV_MPU, 2020 }, 2021 .name = "ck_pll1p_div", 2022 .flags = 0, 2023 .num_parents = 1, 2024 .parents = { &ck_pll1p }, 2025 }; 2026 2027 /* Other PLLs */ 2028 static STM32_PLL_VCO(ck_pll2_vco, 2, PARENT(&ck_hsi, &ck_hse), 2029 0, RCC_PLL2CR, GATE_PLL2, MUX_PLL12); 2030 2031 static STM32_PLL_VCO(ck_pll3_vco, 3, 2032 PARENT(&ck_hsi, &ck_hse, &ck_csi), 2033 0, RCC_PLL3CR, GATE_PLL3, MUX_PLL3); 2034 2035 static STM32_PLL_VCO(ck_pll4_vco, 4, 2036 PARENT(&ck_hsi, &ck_hse, &ck_csi, &ck_i2sckin), 2037 0, RCC_PLL4CR, GATE_PLL4, MUX_PLL4); 2038 2039 static STM32_PLL_OUPUT(ck_pll2p, 1, PARENT(&ck_pll2_vco), 0, 2040 GATE_PLL2_DIVP, DIV_PLL2DIVP, NO_MUX); 2041 2042 static STM32_PLL_OUPUT(ck_pll2q, 1, PARENT(&ck_pll2_vco), 0, 2043 GATE_PLL2_DIVQ, DIV_PLL2DIVQ, NO_MUX); 2044 2045 static STM32_PLL_OUPUT(ck_pll2r, 1, PARENT(&ck_pll2_vco), 0, 2046 GATE_PLL2_DIVR, DIV_PLL2DIVR, NO_MUX); 2047 2048 static STM32_PLL_OUPUT(ck_pll3p, 1, PARENT(&ck_pll3_vco), 0, 2049 GATE_PLL3_DIVP, DIV_PLL3DIVP, NO_MUX); 2050 2051 static STM32_PLL_OUPUT(ck_pll3q, 1, PARENT(&ck_pll3_vco), 0, 2052 GATE_PLL3_DIVQ, DIV_PLL3DIVQ, NO_MUX); 2053 2054 static STM32_PLL_OUPUT(ck_pll3r, 1, PARENT(&ck_pll3_vco), 0, 2055 GATE_PLL3_DIVR, DIV_PLL3DIVR, NO_MUX); 2056 2057 static STM32_PLL_OUPUT(ck_pll4p, 1, PARENT(&ck_pll4_vco), 0, 2058 GATE_PLL4_DIVP, DIV_PLL4DIVP, NO_MUX); 2059 2060 static STM32_PLL_OUPUT(ck_pll4q, 1, PARENT(&ck_pll4_vco), 0, 2061 GATE_PLL4_DIVQ, DIV_PLL4DIVQ, NO_MUX); 2062 2063 static STM32_PLL_OUPUT(ck_pll4r, 1, PARENT(&ck_pll4_vco), 0, 2064 GATE_PLL4_DIVR, DIV_PLL4DIVR, NO_MUX); 2065 2066 /* System clocks */ 2067 static struct clk ck_mpu = { 2068 .ops = &clk_stm32_mpu_ops, 2069 .priv = &(struct clk_stm32_composite_cfg) { 2070 .mux_id = MUX_MPU, 2071 }, 2072 .name = "ck_mpu", 2073 .flags = 0, 2074 .num_parents = 4, 2075 .parents = { &ck_hsi, &ck_hse, &ck_pll1p, &ck_pll1p_div }, 2076 }; 2077 2078 static struct clk ck_axi = { 2079 .ops = &clk_stm32_axi_ops, 2080 .priv = &(struct clk_stm32_composite_cfg) { 2081 .mux_id = MUX_AXI, 2082 .div_id = DIV_AXI, 2083 }, 2084 .name = "ck_axi", 2085 .flags = 0, 2086 .num_parents = 3, 2087 .parents = { &ck_hsi, &ck_hse, &ck_pll2p }, 2088 }; 2089 2090 static struct clk ck_mlahb = { 2091 .ops = &clk_stm32_mlahb_ops, 2092 .priv = &(struct clk_stm32_composite_cfg) { 2093 .mux_id = MUX_MLAHB, 2094 .div_id = DIV_MLAHB, 2095 }, 2096 .name = "ck_mlahb", 2097 .flags = 0, 2098 .num_parents = 4, 2099 .parents = { &ck_hsi, &ck_hse, &ck_csi, &ck_pll3p }, 2100 }; 2101 2102 static STM32_MUX(ck_per, 4, PARENT(&ck_hsi, &ck_csi, &ck_hse, &ck_off), 2103 0, MUX_CKPER); 2104 2105 /* Bus clocks */ 2106 static STM32_DIVIDER(ck_pclk1, &ck_mlahb, 0, DIV_APB1); 2107 static STM32_DIVIDER(ck_pclk2, &ck_mlahb, 0, DIV_APB2); 2108 static STM32_DIVIDER(ck_pclk3, &ck_mlahb, 0, DIV_APB3); 2109 static STM32_DIVIDER(ck_pclk4, &ck_axi, 0, DIV_APB4); 2110 static STM32_DIVIDER(ck_pclk5, &ck_axi, 0, DIV_APB5); 2111 static STM32_DIVIDER(ck_pclk6, &ck_mlahb, 0, DIV_APB6); 2112 2113 /* Timer Clocks */ 2114 static STM32_TIMER(ck_timg1, &ck_pclk1, 0, RCC_APB1DIVR, RCC_TIMG1PRER); 2115 static STM32_TIMER(ck_timg2, &ck_pclk2, 0, RCC_APB2DIVR, RCC_TIMG2PRER); 2116 static STM32_TIMER(ck_timg3, &ck_pclk6, 0, RCC_APB6DIVR, RCC_TIMG3PRER); 2117 2118 /* Peripheral and Kernel Clocks */ 2119 static STM32_GATE(ck_ddrc1, &ck_axi, 0, GATE_DDRC1); 2120 static STM32_GATE(ck_ddrc1lp, &ck_axi, 0, GATE_DDRC1LP); 2121 static STM32_GATE(ck_ddrphyc, &ck_pll2r, 0, GATE_DDRPHYC); 2122 static STM32_GATE(ck_ddrphyclp, &ck_pll2r, 0, GATE_DDRPHYCLP); 2123 static STM32_GATE(ck_ddrcapb, &ck_pclk4, 0, GATE_DDRCAPB); 2124 static STM32_GATE(ck_ddrcapblp, &ck_pclk4, 0, GATE_DDRCAPBLP); 2125 static STM32_GATE(ck_axidcg, &ck_axi, 0, GATE_AXIDCG); 2126 static STM32_GATE(ck_ddrphycapb, &ck_pclk4, 0, 0); 2127 static STM32_GATE(ck_ddrphycapblp, &ck_pclk4, 0, GATE_DDRPHYCAPBLP); 2128 static STM32_GATE(ck_syscfg, &ck_pclk3, 0, GATE_SYSCFG); 2129 static STM32_GATE(ck_ddrperfm, &ck_pclk4, 0, GATE_DDRPERFM); 2130 static STM32_GATE(ck_iwdg2, &ck_pclk4, 0, GATE_IWDG2APB); 2131 static STM32_GATE(ck_rtcapb, &ck_pclk5, 0, GATE_RTCAPB); 2132 static STM32_GATE(ck_tzc, &ck_pclk5, 0, GATE_TZC); 2133 static STM32_GATE(ck_etzpcb, &ck_pclk5, 0, GATE_ETZPC); 2134 static STM32_GATE(ck_iwdg1apb, &ck_pclk5, 0, GATE_IWDG1APB); 2135 static STM32_GATE(ck_bsec, &ck_pclk5, 0, GATE_BSEC); 2136 static STM32_GATE(ck_tim12_k, &ck_timg3, 0, GATE_TIM12); 2137 static STM32_GATE(ck_tim15_k, &ck_timg3, 0, GATE_TIM15); 2138 static STM32_GATE(ck_gpioa, &ck_mlahb, 0, GATE_GPIOA); 2139 static STM32_GATE(ck_gpiob, &ck_mlahb, 0, GATE_GPIOB); 2140 static STM32_GATE(ck_gpioc, &ck_mlahb, 0, GATE_GPIOC); 2141 static STM32_GATE(ck_gpiod, &ck_mlahb, 0, GATE_GPIOD); 2142 static STM32_GATE(ck_gpioe, &ck_mlahb, 0, GATE_GPIOE); 2143 static STM32_GATE(ck_gpiof, &ck_mlahb, 0, GATE_GPIOF); 2144 static STM32_GATE(ck_gpiog, &ck_mlahb, 0, GATE_GPIOG); 2145 static STM32_GATE(ck_gpioh, &ck_mlahb, 0, GATE_GPIOH); 2146 static STM32_GATE(ck_gpioi, &ck_mlahb, 0, GATE_GPIOI); 2147 static STM32_GATE(ck_pka, &ck_axi, 0, GATE_PKA); 2148 static STM32_GATE(ck_cryp1, &ck_pclk5, 0, GATE_CRYP1); 2149 static STM32_GATE(ck_hash1, &ck_pclk5, 0, GATE_HASH1); 2150 static STM32_GATE(ck_bkpsram, &ck_pclk5, 0, GATE_BKPSRAM); 2151 static STM32_GATE(ck_dbg, &ck_axi, 0, GATE_DBGCK); 2152 static STM32_GATE(ck_mce, &ck_axi, 0, GATE_MCE); 2153 static STM32_GATE(ck_tim2_k, &ck_timg1, 0, GATE_TIM2); 2154 static STM32_GATE(ck_tim3_k, &ck_timg1, 0, GATE_TIM3); 2155 static STM32_GATE(ck_tim4_k, &ck_timg1, 0, GATE_TIM4); 2156 static STM32_GATE(ck_tim5_k, &ck_timg1, 0, GATE_TIM5); 2157 static STM32_GATE(ck_tim6_k, &ck_timg1, 0, GATE_TIM6); 2158 static STM32_GATE(ck_tim7_k, &ck_timg1, 0, GATE_TIM7); 2159 static STM32_GATE(ck_tim13_k, &ck_timg3, 0, GATE_TIM13); 2160 static STM32_GATE(ck_tim14_k, &ck_timg3, 0, GATE_TIM14); 2161 static STM32_GATE(ck_tim1_k, &ck_timg2, 0, GATE_TIM1); 2162 static STM32_GATE(ck_tim8_k, &ck_timg2, 0, GATE_TIM8); 2163 static STM32_GATE(ck_tim16_k, &ck_timg3, 0, GATE_TIM16); 2164 static STM32_GATE(ck_tim17_k, &ck_timg3, 0, GATE_TIM17); 2165 static STM32_GATE(ck_ltdc_px, &ck_pll4q, 0, GATE_LTDC); 2166 static STM32_GATE(ck_dma1, &ck_mlahb, 0, GATE_DMA1); 2167 static STM32_GATE(ck_dma2, &ck_mlahb, 0, GATE_DMA2); 2168 static STM32_GATE(ck_mdma, &ck_axi, 0, GATE_MDMA); 2169 static STM32_GATE(ck_eth1mac, &ck_axi, 0, GATE_ETH1MAC); 2170 static STM32_GATE(ck_usbh, &ck_axi, 0, GATE_USBH); 2171 static STM32_GATE(ck_vref, &ck_pclk3, 0, GATE_VREF); 2172 static STM32_GATE(ck_tmpsens, &ck_pclk3, 0, GATE_DTS); 2173 static STM32_GATE(ck_pmbctrl, &ck_pclk3, 0, GATE_HDP); 2174 static STM32_GATE(ck_hdp, &ck_pclk3, 0, GATE_PMBCTRL); 2175 static STM32_GATE(ck_stgenro, &ck_pclk4, 0, GATE_DCMIPP); 2176 static STM32_GATE(ck_dmamux1, &ck_axi, 0, GATE_DMAMUX1); 2177 static STM32_GATE(ck_dmamux2, &ck_axi, 0, GATE_DMAMUX2); 2178 static STM32_GATE(ck_dma3, &ck_axi, 0, GATE_DMAMUX2); 2179 static STM32_GATE(ck_tsc, &ck_axi, 0, GATE_TSC); 2180 static STM32_GATE(ck_aximc, &ck_axi, 0, GATE_AXIMC); 2181 static STM32_GATE(ck_crc1, &ck_axi, 0, GATE_ETH1TX); 2182 static STM32_GATE(ck_eth1tx, &ck_axi, 0, GATE_ETH1TX); 2183 static STM32_GATE(ck_eth1rx, &ck_axi, 0, GATE_ETH1RX); 2184 static STM32_GATE(ck_eth2tx, &ck_axi, 0, GATE_ETH2TX); 2185 static STM32_GATE(ck_eth2rx, &ck_axi, 0, GATE_ETH2RX); 2186 static STM32_GATE(ck_eth2mac, &ck_axi, 0, GATE_ETH2MAC); 2187 2188 /* Kernel Clocks */ 2189 static STM32_KCLK(ck_usbphy_k, 3, 2190 PARENT(&ck_hse, &ck_pll4r, &ck_hse_div2), 2191 0, GATE_USBPHY, MUX_USBPHY); 2192 2193 static STM32_KCLK(ck_usbo_k, 2, 2194 PARENT(&ck_pll4r, &ck_usb_phy_48Mhz), 0, 2195 GATE_USBO, MUX_USBO); 2196 2197 static STM32_KCLK(ck_stgen_k, 2, 2198 PARENT(&ck_hsi, &ck_hse), 0, GATE_STGENC, MUX_STGEN); 2199 2200 static STM32_KCLK(ck_usart1_k, 6, 2201 PARENT(&ck_pclk6, &ck_pll3q, &ck_hsi, 2202 &ck_csi, &ck_pll4q, &ck_hse), 2203 0, GATE_USART1, MUX_UART1); 2204 2205 static STM32_KCLK(ck_usart2_k, 6, 2206 PARENT(&ck_pclk6, &ck_pll3q, &ck_hsi, &ck_csi, &ck_pll4q, 2207 &ck_hse), 2208 0, GATE_USART2, MUX_UART2); 2209 2210 static STM32_KCLK(ck_i2c4_k, 4, 2211 PARENT(&ck_pclk6, &ck_pll4r, &ck_hsi, &ck_csi), 2212 0, GATE_I2C4, MUX_I2C4); 2213 2214 static STM32_KCLK(ck_rtc, 4, 2215 PARENT(&ck_off, &ck_lse, &ck_lsi, &ck_hse), 2216 0, GATE_RTCCK, MUX_RTC); 2217 2218 static STM32_KCLK(ck_saes_k, 4, 2219 PARENT(&ck_axi, &ck_per, &ck_pll4r, &ck_lsi), 2220 0, GATE_SAES, MUX_SAES); 2221 2222 static STM32_KCLK(ck_rng1_k, 4, 2223 PARENT(&ck_csi, &ck_pll4r, &ck_lse, &ck_lsi), 2224 0, GATE_RNG1, MUX_RNG1); 2225 2226 static STM32_KCLK(ck_sdmmc1_k, 4, 2227 PARENT(&ck_axi, &ck_pll3r, &ck_pll4p, &ck_hsi), 2228 0, GATE_SDMMC1, MUX_SDMMC1); 2229 2230 static STM32_KCLK(ck_sdmmc2_k, 4, 2231 PARENT(&ck_axi, &ck_pll3r, &ck_pll4p, &ck_hsi), 2232 0, GATE_SDMMC2, MUX_SDMMC2); 2233 2234 static STM32_KCLK(ck_usart3_k, 5, 2235 PARENT(&ck_pclk1, &ck_pll4q, &ck_hsi, &ck_csi, &ck_hse), 2236 0, GATE_USART3, MUX_UART35); 2237 2238 static STM32_KCLK(ck_uart4_k, 5, 2239 PARENT(&ck_pclk1, &ck_pll4q, &ck_hsi, &ck_csi, &ck_hse), 2240 0, GATE_UART4, MUX_UART4); 2241 2242 static STM32_KCLK(ck_uart5_k, 5, 2243 PARENT(&ck_pclk1, &ck_pll4q, &ck_hsi, &ck_csi, &ck_hse), 2244 0, GATE_UART5, MUX_UART35); 2245 2246 static STM32_KCLK(ck_uart7_k, 5, 2247 PARENT(&ck_pclk1, &ck_pll4q, &ck_hsi, &ck_csi, &ck_hse), 2248 0, GATE_UART7, MUX_UART78); 2249 2250 static STM32_KCLK(ck_uart8_k, 5, 2251 PARENT(&ck_pclk1, &ck_pll4q, &ck_hsi, &ck_csi, &ck_hse), 2252 0, GATE_UART8, MUX_UART78); 2253 2254 static STM32_KCLK(ck_usart6_k, 5, 2255 PARENT(&ck_pclk2, &ck_pll4q, &ck_hsi, &ck_csi, &ck_hse), 2256 0, GATE_USART6, MUX_UART6); 2257 2258 static STM32_KCLK(ck_fmc_k, 4, 2259 PARENT(&ck_axi, &ck_pll3r, &ck_pll4p, &ck_per), 2260 0, GATE_FMC, MUX_FMC); 2261 2262 static STM32_KCLK(ck_qspi_k, 4, 2263 PARENT(&ck_axi, &ck_pll3r, &ck_pll4p, &ck_per), 2264 0, GATE_QSPI, MUX_QSPI); 2265 2266 static STM32_KCLK(ck_lptim1_k, 6, 2267 PARENT(&ck_pclk1, &ck_pll4p, &ck_pll3q, &ck_lse, &ck_lsi, 2268 &ck_per), 2269 0, GATE_LPTIM1, MUX_LPTIM1); 2270 2271 static STM32_KCLK(ck_spi2_k, 5, 2272 PARENT(&ck_pll4p, &ck_pll3q, &ck_i2sckin, &ck_per, &ck_pll3r), 2273 0, GATE_SPI2, MUX_SPI23); 2274 2275 static STM32_KCLK(ck_spi3_k, 5, 2276 PARENT(&ck_pll4p, &ck_pll3q, &ck_i2sckin, &ck_per, &ck_pll3r), 2277 0, GATE_SPI3, MUX_SPI23); 2278 2279 static STM32_KCLK(ck_spdif_k, 3, 2280 PARENT(&ck_pll4p, &ck_pll3q, &ck_hsi), 2281 0, GATE_SPDIF, MUX_SPDIF); 2282 2283 static STM32_KCLK(ck_spi1_k, 5, 2284 PARENT(&ck_pll4p, &ck_pll3q, &ck_i2sckin, &ck_per, &ck_pll3r), 2285 0, GATE_SPI1, MUX_SPI1); 2286 2287 static STM32_KCLK(ck_spi4_k, 6, 2288 PARENT(&ck_pclk6, &ck_pll4q, &ck_hsi, &ck_csi, &ck_hse, 2289 &ck_i2sckin), 2290 0, GATE_SPI4, MUX_SPI4); 2291 2292 static STM32_KCLK(ck_spi5_k, 5, 2293 PARENT(&ck_pclk6, &ck_pll4q, &ck_hsi, &ck_csi, &ck_hse), 2294 0, GATE_SPI5, MUX_SPI5); 2295 2296 static STM32_KCLK(ck_sai1_k, 5, 2297 PARENT(&ck_pll4q, &ck_pll3q, &ck_i2sckin, &ck_per, &ck_pll3r), 2298 0, GATE_SAI1, MUX_SAI1); 2299 2300 static STM32_KCLK(ck_sai2_k, 6, 2301 PARENT(&ck_pll4q, &ck_pll3q, &ck_i2sckin, &ck_per, &ck_off, 2302 &ck_pll3r), 2303 0, GATE_SAI2, MUX_SAI2); 2304 2305 static STM32_KCLK(ck_dfsdm_k, 5, 2306 PARENT(&ck_pll4q, &ck_pll3q, &ck_i2sckin, &ck_per, &ck_pll3r), 2307 0, GATE_DFSDM, MUX_SAI1); 2308 2309 static STM32_KCLK(ck_fdcan_k, 4, 2310 PARENT(&ck_hse, &ck_pll3q, &ck_pll4q, &ck_pll4r), 2311 0, GATE_FDCAN, MUX_FDCAN); 2312 2313 static STM32_KCLK(ck_i2c1_k, 4, 2314 PARENT(&ck_pclk1, &ck_pll4r, &ck_hsi, &ck_csi), 2315 0, GATE_I2C1, MUX_I2C12); 2316 2317 static STM32_KCLK(ck_i2c2_k, 4, 2318 PARENT(&ck_pclk1, &ck_pll4r, &ck_hsi, &ck_csi), 2319 0, GATE_I2C2, MUX_I2C12); 2320 2321 static STM32_KCLK(ck_adfsdm_k, 5, 2322 PARENT(&ck_pll4q, &ck_pll3q, &ck_i2sckin, &ck_per, &ck_pll3r), 2323 0, GATE_ADFSDM, MUX_SAI1); 2324 2325 static STM32_KCLK(ck_lptim2_k, 5, 2326 PARENT(&ck_pclk3, &ck_pll4q, &ck_per, &ck_lse, &ck_lsi), 2327 0, GATE_LPTIM2, MUX_LPTIM2); 2328 2329 static STM32_KCLK(ck_lptim3_k, 5, 2330 PARENT(&ck_pclk3, &ck_pll4q, &ck_per, &ck_lse, &ck_lsi), 2331 0, GATE_LPTIM3, MUX_LPTIM3); 2332 2333 static STM32_KCLK(ck_lptim4_k, 6, 2334 PARENT(&ck_pclk3, &ck_pll4p, &ck_pll3q, &ck_lse, &ck_lsi, 2335 &ck_per), 2336 0, GATE_LPTIM4, MUX_LPTIM45); 2337 2338 static STM32_KCLK(ck_lptim5_k, 6, 2339 PARENT(&ck_pclk3, &ck_pll4p, &ck_pll3q, &ck_lse, &ck_lsi, 2340 &ck_per), 2341 0, GATE_LPTIM5, MUX_LPTIM45); 2342 2343 static STM32_KCLK(ck_i2c3_k, 4, 2344 PARENT(&ck_pclk6, &ck_pll4r, &ck_hsi, &ck_csi), 2345 0, GATE_I2C3, MUX_I2C3); 2346 2347 static STM32_KCLK(ck_i2c5_k, 4, 2348 PARENT(&ck_pclk6, &ck_pll4r, &ck_hsi, &ck_csi), 2349 0, GATE_I2C5, MUX_I2C5); 2350 2351 static STM32_KCLK(ck_dcmipp_k, 4, 2352 PARENT(&ck_axi, &ck_pll2q, &ck_pll4p, &ck_per), 2353 0, GATE_DCMIPP, MUX_DCMIPP); 2354 2355 static STM32_KCLK(ck_adc1_k, 3, PARENT(&ck_pll4r, &ck_per, &ck_pll3q), 2356 0, GATE_ADC1, MUX_ADC1); 2357 2358 static STM32_KCLK(ck_adc2_k, 3, PARENT(&ck_pll4r, &ck_per, &ck_pll3q), 2359 0, GATE_ADC2, MUX_ADC2); 2360 2361 static STM32_KCLK(ck_eth1ck_k, 2, PARENT(&ck_pll4p, &ck_pll3q), 2362 0, GATE_ETH1CK, MUX_ETH1); 2363 2364 static STM32_KCLK(ck_eth2ck_k, 2, PARENT(&ck_pll4p, &ck_pll3q), 2365 0, GATE_ETH2CK, MUX_ETH2); 2366 2367 static STM32_COMPOSITE(ck_mco1, 5, 2368 PARENT(&ck_hsi, &ck_hse, &ck_csi, &ck_lsi, &ck_lse), 2369 0, GATE_MCO1, DIV_MCO1, MUX_MCO1); 2370 2371 static STM32_COMPOSITE(ck_mco2, 6, 2372 PARENT(&ck_mpu, &ck_axi, &ck_mlahb, 2373 &ck_pll4p, &ck_hse, &ck_hsi), 2374 0, GATE_MCO2, DIV_MCO2, MUX_MCO2); 2375 2376 static STM32_COMPOSITE(ck_trace, 1, PARENT(&ck_axi), 2377 0, GATE_TRACECK, DIV_TRACE, NO_MUX); 2378 2379 enum { 2380 USB_PHY_48 = STM32MP1_LAST_CLK, 2381 PLL1P_DIV, 2382 CK_OFF, 2383 I2S_CKIN, 2384 STM32MP13_ALL_CLK_NB 2385 }; 2386 2387 static struct clk *stm32mp13_clk_provided[STM32MP13_ALL_CLK_NB] = { 2388 [CK_HSE] = &ck_hse, 2389 [CK_CSI] = &ck_csi, 2390 [CK_LSI] = &ck_lsi, 2391 [CK_LSE] = &ck_lse, 2392 [CK_HSI] = &ck_hsi, 2393 [CK_HSE_DIV2] = &ck_hse_div2, 2394 [PLL1] = &ck_pll1_vco, 2395 [PLL2] = &ck_pll2_vco, 2396 [PLL3] = &ck_pll3_vco, 2397 [PLL4] = &ck_pll4_vco, 2398 [PLL1_P] = &ck_pll1p, 2399 [PLL2_P] = &ck_pll2p, 2400 [PLL2_Q] = &ck_pll2q, 2401 [PLL2_R] = &ck_pll2r, 2402 [PLL3_P] = &ck_pll3p, 2403 [PLL3_Q] = &ck_pll3q, 2404 [PLL3_R] = &ck_pll3r, 2405 [PLL4_P] = &ck_pll4p, 2406 [PLL4_Q] = &ck_pll4q, 2407 [PLL4_R] = &ck_pll4r, 2408 [PLL1P_DIV] = &ck_pll1p_div, 2409 [CK_MPU] = &ck_mpu, 2410 [CK_AXI] = &ck_axi, 2411 [CK_MLAHB] = &ck_mlahb, 2412 [CK_PER] = &ck_per, 2413 [PCLK1] = &ck_pclk1, 2414 [PCLK2] = &ck_pclk2, 2415 [PCLK3] = &ck_pclk3, 2416 [PCLK4] = &ck_pclk4, 2417 [PCLK5] = &ck_pclk5, 2418 [PCLK6] = &ck_pclk6, 2419 [CK_TIMG1] = &ck_timg1, 2420 [CK_TIMG2] = &ck_timg2, 2421 [CK_TIMG3] = &ck_timg3, 2422 [DDRC1] = &ck_ddrc1, 2423 [DDRC1LP] = &ck_ddrc1lp, 2424 [DDRPHYC] = &ck_ddrphyc, 2425 [DDRPHYCLP] = &ck_ddrphyclp, 2426 [DDRCAPB] = &ck_ddrcapb, 2427 [DDRCAPBLP] = &ck_ddrcapblp, 2428 [AXIDCG] = &ck_axidcg, 2429 [DDRPHYCAPB] = &ck_ddrphycapb, 2430 [DDRPHYCAPBLP] = &ck_ddrphycapblp, 2431 [SYSCFG] = &ck_syscfg, 2432 [DDRPERFM] = &ck_ddrperfm, 2433 [IWDG2] = &ck_iwdg2, 2434 [USBPHY_K] = &ck_usbphy_k, 2435 [USBO_K] = &ck_usbo_k, 2436 [RTCAPB] = &ck_rtcapb, 2437 [TZC] = &ck_tzc, 2438 [TZPC] = &ck_etzpcb, 2439 [IWDG1] = &ck_iwdg1apb, 2440 [BSEC] = &ck_bsec, 2441 [STGEN_K] = &ck_stgen_k, 2442 [USART1_K] = &ck_usart1_k, 2443 [USART2_K] = &ck_usart2_k, 2444 [I2C4_K] = &ck_i2c4_k, 2445 [TIM12_K] = &ck_tim12_k, 2446 [TIM15_K] = &ck_tim15_k, 2447 [RTC] = &ck_rtc, 2448 [GPIOA] = &ck_gpioa, 2449 [GPIOB] = &ck_gpiob, 2450 [GPIOC] = &ck_gpioc, 2451 [GPIOD] = &ck_gpiod, 2452 [GPIOE] = &ck_gpioe, 2453 [GPIOF] = &ck_gpiof, 2454 [GPIOG] = &ck_gpiog, 2455 [GPIOH] = &ck_gpioh, 2456 [GPIOI] = &ck_gpioi, 2457 [PKA] = &ck_pka, 2458 [SAES_K] = &ck_saes_k, 2459 [CRYP1] = &ck_cryp1, 2460 [HASH1] = &ck_hash1, 2461 [RNG1_K] = &ck_rng1_k, 2462 [BKPSRAM] = &ck_bkpsram, 2463 [SDMMC1_K] = &ck_sdmmc1_k, 2464 [SDMMC2_K] = &ck_sdmmc2_k, 2465 [CK_DBG] = &ck_dbg, 2466 [MCE] = &ck_mce, 2467 [TIM2_K] = &ck_tim2_k, 2468 [TIM3_K] = &ck_tim3_k, 2469 [TIM4_K] = &ck_tim4_k, 2470 [TIM5_K] = &ck_tim5_k, 2471 [TIM6_K] = &ck_tim6_k, 2472 [TIM7_K] = &ck_tim7_k, 2473 [TIM13_K] = &ck_tim13_k, 2474 [TIM14_K] = &ck_tim14_k, 2475 [TIM1_K] = &ck_tim1_k, 2476 [TIM8_K] = &ck_tim8_k, 2477 [TIM16_K] = &ck_tim16_k, 2478 [TIM17_K] = &ck_tim17_k, 2479 [LTDC_PX] = &ck_ltdc_px, 2480 [DMA1] = &ck_dma1, 2481 [DMA2] = &ck_dma2, 2482 [MDMA] = &ck_mdma, 2483 [ETH1MAC] = &ck_eth1mac, 2484 [USBH] = &ck_usbh, 2485 [VREF] = &ck_vref, 2486 [TMPSENS] = &ck_tmpsens, 2487 [PMBCTRL] = &ck_pmbctrl, 2488 [HDP] = &ck_hdp, 2489 [STGENRO] = &ck_stgenro, 2490 [DMAMUX1] = &ck_dmamux1, 2491 [DMAMUX2] = &ck_dmamux2, 2492 [DMA3] = &ck_dma3, 2493 [TSC] = &ck_tsc, 2494 [AXIMC] = &ck_aximc, 2495 [CRC1] = &ck_crc1, 2496 [ETH1TX] = &ck_eth1tx, 2497 [ETH1RX] = &ck_eth1rx, 2498 [ETH2TX] = &ck_eth2tx, 2499 [ETH2RX] = &ck_eth2rx, 2500 [ETH2MAC] = &ck_eth2mac, 2501 [USART3_K] = &ck_usart3_k, 2502 [UART4_K] = &ck_uart4_k, 2503 [UART5_K] = &ck_uart5_k, 2504 [UART7_K] = &ck_uart7_k, 2505 [UART8_K] = &ck_uart8_k, 2506 [USART6_K] = &ck_usart6_k, 2507 [FMC_K] = &ck_fmc_k, 2508 [QSPI_K] = &ck_qspi_k, 2509 [LPTIM1_K] = &ck_lptim1_k, 2510 [SPI2_K] = &ck_spi2_k, 2511 [SPI3_K] = &ck_spi3_k, 2512 [SPDIF_K] = &ck_spdif_k, 2513 [SPI1_K] = &ck_spi1_k, 2514 [SPI4_K] = &ck_spi4_k, 2515 [SPI5_K] = &ck_spi5_k, 2516 [SAI1_K] = &ck_sai1_k, 2517 [SAI2_K] = &ck_sai2_k, 2518 [DFSDM_K] = &ck_dfsdm_k, 2519 [FDCAN_K] = &ck_fdcan_k, 2520 [I2C1_K] = &ck_i2c1_k, 2521 [I2C2_K] = &ck_i2c2_k, 2522 [ADFSDM_K] = &ck_adfsdm_k, 2523 [LPTIM2_K] = &ck_lptim2_k, 2524 [LPTIM3_K] = &ck_lptim3_k, 2525 [LPTIM4_K] = &ck_lptim4_k, 2526 [LPTIM5_K] = &ck_lptim5_k, 2527 [I2C3_K] = &ck_i2c3_k, 2528 [I2C5_K] = &ck_i2c5_k, 2529 [DCMIPP_K] = &ck_dcmipp_k, 2530 [ADC1_K] = &ck_adc1_k, 2531 [ADC2_K] = &ck_adc2_k, 2532 [ETH1CK_K] = &ck_eth1ck_k, 2533 [ETH2CK_K] = &ck_eth2ck_k, 2534 [CK_MCO1] = &ck_mco1, 2535 [CK_MCO2] = &ck_mco2, 2536 [CK_TRACE] = &ck_trace, 2537 [CK_OFF] = &ck_off, 2538 [USB_PHY_48] = &ck_usb_phy_48Mhz, 2539 [I2S_CKIN] = &ck_i2sckin, 2540 }; 2541 2542 static bool clk_stm32_clock_is_critical(struct clk *clk __maybe_unused) 2543 { 2544 struct clk *clk_criticals[] = { 2545 &ck_hsi, 2546 &ck_hse, 2547 &ck_csi, 2548 &ck_lsi, 2549 &ck_lse, 2550 &ck_pll2r, 2551 &ck_mpu, 2552 &ck_ddrc1, 2553 &ck_ddrc1lp, 2554 &ck_ddrphyc, 2555 &ck_ddrphyclp, 2556 &ck_ddrcapb, 2557 &ck_ddrcapblp, 2558 &ck_axidcg, 2559 &ck_ddrphycapb, 2560 &ck_ddrphycapblp, 2561 &ck_rtcapb, 2562 &ck_tzc, 2563 &ck_etzpcb, 2564 &ck_iwdg1apb, 2565 &ck_bsec, 2566 &ck_stgen_k, 2567 &ck_bkpsram, 2568 &ck_mce, 2569 &ck_mco1, 2570 &ck_rng1_k, 2571 &ck_mlahb, 2572 }; 2573 size_t i = 0; 2574 2575 for (i = 0; i < ARRAY_SIZE(clk_criticals); i++) { 2576 struct clk *clk_critical = clk_criticals[i]; 2577 2578 if (clk == clk_critical) 2579 return true; 2580 } 2581 2582 return false; 2583 } 2584 2585 static void clk_stm32_init_oscillators(const void *fdt, int node) 2586 { 2587 size_t i = 0; 2588 const char *name[6] = { "clk-hse", "clk-hsi", "clk-lse", 2589 "clk-lsi", "clk-csi", "clk-i2sin" }; 2590 struct clk *clks[6] = { &ck_hse, &ck_hsi, &ck_lse, 2591 &ck_lsi, &ck_csi, &ck_i2sckin }; 2592 2593 for (i = 0; i < ARRAY_SIZE(clks); i++) { 2594 struct clk *clk = NULL; 2595 2596 clk_dt_get_by_name(fdt, node, name[i], &clk); 2597 2598 clks[i]->parents[0] = clk; 2599 } 2600 } 2601 2602 static struct stm32_pll_dt_cfg mp13_pll[PLL_NB]; 2603 static struct stm32_clk_opp_dt_cfg mp13_clk_opp; 2604 static struct stm32_osci_dt_cfg mp13_osci[NB_OSCILLATOR]; 2605 static uint32_t mp13_clksrc[MUX_NB]; 2606 static uint32_t mp13_clkdiv[DIV_NB]; 2607 2608 static struct stm32_clk_platdata stm32mp13_clock_pdata = { 2609 .osci = mp13_osci, 2610 .nosci = NB_OSCILLATOR, 2611 .pll = mp13_pll, 2612 .opp = &mp13_clk_opp, 2613 .npll = PLL_NB, 2614 .clksrc = mp13_clksrc, 2615 .nclksrc = MUX_NB, 2616 .clkdiv = mp13_clkdiv, 2617 .nclkdiv = DIV_NB, 2618 }; 2619 2620 static struct clk_stm32_priv stm32mp13_clock_data = { 2621 .muxes = parent_mp13, 2622 .nb_muxes = ARRAY_SIZE(parent_mp13), 2623 .gates = gates_mp13, 2624 .nb_gates = ARRAY_SIZE(gates_mp13), 2625 .div = dividers_mp13, 2626 .nb_div = ARRAY_SIZE(dividers_mp13), 2627 .pdata = &stm32mp13_clock_pdata, 2628 .nb_clk_refs = STM32MP13_ALL_CLK_NB, 2629 .clk_refs = stm32mp13_clk_provided, 2630 .is_critical = clk_stm32_clock_is_critical, 2631 }; 2632 2633 static TEE_Result stm32mp13_clk_probe(const void *fdt, int node, 2634 const void *compat_data __unused) 2635 { 2636 TEE_Result res = TEE_ERROR_GENERIC; 2637 int fdt_rc = 0; 2638 int rc = 0; 2639 struct clk_stm32_priv *priv = &stm32mp13_clock_data; 2640 struct stm32_clk_platdata *pdata = &stm32mp13_clock_pdata; 2641 2642 fdt_rc = stm32_clk_parse_fdt(fdt, node, pdata); 2643 if (fdt_rc) { 2644 EMSG("Failed to parse clock node: %d", fdt_rc); 2645 return TEE_ERROR_GENERIC; 2646 } 2647 2648 res = clk_stm32_init(priv, stm32_rcc_base()); 2649 if (res) 2650 return res; 2651 2652 rc = stm32mp1_init_clock_tree(priv, pdata); 2653 if (rc) 2654 return TEE_ERROR_GENERIC; 2655 2656 clk_stm32_init_oscillators(fdt, node); 2657 2658 stm32mp_clk_provider_probe_final(fdt, node, priv); 2659 2660 return TEE_SUCCESS; 2661 } 2662 2663 CLK_DT_DECLARE(stm32mp13_clk, "st,stm32mp13-rcc", stm32mp13_clk_probe); 2664