1/* 2 * Copyright (c) 2014, STMicroelectronics International N.V. 3 * All rights reserved. 4 * Copyright (c) 2016, Wind River Systems. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30/* 31 * Entry points for the A9 inits, A9 revision specific or not. 32 * It is assume no stack is available when these routines are called. 33 * It is assume each routine is called with return address in LR 34 * and with ARM registers R0, R1, R2, R3 being scratchable. 35 */ 36 37#include <arm32.h> 38#include <arm32_macros.S> 39#include <arm32_macros_cortex_a9.S> 40#include <asm.S> 41#include <kernel/tz_ssvce_def.h> 42#include <kernel/unwind.h> 43#include <platform_config.h> 44 45#define ZYNQ_SLCR_L2C_RAM 0xF8000A1C 46 47.section .text 48.balign 4 49.code 32 50 51/* 52 * Cortex A9 early configuration 53 * 54 * Use registers R0-R3. 55 * No stack usage. 56 * LR store return address. 57 * Trap CPU in case of error. 58 */ 59FUNC plat_cpu_reset_early , : 60UNWIND( .fnstart) 61 62 /* 63 * Disallow NSec to mask FIQ [bit4: FW=0] 64 * Allow NSec to manage Imprecise Abort [bit5: AW=1] 65 * Imprecise Abort trapped to Abort Mode [bit3: EA=0] 66 * In Sec world, FIQ trapped to FIQ Mode [bit2: FIQ=0] 67 * IRQ always trapped to IRQ Mode [bit1: IRQ=0] 68 * Secure World [bit0: NS=0] 69 */ 70 mov r0, #SCR_AW 71 write_scr r0 /* write Secure Configuration Register */ 72 73 /* 74 * Mandated HW config loaded 75 * 76 * SCTLR = 0x00004000 77 * - Round-Robin replac. for icache, btac, i/duTLB (bit14: RoundRobin) 78 * 79 * ACTRL = 0x00000041 80 * - core always in full SMP (FW bit0=1, SMP bit6=1) 81 * - L2 write full line of zero disabled (bit3=0) 82 * (keep WFLZ low. Will be set once outer L2 is ready) 83 * 84 * NSACR = 0x00020C00 85 * - NSec cannot change ACTRL.SMP (NS_SMP bit18=0) 86 * - Nsec can lockdown TLB (TL bit17=1) 87 * - NSec cannot access PLE (PLE bit16=0) 88 * - NSec can use SIMD/VFP (CP10/CP11) (bit15:14=2b00, bit11:10=2b11) 89 * 90 * PCR = 0x00000001 91 * - no change latency, enable clk gating 92 */ 93 mov_imm r0, 0x00004000 94 write_sctlr r0 95 96 mov_imm r0, 0x00000041 97 write_actlr r0 98 99 mov_imm r0, 0x00020C00 100 write_nsacr r0 101 102 mov_imm r0, 0x00000001 103 write_pcr r0 104 105 mov pc, lr 106UNWIND( .fnend) 107END_FUNC plat_cpu_reset_early 108