1/* SPDX-License-Identifier: BSD-2-Clause */ 2/* 3 * Copyright (c) 2014, STMicroelectronics International N.V. 4 * All rights reserved. 5 * Copyright (c) 2016, Wind River Systems. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31/* 32 * Entry points for the A9 inits, A9 revision specific or not. 33 * It is assume no stack is available when these routines are called. 34 * It is assume each routine is called with return address in LR 35 * and with ARM registers R0, R1, R2, R3 being scratchable. 36 */ 37 38#include <arm32.h> 39#include <arm32_macros.S> 40#include <arm32_macros_cortex_a9.S> 41#include <asm.S> 42#include <kernel/tz_ssvce_def.h> 43#include <kernel/unwind.h> 44#include <platform_config.h> 45 46#define ZYNQ_SLCR_L2C_RAM 0xF8000A1C 47 48.section .text 49.balign 4 50.code 32 51 52/* 53 * Cortex A9 early configuration 54 * 55 * Use registers R0-R3. 56 * No stack usage. 57 * LR store return address. 58 * Trap CPU in case of error. 59 */ 60FUNC plat_cpu_reset_early , : 61UNWIND( .fnstart) 62 63 /* 64 * Disallow NSec to mask FIQ [bit4: FW=0] 65 * Allow NSec to manage Imprecise Abort [bit5: AW=1] 66 * Imprecise Abort trapped to Abort Mode [bit3: EA=0] 67 * In Sec world, FIQ trapped to FIQ Mode [bit2: FIQ=0] 68 * IRQ always trapped to IRQ Mode [bit1: IRQ=0] 69 * Secure World [bit0: NS=0] 70 */ 71 mov r0, #SCR_AW 72 write_scr r0 /* write Secure Configuration Register */ 73 74 /* 75 * Mandated HW config loaded 76 * 77 * SCTLR = 0x00004000 78 * - Round-Robin replac. for icache, btac, i/duTLB (bit14: RoundRobin) 79 * 80 * ACTRL = 0x00000041 81 * - core always in full SMP (FW bit0=1, SMP bit6=1) 82 * - L2 write full line of zero disabled (bit3=0) 83 * (keep WFLZ low. Will be set once outer L2 is ready) 84 * 85 * NSACR = 0x00020C00 86 * - NSec cannot change ACTRL.SMP (NS_SMP bit18=0) 87 * - Nsec can lockdown TLB (TL bit17=1) 88 * - NSec cannot access PLE (PLE bit16=0) 89 * - NSec can use SIMD/VFP (CP10/CP11) (bit15:14=2b00, bit11:10=2b11) 90 * 91 * PCR = 0x00000001 92 * - no change latency, enable clk gating 93 */ 94 mov_imm r0, 0x00004000 95 write_sctlr r0 96 97 mov_imm r0, 0x00000041 98 write_actlr r0 99 100 mov_imm r0, 0x00020C00 101 write_nsacr r0 102 103 mov_imm r0, 0x00000001 104 write_pcr r0 105 106 mov pc, lr 107UNWIND( .fnend) 108END_FUNC plat_cpu_reset_early 109