157f3d625Syanyan-wrsPLATFORM_FLAVOR ?= zc702 257f3d625Syanyan-wrs 343896851SEtienne Carriereinclude core/arch/arm/cpu/cortex-a9.mk 457f3d625Syanyan-wrs 59460285eSJerome Forissier$(call force,CFG_TEE_CORE_NB_CORE,2) 657f3d625Syanyan-wrs$(call force,CFG_ARM32_core,y) 757f3d625Syanyan-wrs$(call force,CFG_GIC,y) 857f3d625Syanyan-wrs$(call force,CFG_CDNS_UART,y) 957f3d625Syanyan-wrs$(call force,CFG_WITH_SOFTWARE_PRNG,y) 1057f3d625Syanyan-wrs$(call force,CFG_PL310,y) 1157f3d625Syanyan-wrs$(call force,CFG_PL310_LOCKED,y) 1257f3d625Syanyan-wrs$(call force,CFG_SECURE_TIME_SOURCE_REE,y) 1357f3d625Syanyan-wrs 14*217277deSVesa Jääskeläinen# Xilinx Zynq-7000's Cortex-A9 core has been configured with Non-maskable FIQ 15*217277deSVesa Jääskeläinen# (NMFI) support. This means that FIQ interrupts cannot be used in system 16*217277deSVesa Jääskeläinen# designs as atomic contexts cannot mask FIQ out. 17*217277deSVesa Jääskeläinen$(call force,CFG_CORE_WORKAROUND_ARM_NMFI,y) 18*217277deSVesa Jääskeläinen 1957f3d625Syanyan-wrsCFG_BOOT_SYNC_CPU ?= y 2057f3d625Syanyan-wrsCFG_BOOT_SECONDARY_REQUEST ?= y 2157f3d625Syanyan-wrsCFG_CRYPTO_SIZE_OPTIMIZATION ?= n 22909cd817SEtienne CarriereCFG_ENABLE_SCTLR_RR ?= y 23