1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) Foundries Ltd. 2022 - All Rights Reserved 4 */ 5 6 #include <arm.h> 7 #include <assert.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/pl011.h> 11 #include <drivers/versal_pm.h> 12 #include <io.h> 13 #include <kernel/boot.h> 14 #include <kernel/misc.h> 15 #include <kernel/tee_time.h> 16 #include <mm/core_memprot.h> 17 #include <platform_config.h> 18 #include <stdint.h> 19 #include <string.h> 20 #include <tee/tee_fs.h> 21 #include <trace.h> 22 23 #define VERSAL_AHWROT_SECURED 0xA5A5A5A5 24 #define VERSAL_SHWROT_SECURED 0x96969696 25 #define VERSAL_AHWROT_REG 0x14C 26 #define VERSAL_SHWROT_REG 0x150 27 28 static struct pl011_data console_data; 29 30 register_phys_mem_pgdir(MEM_AREA_IO_SEC, 31 ROUNDDOWN(CONSOLE_UART_BASE, CORE_MMU_PGDIR_SIZE), 32 CORE_MMU_PGDIR_SIZE); 33 34 register_phys_mem_pgdir(MEM_AREA_IO_SEC, 35 GIC_BASE, CORE_MMU_PGDIR_SIZE); 36 37 register_phys_mem_pgdir(MEM_AREA_IO_SEC, 38 GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE); 39 40 register_phys_mem(MEM_AREA_IO_SEC, PLM_RTCA, PLM_RTCA_LEN); 41 42 register_ddr(DRAM0_BASE, DRAM0_SIZE); 43 44 #if defined(DRAM1_BASE) 45 register_ddr(DRAM1_BASE, DRAM1_SIZE); 46 register_ddr(DRAM2_BASE, DRAM2_SIZE); 47 #endif 48 49 void boot_primary_init_intc(void) 50 { 51 gic_init(GIC_BASE + GICC_OFFSET, GIC_BASE + GICD_OFFSET); 52 } 53 54 void plat_console_init(void) 55 { 56 pl011_init(&console_data, CONSOLE_UART_BASE, 57 CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE); 58 register_serial_console(&console_data.chip); 59 } 60 61 static TEE_Result platform_banner(void) 62 { 63 vaddr_t plm_rtca = (vaddr_t)phys_to_virt(PLM_RTCA, MEM_AREA_IO_SEC, 64 PLM_RTCA_LEN); 65 const char __maybe_unused *ahwrot_str = "OFF"; 66 const char __maybe_unused *shwrot_str = "OFF"; 67 uint8_t version = 0; 68 69 assert(plm_rtca); 70 71 if (versal_soc_version(&version)) { 72 EMSG("Failure to retrieve SoC version"); 73 return TEE_ERROR_GENERIC; 74 } 75 76 IMSG("Platform Versal:\tSilicon Revision v%"PRIu8, version); 77 78 if (io_read32(plm_rtca + VERSAL_AHWROT_REG) == VERSAL_AHWROT_SECURED) 79 ahwrot_str = "ON"; 80 81 if (io_read32(plm_rtca + VERSAL_SHWROT_REG) == VERSAL_SHWROT_SECURED) 82 shwrot_str = "ON"; 83 84 IMSG("Hardware Root of Trust: Asymmetric[%s], Symmetric[%s]", 85 ahwrot_str, shwrot_str); 86 87 return TEE_SUCCESS; 88 } 89 90 #if defined(CFG_RPMB_FS) 91 bool plat_rpmb_key_is_ready(void) 92 { 93 vaddr_t plm_rtca = (vaddr_t)phys_to_virt(PLM_RTCA, MEM_AREA_IO_SEC, 94 PLM_RTCA_LEN); 95 96 assert(plm_rtca); 97 98 if (io_read32(plm_rtca + VERSAL_AHWROT_REG) == VERSAL_AHWROT_SECURED) 99 return true; 100 101 if (io_read32(plm_rtca + VERSAL_SHWROT_REG) == VERSAL_SHWROT_SECURED) 102 return true; 103 104 return false; 105 } 106 #endif 107 108 service_init(platform_banner); 109 110 #if defined(CFG_VERSAL_FPGA_DDR_ADDR) 111 static TEE_Result program_fpga(void) 112 { 113 return versal_write_fpga(CFG_VERSAL_FPGA_DDR_ADDR); 114 } 115 116 service_init(program_fpga); 117 #endif 118