1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) Foundries Ltd. 2022 - All Rights Reserved 4 */ 5 6 #include <arm.h> 7 #include <assert.h> 8 #include <console.h> 9 #include <drivers/gic.h> 10 #include <drivers/pl011.h> 11 #include <drivers/versal_pm.h> 12 #include <io.h> 13 #include <kernel/boot.h> 14 #include <kernel/interrupt.h> 15 #include <kernel/misc.h> 16 #include <kernel/tee_time.h> 17 #include <mm/core_memprot.h> 18 #include <platform_config.h> 19 #include <stdint.h> 20 #include <string.h> 21 #include <tee/tee_fs.h> 22 #include <trace.h> 23 24 #define VERSAL_AHWROT_SECURED 0xA5A5A5A5 25 #define VERSAL_SHWROT_SECURED 0x96969696 26 #define VERSAL_AHWROT_REG 0x14C 27 #define VERSAL_SHWROT_REG 0x150 28 29 static struct gic_data gic_data; 30 static struct pl011_data console_data; 31 32 register_phys_mem_pgdir(MEM_AREA_IO_SEC, 33 ROUNDDOWN(CONSOLE_UART_BASE, CORE_MMU_PGDIR_SIZE), 34 CORE_MMU_PGDIR_SIZE); 35 36 register_phys_mem_pgdir(MEM_AREA_IO_SEC, 37 GIC_BASE, CORE_MMU_PGDIR_SIZE); 38 39 register_phys_mem_pgdir(MEM_AREA_IO_SEC, 40 GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE); 41 42 register_phys_mem(MEM_AREA_IO_SEC, PLM_RTCA, PLM_RTCA_LEN); 43 44 register_ddr(DRAM0_BASE, DRAM0_SIZE); 45 46 #if defined(DRAM1_BASE) 47 register_ddr(DRAM1_BASE, DRAM1_SIZE); 48 register_ddr(DRAM2_BASE, DRAM2_SIZE); 49 #endif 50 51 void main_init_gic(void) 52 { 53 /* On ARMv8, GIC configuration is initialized in ARM-TF */ 54 gic_init_base_addr(&gic_data, 55 GIC_BASE + GICC_OFFSET, 56 GIC_BASE + GICD_OFFSET); 57 } 58 59 void itr_core_handler(void) 60 { 61 gic_it_handle(&gic_data); 62 } 63 64 void console_init(void) 65 { 66 pl011_init(&console_data, CONSOLE_UART_BASE, 67 CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE); 68 register_serial_console(&console_data.chip); 69 } 70 71 static TEE_Result platform_banner(void) 72 { 73 vaddr_t plm_rtca = (vaddr_t)phys_to_virt(PLM_RTCA, MEM_AREA_IO_SEC, 74 PLM_RTCA_LEN); 75 const char *ahwrot_str = "OFF"; 76 const char *shwrot_str = "OFF"; 77 uint8_t version = 0; 78 79 assert(plm_rtca); 80 81 if (versal_soc_version(&version)) { 82 EMSG("Failure to retrieve SoC version"); 83 return TEE_ERROR_GENERIC; 84 } 85 86 IMSG("Platform Versal:\tSilicon Revision v%"PRIu8, version); 87 88 if (io_read32(plm_rtca + VERSAL_AHWROT_REG) == VERSAL_AHWROT_SECURED) 89 ahwrot_str = "ON"; 90 91 if (io_read32(plm_rtca + VERSAL_SHWROT_REG) == VERSAL_SHWROT_SECURED) 92 shwrot_str = "ON"; 93 94 IMSG("Hardware Root of Trust: Asymmetric[%s], Symmetric[%s]", 95 ahwrot_str, shwrot_str); 96 97 return TEE_SUCCESS; 98 } 99 100 #if defined(CFG_RPMB_FS) 101 bool plat_rpmb_key_is_ready(void) 102 { 103 vaddr_t plm_rtca = (vaddr_t)phys_to_virt(PLM_RTCA, MEM_AREA_IO_SEC, 104 PLM_RTCA_LEN); 105 106 assert(plm_rtca); 107 108 if (io_read32(plm_rtca + VERSAL_AHWROT_REG) == VERSAL_AHWROT_SECURED) 109 return true; 110 111 if (io_read32(plm_rtca + VERSAL_SHWROT_REG) == VERSAL_SHWROT_SECURED) 112 return true; 113 114 return false; 115 } 116 #endif 117 118 service_init(platform_banner); 119 120 #if defined(CFG_VERSAL_FPGA_DDR_ADDR) 121 static TEE_Result program_fpga(void) 122 { 123 return versal_write_fpga(CFG_VERSAL_FPGA_DDR_ADDR); 124 } 125 126 service_init(program_fpga); 127 #endif 128