xref: /optee_os/core/arch/arm/plat-versal/main.c (revision 039e02df2716a0ed886b56e1e07b7ac1d8597228)
1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3  * Copyright (C) Foundries Ltd. 2022 - All Rights Reserved
4  */
5 
6 #include <arm.h>
7 #include <console.h>
8 #include <drivers/gic.h>
9 #include <drivers/pl011.h>
10 #include <kernel/boot.h>
11 #include <kernel/interrupt.h>
12 #include <kernel/misc.h>
13 #include <kernel/tee_time.h>
14 #include <mm/core_memprot.h>
15 #include <platform_config.h>
16 #include <stdint.h>
17 #include <string.h>
18 #include <trace.h>
19 
20 static struct gic_data gic_data;
21 static struct pl011_data console_data;
22 
23 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
24 			ROUNDDOWN(CONSOLE_UART_BASE, CORE_MMU_PGDIR_SIZE),
25 			CORE_MMU_PGDIR_SIZE);
26 
27 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
28 			GIC_BASE, CORE_MMU_PGDIR_SIZE);
29 
30 register_phys_mem_pgdir(MEM_AREA_IO_SEC,
31 			GIC_BASE + GICD_OFFSET, CORE_MMU_PGDIR_SIZE);
32 
33 register_ddr(DRAM0_BASE, DRAM0_SIZE);
34 
35 #if defined(DRAM1_BASE)
36 register_ddr(DRAM1_BASE, DRAM1_SIZE);
37 register_ddr(DRAM2_BASE, DRAM2_SIZE);
38 #endif
39 
40 void main_init_gic(void)
41 {
42 	/* On ARMv8, GIC configuration is initialized in ARM-TF */
43 	gic_init_base_addr(&gic_data,
44 			   GIC_BASE + GICC_OFFSET,
45 			   GIC_BASE + GICD_OFFSET);
46 }
47 
48 void itr_core_handler(void)
49 {
50 	gic_it_handle(&gic_data);
51 }
52 
53 void console_init(void)
54 {
55 	pl011_init(&console_data, CONSOLE_UART_BASE,
56 		   CONSOLE_UART_CLK_IN_HZ, CONSOLE_BAUDRATE);
57 	register_serial_console(&console_data.chip);
58 }
59