1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2021, Arm Limited. All rights reserved. 4 */ 5 6 #include <arm.h> 7 #include <console.h> 8 #include <drivers/gic.h> 9 #include <drivers/pl011.h> 10 #include <initcall.h> 11 #include <kernel/boot.h> 12 #include <kernel/interrupt.h> 13 #include <kernel/misc.h> 14 #include <kernel/panic.h> 15 16 #include <mm/core_mmu.h> 17 #include <platform_config.h> 18 19 #ifndef CFG_CORE_SEL2_SPMC 20 static struct gic_data gic_data __nex_bss; 21 #endif 22 static struct pl011_data console_data __nex_bss; 23 24 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE); 25 #ifndef CFG_CORE_SEL2_SPMC 26 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE); 27 #endif 28 29 register_ddr(DRAM0_BASE, DRAM0_SIZE); 30 register_ddr(DRAM1_BASE, DRAM1_SIZE); 31 32 #ifndef CFG_CORE_SEL2_SPMC 33 void main_init_gic(void) 34 { 35 /* 36 * On ARMv8, GIC configuration is initialized in ARM-TF 37 * gicd base address is same as gicc_base. 38 */ 39 gic_init_base_addr(&gic_data, GIC_BASE + GICC_OFFSET, 40 GIC_BASE + GICC_OFFSET); 41 itr_init(&gic_data.chip); 42 } 43 #endif 44 45 void itr_core_handler(void) 46 { 47 #ifdef CFG_CORE_SEL2_SPMC 48 panic("Secure interrupt handler not defined"); 49 #else 50 gic_it_handle(&gic_data); 51 #endif 52 } 53 54 void console_init(void) 55 { 56 pl011_init(&console_data, CONSOLE_UART_BASE, CONSOLE_UART_CLK_IN_HZ, 57 CONSOLE_UART_BAUDRATE); 58 register_serial_console(&console_data.chip); 59 } 60