1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2014, Allwinner Technology Co., Ltd. 4 * Copyright (c) 2018, Linaro Limited 5 * Copyright (c) 2018, Amit Singh Tomar <amittomer25@gmail.com> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <console.h> 32 #include <io.h> 33 #include <stdint.h> 34 #include <drivers/gic.h> 35 #include <drivers/serial8250_uart.h> 36 #include <drivers/tzc380.h> 37 #include <kernel/boot.h> 38 #include <kernel/misc.h> 39 #include <kernel/panic.h> 40 #include <kernel/pm_stubs.h> 41 #include <kernel/tz_ssvce_def.h> 42 #include <mm/core_mmu.h> 43 #include <mm/core_memprot.h> 44 #include <mm/tee_pager.h> 45 #include <platform_config.h> 46 #include <sm/optee_smc.h> 47 #include <tee/entry_fast.h> 48 #include <tee/entry_std.h> 49 50 #ifdef GIC_BASE 51 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE); 52 #endif 53 54 #ifdef CONSOLE_UART_BASE 55 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, 56 CONSOLE_UART_BASE, SUNXI_UART_REG_SIZE); 57 #endif 58 59 #ifdef SUNXI_TZPC_BASE 60 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_TZPC_BASE, SUNXI_TZPC_REG_SIZE); 61 #define REG_TZPC_SMTA_DECPORT0_STA_REG (0x0004) 62 #define REG_TZPC_SMTA_DECPORT0_SET_REG (0x0008) 63 #define REG_TZPC_SMTA_DECPORT0_CLR_REG (0x000C) 64 #define REG_TZPC_SMTA_DECPORT1_STA_REG (0x0010) 65 #define REG_TZPC_SMTA_DECPORT1_SET_REG (0x0014) 66 #define REG_TZPC_SMTA_DECPORT1_CLR_REG (0x0018) 67 #define REG_TZPC_SMTA_DECPORT2_STA_REG (0x001c) 68 #define REG_TZPC_SMTA_DECPORT2_SET_REG (0x0020) 69 #define REG_TZPC_SMTA_DECPORT2_CLR_REG (0x0024) 70 #endif 71 72 #ifdef SUNXI_CPUCFG_BASE 73 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_CPUCFG_BASE, 74 SUNXI_CPUCFG_REG_SIZE); 75 #endif 76 77 #ifdef SUNXI_PRCM_BASE 78 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_PRCM_BASE, SUNXI_PRCM_REG_SIZE); 79 #endif 80 81 #ifdef CFG_TZC380 82 vaddr_t smc_base(void); 83 register_phys_mem_pgdir(MEM_AREA_IO_SEC, SUNXI_SMC_BASE, TZC400_REG_SIZE); 84 #define SMC_MASTER_BYPASS 0x18 85 #define SMC_MASTER_BYPASS_EN_MASK 0x1 86 #endif 87 88 #ifdef GIC_BASE 89 static struct gic_data gic_data; 90 #endif 91 #ifdef SUNXI_TZPC_BASE 92 static void tzpc_init(void); 93 #endif 94 95 static const struct thread_handlers handlers = { 96 #if defined(CFG_WITH_ARM_TRUSTED_FW) 97 .cpu_on = cpu_on_handler, 98 .cpu_off = pm_do_nothing, 99 .cpu_suspend = pm_do_nothing, 100 .cpu_resume = pm_do_nothing, 101 .system_off = pm_do_nothing, 102 .system_reset = pm_do_nothing, 103 #else 104 .cpu_on = pm_panic, 105 .cpu_off = pm_panic, 106 .cpu_suspend = pm_panic, 107 .cpu_resume = pm_panic, 108 .system_off = pm_panic, 109 .system_reset = pm_panic, 110 #endif 111 }; 112 113 static struct serial8250_uart_data console_data; 114 115 const struct thread_handlers *boot_get_handlers(void) 116 { 117 return &handlers; 118 } 119 120 void console_init(void) 121 { 122 serial8250_uart_init(&console_data, 123 CONSOLE_UART_BASE, 124 CONSOLE_UART_CLK_IN_HZ, 125 CONSOLE_BAUDRATE); 126 register_serial_console(&console_data.chip); 127 } 128 129 #ifdef SUNXI_TZPC_BASE 130 static void tzpc_init(void) 131 { 132 vaddr_t v = (vaddr_t)phys_to_virt(SUNXI_TZPC_BASE, MEM_AREA_IO_SEC); 133 134 DMSG("SMTA_DECPORT0=%x", io_read32(v + REG_TZPC_SMTA_DECPORT0_STA_REG)); 135 DMSG("SMTA_DECPORT1=%x", io_read32(v + REG_TZPC_SMTA_DECPORT1_STA_REG)); 136 DMSG("SMTA_DECPORT2=%x", io_read32(v + REG_TZPC_SMTA_DECPORT2_STA_REG)); 137 138 /* Allow all peripherals for normal world */ 139 io_write32(v + REG_TZPC_SMTA_DECPORT0_SET_REG, 0xbe); 140 io_write32(v + REG_TZPC_SMTA_DECPORT1_SET_REG, 0xff); 141 io_write32(v + REG_TZPC_SMTA_DECPORT2_SET_REG, 0x7f); 142 143 DMSG("SMTA_DECPORT0=%x", io_read32(v + REG_TZPC_SMTA_DECPORT0_STA_REG)); 144 DMSG("SMTA_DECPORT1=%x", io_read32(v + REG_TZPC_SMTA_DECPORT1_STA_REG)); 145 DMSG("SMTA_DECPORT2=%x", io_read32(v + REG_TZPC_SMTA_DECPORT2_STA_REG)); 146 } 147 #else 148 static inline void tzpc_init(void) 149 { 150 } 151 #endif /* SUNXI_TZPC_BASE */ 152 153 #ifndef CFG_WITH_ARM_TRUSTED_FW 154 void main_init_gic(void) 155 { 156 vaddr_t gicc_base; 157 vaddr_t gicd_base; 158 159 gicc_base = core_mmu_get_va(GIC_BASE + GICC_OFFSET, MEM_AREA_IO_SEC); 160 gicd_base = core_mmu_get_va(GIC_BASE + GICD_OFFSET, MEM_AREA_IO_SEC); 161 162 if (!gicc_base || !gicd_base) 163 panic(); 164 165 /* Initialize GIC */ 166 gic_init(&gic_data, gicc_base, gicd_base); 167 itr_init(&gic_data.chip); 168 } 169 170 void main_secondary_init_gic(void) 171 { 172 gic_cpu_init(&gic_data); 173 } 174 #endif 175 176 #ifdef ARM32 177 void plat_primary_init_early(void) 178 { 179 assert(!cpu_mmu_enabled()); 180 181 tzpc_init(); 182 } 183 #endif 184 185 /* 186 * Allwinner's A64 has TZC380 like controller called SMC that can 187 * be programmed to protect parts of DRAM from non-secure world. 188 */ 189 #ifdef CFG_TZC380 190 vaddr_t smc_base(void) 191 { 192 return (vaddr_t)phys_to_virt(SUNXI_SMC_BASE, MEM_AREA_IO_SEC); 193 } 194 195 static TEE_Result smc_init(void) 196 { 197 vaddr_t base = smc_base(); 198 199 if (!base) { 200 EMSG("smc not mapped"); 201 panic(); 202 } 203 204 tzc_init(base); 205 tzc_configure_region(0, 0x0, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_1G) | 206 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); 207 tzc_configure_region(1, 0x0, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_32M) | 208 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_S_RW); 209 210 /* SoC specific bits */ 211 io_clrbits32(base + SMC_MASTER_BYPASS, SMC_MASTER_BYPASS_EN_MASK); 212 213 return TEE_SUCCESS; 214 } 215 216 driver_init(smc_init); 217 #endif /* CFG_TZC380 */ 218