1flavor_dts_file-257F_EV1 = stm32mp257f-ev1.dts 2 3flavorlist-MP25 = $(flavor_dts_file-257F_EV1) 4 5ifneq ($(PLATFORM_FLAVOR),) 6ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 7$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 8endif 9CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 10endif 11CFG_EMBED_DTB_SOURCE_FILE ?= stm32mp257f-ev1.dts 12 13ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP25)),) 14$(call force,CFG_STM32MP25,y) 15endif 16 17ifneq ($(CFG_STM32MP25),y) 18$(error STM32 Platform must be defined) 19endif 20 21include core/arch/arm/cpu/cortex-armv8-0.mk 22supported-ta-targets ?= ta_arm64 23 24$(call force,CFG_ARM64_core,y) 25$(call force,CFG_DRIVERS_CLK,y) 26$(call force,CFG_DRIVERS_CLK_DT,y) 27$(call force,CFG_DRIVERS_GPIO,y) 28$(call force,CFG_DRIVERS_PINCTRL,y) 29$(call force,CFG_DT,y) 30$(call force,CFG_GIC,y) 31$(call force,CFG_HALT_CORES_ON_PANIC_SGI,15) 32$(call force,CFG_INIT_CNTVOFF,y) 33$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 34$(call force,CFG_STM32_SHARED_IO,y) 35$(call force,CFG_STM32MP_CLK_CORE,y) 36$(call force,CFG_STM32MP25_CLK,y) 37$(call force,CFG_STM32MP25_RSTCTRL,y) 38$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 39$(call force,CFG_WITH_LPAE,y) 40 41CFG_TZDRAM_START ?= 0x82000000 42CFG_TZDRAM_SIZE ?= 0x02000000 43 44# Support DDR ranges up to 8GBytes (address range: 0x80000000 + DDR size) 45CFG_CORE_LARGE_PHYS_ADDR ?= y 46CFG_CORE_ARM64_PA_BITS ?= 34 47 48CFG_CORE_HEAP_SIZE ?= 262144 49CFG_CORE_RESERVED_SHM ?= n 50CFG_DTB_MAX_SIZE ?= 262144 51CFG_HALT_CORES_ON_PANIC ?= y 52CFG_MMAP_REGIONS ?= 30 53CFG_NUM_THREADS ?= 5 54CFG_TEE_CORE_NB_CORE ?= 2 55CFG_STM32MP_OPP_COUNT ?= 3 56 57CFG_STM32_FMC ?= y 58CFG_STM32_GPIO ?= y 59CFG_STM32_HPDMA ?= y 60CFG_STM32_HSEM ?= y 61CFG_STM32_IAC ?= y 62CFG_STM32_IPCC ?= y 63CFG_STM32_RIF ?= y 64CFG_STM32_RIFSC ?= y 65CFG_STM32_RNG ?= y 66CFG_STM32_SERC ?= y 67CFG_STM32_UART ?= y 68 69# Default enable some test facitilites 70CFG_ENABLE_EMBEDDED_TESTS ?= y 71CFG_WITH_STATS ?= y 72 73# Default disable ASLR 74CFG_CORE_ASLR ?= n 75 76# UART instance used for early console (0 disables early console) 77CFG_STM32_EARLY_CONSOLE_UART ?= 2 78 79# Default disable external DT support 80CFG_EXTERNAL_DT ?= n 81 82# Default enable HWRNG PTA support 83CFG_HWRNG_PTA ?= y 84ifeq ($(CFG_HWRNG_PTA),y) 85$(call force,CFG_STM32_RNG,y,Required by CFG_HWRNG_PTA) 86$(call force,CFG_WITH_SOFTWARE_PRNG,n,Required by CFG_HWRNG_PTA) 87CFG_HWRNG_QUALITY ?= 1024 88endif 89 90# Enable reset control 91ifeq ($(CFG_STM32MP25_RSTCTRL),y) 92$(call force,CFG_DRIVERS_RSTCTRL,y) 93$(call force,CFG_STM32_RSTCTRL,y) 94endif 95 96# Optional behavior upon receiving illegal access events 97CFG_STM32_PANIC_ON_IAC_EVENT ?= y 98ifeq ($(CFG_TEE_CORE_DEBUG),y) 99CFG_STM32_PANIC_ON_SERC_EVENT ?= n 100else 101CFG_STM32_PANIC_ON_SERC_EVENT ?= y 102endif 103