1flavor_dts_file-215F_DK = stm32mp215f-dk.dts 2flavor_dts_file-257F_DK = stm32mp257f-dk.dts 3flavor_dts_file-257F_EV1 = stm32mp257f-ev1.dts 4 5flavorlist-MP21 = $(flavor_dts_file-215F_DK) 6flavorlist-MP25 = $(flavor_dts_file-257F_DK) \ 7 $(flavor_dts_file-257F_EV1) 8 9# List of all DTS for this PLATFORM 10ALL_DTS = $(flavorlist-MP21) $(flavorlist-MP25) 11 12ifneq ($(PLATFORM_FLAVOR),) 13ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 14$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 15endif 16CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 17endif 18CFG_EMBED_DTB_SOURCE_FILE ?= stm32mp257f-ev1.dts 19 20ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP21)),) 21$(call force,CFG_STM32MP21,y) 22endif 23ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP25)),) 24$(call force,CFG_STM32MP25,y) 25endif 26 27# CFG_STM32MP2x switches are exclusive. 28# - CFG_STM32MP21 is enabled for STM32MP21x-* targets 29# - CFG_STM32MP25 is enabled for STM32MP25x-* targets (default) 30ifeq ($(CFG_STM32MP21),y) 31$(call force,CFG_STM32MP25,n) 32else 33$(call force,CFG_STM32MP21,n) 34$(call force,CFG_STM32MP25,y) 35endif 36 37include core/arch/arm/cpu/cortex-armv8-0.mk 38supported-ta-targets ?= ta_arm64 39 40$(call force,CFG_ARM64_core,y) 41$(call force,CFG_CORE_ASYNC_NOTIF,y) 42$(call force,CFG_CORE_ASYNC_NOTIF_GIC_INTID,31) 43$(call force,CFG_DRIVERS_CLK,y) 44$(call force,CFG_DRIVERS_CLK_DT,y) 45$(call force,CFG_DRIVERS_GPIO,y) 46$(call force,CFG_DRIVERS_PINCTRL,y) 47$(call force,CFG_DT,y) 48$(call force,CFG_GIC,y) 49$(call force,CFG_HALT_CORES_SGI,15) 50$(call force,CFG_INIT_CNTVOFF,y) 51$(call force,CFG_SCMI_SCPFW_PRODUCT,stm32mp2) 52$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 53$(call force,CFG_STM32_SHARED_IO,y) 54$(call force,CFG_STM32_STGEN,y) 55$(call force,CFG_STM32MP_CLK_CORE,y) 56$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 57$(call force,CFG_WITH_LPAE,y) 58 59ifeq ($(CFG_STM32MP21),y) 60$(call force,CFG_STM32MP21_CLK,y) 61$(call force,CFG_STM32MP21_RSTCTRL,y) 62else 63$(call force,CFG_STM32MP25_CLK,y) 64$(call force,CFG_STM32MP25_RSTCTRL,y) 65endif 66 67CFG_TZDRAM_START ?= 0x82000000 68CFG_TZDRAM_SIZE ?= 0x02000000 69 70# Support DDR ranges up to 8GBytes (address range: 0x80000000 + DDR size) 71CFG_CORE_LARGE_PHYS_ADDR ?= y 72CFG_CORE_ARM64_PA_BITS ?= 34 73 74CFG_CORE_HEAP_SIZE ?= 262144 75CFG_CORE_RESERVED_SHM ?= n 76CFG_DTB_MAX_SIZE ?= 262144 77CFG_MULTI_CORE_HALTING ?= y 78CFG_MMAP_REGIONS ?= 30 79CFG_NUM_THREADS ?= 5 80ifeq ($(CFG_STM32MP21),y) 81$(call force,CFG_TEE_CORE_NB_CORE,1) 82endif 83CFG_TEE_CORE_NB_CORE ?= 2 84CFG_STM32MP_OPP_COUNT ?= 3 85 86CFG_STM32_EXTI ?= y 87CFG_STM32_FMC ?= y 88CFG_STM32_GPIO ?= y 89CFG_STM32_HPDMA ?= y 90CFG_STM32_HSEM ?= y 91CFG_STM32_IAC ?= y 92CFG_STM32_IPCC ?= y 93CFG_STM32_IWDG ?= y 94CFG_STM32_OMM ?= y 95CFG_STM32_RIF ?= y 96CFG_STM32_RIFSC ?= y 97CFG_STM32_RISAB ?= y 98CFG_STM32_RISAF ?= y 99CFG_STM32_RNG ?= y 100CFG_STM32_RTC ?= y 101CFG_STM32_SERC ?= y 102CFG_STM32_TAMP ?= y 103CFG_STM32_UART ?= y 104 105# Default RTC accuracy, higher accuracy means higher power consumption 106CFG_STM32_RTC_HIGH_ACCURACY ?= n 107 108CFG_SCMI_PTA ?= y 109CFG_SCMI_SCPFW ?= n 110CFG_SCMI_SCPFW_FROM_DT ?= y 111CFG_SCMI_SERVER_CLOCK_CONSUMER ?= y 112CFG_SCMI_SERVER_RESET_CONSUMER ?= y 113# Default enable some test facitilites 114CFG_ENABLE_EMBEDDED_TESTS ?= y 115CFG_WITH_STATS ?= y 116 117# Default disable ASLR 118CFG_CORE_ASLR ?= n 119 120# UART instance used for early console (0 disables early console) 121CFG_STM32_EARLY_CONSOLE_UART ?= 2 122 123# Default disable external DT support 124CFG_EXTERNAL_DT ?= n 125 126# Default enable HWRNG PTA support 127CFG_HWRNG_PTA ?= y 128ifeq ($(CFG_HWRNG_PTA),y) 129$(call force,CFG_STM32_RNG,y,Required by CFG_HWRNG_PTA) 130$(call force,CFG_WITH_SOFTWARE_PRNG,n,Required by CFG_HWRNG_PTA) 131CFG_HWRNG_QUALITY ?= 1024 132endif 133 134# Watchdog SMC service to non-secure world 135CFG_WDT ?= $(CFG_STM32_IWDG) 136CFG_WDT_SM_HANDLER ?= $(CFG_WDT) 137CFG_WDT_SM_HANDLER_ID ?= 0xbc000000 138 139# Enable reset control 140ifeq ($(CFG_STM32MP21_RSTCTRL),y) 141$(call force,CFG_DRIVERS_RSTCTRL,y) 142$(call force,CFG_STM32_RSTCTRL,y) 143endif 144ifeq ($(CFG_STM32MP25_RSTCTRL),y) 145$(call force,CFG_DRIVERS_RSTCTRL,y) 146$(call force,CFG_STM32_RSTCTRL,y) 147endif 148 149# Optional behavior upon receiving illegal access events 150CFG_STM32_PANIC_ON_IAC_EVENT ?= y 151ifeq ($(CFG_TEE_CORE_DEBUG),y) 152CFG_STM32_PANIC_ON_SERC_EVENT ?= n 153else 154CFG_STM32_PANIC_ON_SERC_EVENT ?= y 155endif 156 157# Default enable firewall support 158CFG_DRIVERS_FIREWALL ?= y 159ifeq ($(call cfg-one-enabled, CFG_STM32_RISAB CFG_STM32_RIFSC),y) 160$(call force,CFG_DRIVERS_FIREWALL,y) 161endif 162 163# Enable RTC 164ifeq ($(CFG_STM32_RTC),y) 165$(call force,CFG_DRIVERS_RTC,y) 166$(call force,CFG_RTC_PTA,y) 167endif 168 169ifeq ($(CFG_STM32_SERC),y) 170$(call force,CFG_EXTERNAL_ABORT_PLAT_HANDLER,y) 171endif 172