1flavor_dts_file-257F_EV1 = stm32mp257f-ev1.dts 2 3flavorlist-MP25 = $(flavor_dts_file-257F_EV1) 4 5ifneq ($(PLATFORM_FLAVOR),) 6ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 7$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 8endif 9CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 10endif 11CFG_EMBED_DTB_SOURCE_FILE ?= stm32mp257f-ev1.dts 12 13ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP25)),) 14$(call force,CFG_STM32MP25,y) 15endif 16 17ifneq ($(CFG_STM32MP25),y) 18$(error STM32 Platform must be defined) 19endif 20 21include core/arch/arm/cpu/cortex-armv8-0.mk 22supported-ta-targets ?= ta_arm64 23 24$(call force,CFG_ARM64_core,y) 25$(call force,CFG_DRIVERS_CLK,y) 26$(call force,CFG_DRIVERS_CLK_DT,y) 27$(call force,CFG_DRIVERS_GPIO,y) 28$(call force,CFG_DRIVERS_PINCTRL,y) 29$(call force,CFG_DT,y) 30$(call force,CFG_GIC,y) 31$(call force,CFG_HALT_CORES_ON_PANIC_SGI,15) 32$(call force,CFG_INIT_CNTVOFF,y) 33$(call force,CFG_SCMI_SCPFW_PRODUCT,stm32mp2) 34$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 35$(call force,CFG_STM32_SHARED_IO,y) 36$(call force,CFG_STM32_STGEN,y) 37$(call force,CFG_STM32MP_CLK_CORE,y) 38$(call force,CFG_STM32MP25_CLK,y) 39$(call force,CFG_STM32MP25_RSTCTRL,y) 40$(call force,CFG_WITH_ARM_TRUSTED_FW,y) 41$(call force,CFG_WITH_LPAE,y) 42 43CFG_TZDRAM_START ?= 0x82000000 44CFG_TZDRAM_SIZE ?= 0x02000000 45 46# Support DDR ranges up to 8GBytes (address range: 0x80000000 + DDR size) 47CFG_CORE_LARGE_PHYS_ADDR ?= y 48CFG_CORE_ARM64_PA_BITS ?= 34 49 50CFG_CORE_HEAP_SIZE ?= 262144 51CFG_CORE_RESERVED_SHM ?= n 52CFG_DTB_MAX_SIZE ?= 262144 53CFG_HALT_CORES_ON_PANIC ?= y 54CFG_MMAP_REGIONS ?= 30 55CFG_NUM_THREADS ?= 5 56CFG_TEE_CORE_NB_CORE ?= 2 57CFG_STM32MP_OPP_COUNT ?= 3 58 59CFG_STM32_FMC ?= y 60CFG_STM32_GPIO ?= y 61CFG_STM32_HPDMA ?= y 62CFG_STM32_HSEM ?= y 63CFG_STM32_IAC ?= y 64CFG_STM32_IPCC ?= y 65CFG_STM32_OMM ?= y 66CFG_STM32_RIF ?= y 67CFG_STM32_RIFSC ?= y 68CFG_STM32_RISAB ?= y 69CFG_STM32_RISAF ?= y 70CFG_STM32_RNG ?= y 71CFG_STM32_RTC ?= y 72CFG_STM32_SERC ?= y 73CFG_STM32_TAMP ?= y 74CFG_STM32_UART ?= y 75 76CFG_SCMI_PTA ?= y 77CFG_SCMI_SCPFW ?= n 78CFG_SCMI_SCPFW_FROM_DT ?= y 79CFG_SCMI_SERVER_CLOCK_CONSUMER ?= y 80CFG_SCMI_SERVER_RESET_CONSUMER ?= y 81# Default enable some test facitilites 82CFG_ENABLE_EMBEDDED_TESTS ?= y 83CFG_WITH_STATS ?= y 84 85# Default disable ASLR 86CFG_CORE_ASLR ?= n 87 88# UART instance used for early console (0 disables early console) 89CFG_STM32_EARLY_CONSOLE_UART ?= 2 90 91# Default disable external DT support 92CFG_EXTERNAL_DT ?= n 93 94# Default enable HWRNG PTA support 95CFG_HWRNG_PTA ?= y 96ifeq ($(CFG_HWRNG_PTA),y) 97$(call force,CFG_STM32_RNG,y,Required by CFG_HWRNG_PTA) 98$(call force,CFG_WITH_SOFTWARE_PRNG,n,Required by CFG_HWRNG_PTA) 99CFG_HWRNG_QUALITY ?= 1024 100endif 101 102# Enable reset control 103ifeq ($(CFG_STM32MP25_RSTCTRL),y) 104$(call force,CFG_DRIVERS_RSTCTRL,y) 105$(call force,CFG_STM32_RSTCTRL,y) 106endif 107 108# Optional behavior upon receiving illegal access events 109CFG_STM32_PANIC_ON_IAC_EVENT ?= y 110ifeq ($(CFG_TEE_CORE_DEBUG),y) 111CFG_STM32_PANIC_ON_SERC_EVENT ?= n 112else 113CFG_STM32_PANIC_ON_SERC_EVENT ?= y 114endif 115 116# Default enable firewall support 117CFG_DRIVERS_FIREWALL ?= y 118ifeq ($(call cfg-one-enabled, CFG_STM32_RISAB CFG_STM32_RIFSC),y) 119$(call force,CFG_DRIVERS_FIREWALL,y) 120endif 121 122# Enable RTC 123ifeq ($(CFG_STM32_RTC),y) 124$(call force,CFG_DRIVERS_RTC,y) 125endif 126 127ifeq ($(CFG_STM32_SERC),y) 128$(call force,CFG_EXTERNAL_ABORT_PLAT_HANDLER,y) 129endif 130