1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (c) 2019, STMicroelectronics 4 */ 5 #include <assert.h> 6 #include <compiler.h> 7 #include <drivers/scmi-msg.h> 8 #include <drivers/scmi.h> 9 #include <dt-bindings/clock/stm32mp1-clks.h> 10 #include <dt-bindings/reset/stm32mp1-resets.h> 11 #include <initcall.h> 12 #include <mm/core_memprot.h> 13 #include <mm/core_mmu.h> 14 #include <platform_config.h> 15 #include <stdint.h> 16 #include <speculation_barrier.h> 17 #include <stm32_util.h> 18 #include <string.h> 19 #include <tee_api_defines.h> 20 #include <util.h> 21 22 #define TIMEOUT_US_1MS 1000 23 24 #define SCMI_CLOCK_NAME_SIZE 16 25 #define SCMI_RD_NAME_SIZE 16 26 27 /* 28 * struct stm32_scmi_clk - Data for the exposed clock 29 * @clock_id: Clock identifier in RCC clock driver 30 * @name: Clock string ID exposed to agent 31 * @enabled: State of the SCMI clock 32 */ 33 struct stm32_scmi_clk { 34 unsigned long clock_id; 35 const char *name; 36 bool enabled; 37 }; 38 39 /* 40 * struct stm32_scmi_rd - Data for the exposed reset controller 41 * @reset_id: Reset identifier in RCC reset driver 42 * @name: Reset string ID exposed to agent 43 */ 44 struct stm32_scmi_rd { 45 unsigned long reset_id; 46 const char *name; 47 }; 48 49 /* Locate all non-secure SMT message buffers in last page of SYSRAM */ 50 #define SMT_BUFFER_BASE CFG_STM32MP1_SCMI_SHM_BASE 51 #define SMT_BUFFER0_BASE SMT_BUFFER_BASE 52 #define SMT_BUFFER1_BASE (SMT_BUFFER_BASE + 0x200) 53 54 #if (SMT_BUFFER1_BASE + SMT_BUF_SLOT_SIZE > \ 55 CFG_STM32MP1_SCMI_SHM_BASE + CFG_STM32MP1_SCMI_SHM_SIZE) 56 #error "SCMI shared memory mismatch" 57 #endif 58 59 register_phys_mem(MEM_AREA_IO_NSEC, CFG_STM32MP1_SCMI_SHM_BASE, 60 CFG_STM32MP1_SCMI_SHM_SIZE); 61 62 static struct scmi_msg_channel scmi_channel[] = { 63 [0] = { 64 .agent_name = "stm32mp1-agent-0", 65 .shm_addr = { .pa = SMT_BUFFER0_BASE, }, 66 .shm_size = SMT_BUF_SLOT_SIZE, 67 }, 68 [1] = { 69 .agent_name = "stm32mp1-agent-1", 70 .shm_addr = { .pa = SMT_BUFFER1_BASE, }, 71 .shm_size = SMT_BUF_SLOT_SIZE, 72 }, 73 }; 74 75 struct scmi_msg_channel *plat_scmi_get_channel(unsigned int agent_id) 76 { 77 assert(agent_id < ARRAY_SIZE(scmi_channel)); 78 79 return &scmi_channel[agent_id]; 80 } 81 82 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ 83 [_scmi_id] = { \ 84 .clock_id = _id, \ 85 .name = _name, \ 86 .enabled = _init_enabled, \ 87 } 88 89 struct stm32_scmi_clk stm32_scmi0_clock[] = { 90 CLOCK_CELL(CK_SCMI0_HSE, CK_HSE, "ck_hse", true), 91 CLOCK_CELL(CK_SCMI0_HSI, CK_HSI, "ck_hsi", true), 92 CLOCK_CELL(CK_SCMI0_CSI, CK_CSI, "ck_csi", true), 93 CLOCK_CELL(CK_SCMI0_LSE, CK_LSE, "ck_lse", true), 94 CLOCK_CELL(CK_SCMI0_LSI, CK_LSI, "ck_lsi", true), 95 CLOCK_CELL(CK_SCMI0_PLL2_Q, PLL2_Q, "pll2_q", true), 96 CLOCK_CELL(CK_SCMI0_PLL2_R, PLL2_R, "pll2_r", true), 97 CLOCK_CELL(CK_SCMI0_MPU, CK_MPU, "ck_mpu", true), 98 CLOCK_CELL(CK_SCMI0_AXI, CK_AXI, "ck_axi", true), 99 CLOCK_CELL(CK_SCMI0_BSEC, BSEC, "bsec", true), 100 CLOCK_CELL(CK_SCMI0_CRYP1, CRYP1, "cryp1", false), 101 CLOCK_CELL(CK_SCMI0_GPIOZ, GPIOZ, "gpioz", false), 102 CLOCK_CELL(CK_SCMI0_HASH1, HASH1, "hash1", false), 103 CLOCK_CELL(CK_SCMI0_I2C4, I2C4_K, "i2c4_k", false), 104 CLOCK_CELL(CK_SCMI0_I2C6, I2C6_K, "i2c6_k", false), 105 CLOCK_CELL(CK_SCMI0_IWDG1, IWDG1, "iwdg1", false), 106 CLOCK_CELL(CK_SCMI0_RNG1, RNG1_K, "rng1_k", true), 107 CLOCK_CELL(CK_SCMI0_RTC, RTC, "ck_rtc", true), 108 CLOCK_CELL(CK_SCMI0_RTCAPB, RTCAPB, "rtcapb", true), 109 CLOCK_CELL(CK_SCMI0_SPI6, SPI6_K, "spi6_k", false), 110 CLOCK_CELL(CK_SCMI0_USART1, USART1_K, "usart1_k", false), 111 }; 112 113 struct stm32_scmi_clk stm32_scmi1_clock[] = { 114 CLOCK_CELL(CK_SCMI1_PLL3_Q, PLL3_Q, "pll3_q", true), 115 CLOCK_CELL(CK_SCMI1_PLL3_R, PLL3_R, "pll3_r", true), 116 CLOCK_CELL(CK_SCMI1_MCU, CK_MCU, "ck_mcu", false), 117 }; 118 119 #define RESET_CELL(_scmi_id, _id, _name) \ 120 [_scmi_id] = { \ 121 .reset_id = _id, \ 122 .name = _name, \ 123 } 124 125 struct stm32_scmi_rd stm32_scmi0_reset_domain[] = { 126 RESET_CELL(RST_SCMI0_SPI6, SPI6_R, "spi6"), 127 RESET_CELL(RST_SCMI0_I2C4, I2C4_R, "i2c4"), 128 RESET_CELL(RST_SCMI0_I2C6, I2C6_R, "i2c6"), 129 RESET_CELL(RST_SCMI0_USART1, USART1_R, "usart1"), 130 RESET_CELL(RST_SCMI0_STGEN, STGEN_R, "stgen"), 131 RESET_CELL(RST_SCMI0_GPIOZ, GPIOZ_R, "gpioz"), 132 RESET_CELL(RST_SCMI0_CRYP1, CRYP1_R, "cryp1"), 133 RESET_CELL(RST_SCMI0_HASH1, HASH1_R, "hash1"), 134 RESET_CELL(RST_SCMI0_RNG1, RNG1_R, "rng1"), 135 RESET_CELL(RST_SCMI0_MDMA, MDMA_R, "mdma"), 136 RESET_CELL(RST_SCMI0_MCU, MCU_R, "mcu"), 137 }; 138 139 struct scmi_agent_resources { 140 struct stm32_scmi_clk *clock; 141 size_t clock_count; 142 struct stm32_scmi_rd *rd; 143 size_t rd_count; 144 struct stm32_scmi_pd *pd; 145 size_t pd_count; 146 struct stm32_scmi_perfs *perfs; 147 size_t perfs_count; 148 }; 149 150 const struct scmi_agent_resources agent_resources[] = { 151 [0] = { 152 .clock = stm32_scmi0_clock, 153 .clock_count = ARRAY_SIZE(stm32_scmi0_clock), 154 .rd = stm32_scmi0_reset_domain, 155 .rd_count = ARRAY_SIZE(stm32_scmi0_reset_domain), 156 }, 157 [1] = { 158 .clock = stm32_scmi1_clock, 159 .clock_count = ARRAY_SIZE(stm32_scmi1_clock), 160 }, 161 }; 162 163 static const struct scmi_agent_resources *find_resource(unsigned int agent_id) 164 { 165 assert(agent_id < ARRAY_SIZE(agent_resources)); 166 167 return &agent_resources[agent_id]; 168 } 169 170 static size_t __maybe_unused plat_scmi_protocol_count_paranoid(void) 171 { 172 unsigned int n = 0; 173 unsigned int count = 0; 174 const size_t agent_count = ARRAY_SIZE(agent_resources); 175 176 for (n = 0; n < agent_count; n++) 177 if (agent_resources[n].clock_count) 178 break; 179 if (n < agent_count) 180 count++; 181 182 for (n = 0; n < agent_count; n++) 183 if (agent_resources[n].rd_count) 184 break; 185 if (n < agent_count) 186 count++; 187 188 for (n = 0; n < agent_count; n++) 189 if (agent_resources[n].pd_count) 190 break; 191 if (n < agent_count) 192 count++; 193 194 for (n = 0; n < agent_count; n++) 195 if (agent_resources[n].perfs_count) 196 break; 197 if (n < agent_count) 198 count++; 199 200 return count; 201 } 202 203 static const char vendor[] = "ST"; 204 static const char sub_vendor[] = ""; 205 206 const char *plat_scmi_vendor_name(void) 207 { 208 return vendor; 209 } 210 211 const char *plat_scmi_sub_vendor_name(void) 212 { 213 return sub_vendor; 214 } 215 216 /* Currently supporting Clocks and Reset Domains */ 217 static const uint8_t plat_protocol_list[] = { 218 SCMI_PROTOCOL_ID_CLOCK, 219 SCMI_PROTOCOL_ID_RESET_DOMAIN, 220 0 /* Null termination */ 221 }; 222 223 size_t plat_scmi_protocol_count(void) 224 { 225 const size_t count = ARRAY_SIZE(plat_protocol_list) - 1; 226 227 assert(count == plat_scmi_protocol_count_paranoid()); 228 229 return count; 230 } 231 232 const uint8_t *plat_scmi_protocol_list(unsigned int agent_id __unused) 233 { 234 assert(plat_scmi_protocol_count_paranoid() == 235 (ARRAY_SIZE(plat_protocol_list) - 1)); 236 237 return plat_protocol_list; 238 } 239 240 /* 241 * Platform SCMI clocks 242 */ 243 static struct stm32_scmi_clk *find_clock(unsigned int agent_id, 244 unsigned int scmi_id) 245 { 246 const struct scmi_agent_resources *resource = find_resource(agent_id); 247 size_t n = 0; 248 249 if (resource) { 250 for (n = 0U; n < resource->clock_count; n++) 251 if (n == scmi_id) 252 return &resource->clock[n]; 253 } 254 255 return NULL; 256 } 257 258 size_t plat_scmi_clock_count(unsigned int agent_id) 259 { 260 const struct scmi_agent_resources *resource = find_resource(agent_id); 261 262 if (!resource) 263 return 0; 264 265 return resource->clock_count; 266 } 267 268 const char *plat_scmi_clock_get_name(unsigned int agent_id, 269 unsigned int scmi_id) 270 { 271 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 272 273 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 274 return NULL; 275 276 return clock->name; 277 } 278 279 int32_t plat_scmi_clock_rates_array(unsigned int agent_id, unsigned int scmi_id, 280 unsigned long *array, size_t *nb_elts) 281 { 282 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 283 284 if (!clock) 285 return SCMI_NOT_FOUND; 286 287 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 288 return SCMI_DENIED; 289 290 if (!array) 291 *nb_elts = 1; 292 else if (*nb_elts == 1) 293 *array = stm32_clock_get_rate(clock->clock_id); 294 else 295 return SCMI_GENERIC_ERROR; 296 297 return SCMI_SUCCESS; 298 } 299 300 unsigned long plat_scmi_clock_get_rate(unsigned int agent_id, 301 unsigned int scmi_id) 302 { 303 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 304 305 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 306 return 0; 307 308 return stm32_clock_get_rate(clock->clock_id); 309 } 310 311 int32_t plat_scmi_clock_get_state(unsigned int agent_id, unsigned int scmi_id) 312 { 313 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 314 315 if (!clock || !stm32mp_nsec_can_access_clock(clock->clock_id)) 316 return 0; 317 318 return (int32_t)clock->enabled; 319 } 320 321 int32_t plat_scmi_clock_set_state(unsigned int agent_id, unsigned int scmi_id, 322 bool enable_not_disable) 323 { 324 struct stm32_scmi_clk *clock = find_clock(agent_id, scmi_id); 325 326 if (!clock) 327 return SCMI_NOT_FOUND; 328 329 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) 330 return SCMI_DENIED; 331 332 if (enable_not_disable) { 333 if (!clock->enabled) { 334 DMSG("SCMI clock %u enable", scmi_id); 335 stm32_clock_enable(clock->clock_id); 336 clock->enabled = true; 337 } 338 } else { 339 if (clock->enabled) { 340 DMSG("SCMI clock %u disable", scmi_id); 341 stm32_clock_disable(clock->clock_id); 342 clock->enabled = false; 343 } 344 } 345 346 return SCMI_SUCCESS; 347 } 348 349 /* 350 * Platform SCMI reset domains 351 */ 352 static struct stm32_scmi_rd *find_rd(unsigned int agent_id, 353 unsigned int scmi_id) 354 { 355 const struct scmi_agent_resources *resource = find_resource(agent_id); 356 size_t n = 0; 357 358 if (resource) { 359 for (n = 0; n < resource->rd_count; n++) 360 if (n == scmi_id) 361 return &resource->rd[n]; 362 } 363 364 return NULL; 365 } 366 367 const char *plat_scmi_rd_get_name(unsigned int agent_id, unsigned int scmi_id) 368 { 369 const struct stm32_scmi_rd *rd = find_rd(agent_id, scmi_id); 370 371 if (!rd) 372 return NULL; 373 374 return rd->name; 375 } 376 377 size_t plat_scmi_rd_count(unsigned int agent_id) 378 { 379 const struct scmi_agent_resources *resource = find_resource(agent_id); 380 381 if (!resource) 382 return 0; 383 384 return resource->rd_count; 385 } 386 387 int32_t plat_scmi_rd_autonomous(unsigned int agent_id, unsigned int scmi_id, 388 uint32_t state) 389 { 390 const struct stm32_scmi_rd *rd = find_rd(agent_id, scmi_id); 391 392 if (!rd) 393 return SCMI_NOT_FOUND; 394 395 if (!stm32mp_nsec_can_access_reset(rd->reset_id)) 396 return SCMI_DENIED; 397 398 /* Supports only reset with context loss */ 399 if (state) 400 return SCMI_NOT_SUPPORTED; 401 402 DMSG("SCMI reset %u cycle", scmi_id); 403 404 if (stm32_reset_assert(rd->reset_id, TIMEOUT_US_1MS)) 405 return SCMI_HARDWARE_ERROR; 406 407 if (stm32_reset_deassert(rd->reset_id, TIMEOUT_US_1MS)) 408 return SCMI_HARDWARE_ERROR; 409 410 return SCMI_SUCCESS; 411 } 412 413 int32_t plat_scmi_rd_set_state(unsigned int agent_id, unsigned int scmi_id, 414 bool assert_not_deassert) 415 { 416 const struct stm32_scmi_rd *rd = find_rd(agent_id, scmi_id); 417 418 if (!rd) 419 return SCMI_NOT_FOUND; 420 421 if (!stm32mp_nsec_can_access_reset(rd->reset_id)) 422 return SCMI_DENIED; 423 424 if (assert_not_deassert) { 425 DMSG("SCMI reset %u set", scmi_id); 426 stm32_reset_set(rd->reset_id); 427 } else { 428 DMSG("SCMI reset %u release", scmi_id); 429 stm32_reset_release(rd->reset_id); 430 } 431 432 return SCMI_SUCCESS; 433 } 434 435 /* 436 * Initialize platform SCMI resources 437 */ 438 static TEE_Result stm32mp1_init_scmi_server(void) 439 { 440 size_t i = 0; 441 size_t j = 0; 442 443 for (i = 0; i < ARRAY_SIZE(scmi_channel); i++) { 444 struct scmi_msg_channel *chan = &scmi_channel[i]; 445 446 /* Enforce non-secure shm mapped as device memory */ 447 chan->shm_addr.va = (vaddr_t)phys_to_virt(chan->shm_addr.pa, 448 MEM_AREA_IO_NSEC); 449 assert(chan->shm_addr.va); 450 451 scmi_smt_init_agent_channel(chan); 452 } 453 454 for (i = 0; i < ARRAY_SIZE(agent_resources); i++) { 455 const struct scmi_agent_resources *res = &agent_resources[i]; 456 457 for (j = 0; j < res->clock_count; j++) { 458 struct stm32_scmi_clk *clk = &res->clock[j]; 459 460 if (!clk->name || 461 strlen(clk->name) >= SCMI_CLOCK_NAME_SIZE) 462 panic("SCMI clock name invalid"); 463 464 /* Sync SCMI clocks with their targeted initial state */ 465 if (clk->enabled && 466 stm32mp_nsec_can_access_clock(clk->clock_id)) 467 stm32_clock_enable(clk->clock_id); 468 } 469 470 for (j = 0; j < res->rd_count; j++) { 471 struct stm32_scmi_rd *rd = &res->rd[j]; 472 473 if (!rd->name || 474 strlen(rd->name) >= SCMI_RD_NAME_SIZE) 475 panic("SCMI reset domain name invalid"); 476 } 477 } 478 479 return TEE_SUCCESS; 480 } 481 482 driver_init_late(stm32mp1_init_scmi_server); 483