1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DHCOR_AVENGER96 = stm32mp157a-dhcor-avenger96.dts 3flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 4flavor_dts_file-157C_DHCOM_PDK2 = stm32mp157c-dhcom-pdk2.dts 5flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 6flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 7flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 8flavor_dts_file-157A_DK1_SCMI = stm32mp157a-dk1-scmi.dts 9flavor_dts_file-157C_DK2_SCMI = stm32mp157c-dk2-scmi.dts 10flavor_dts_file-157C_ED1_SCMI = stm32mp157c-ed1-scmi.dts 11flavor_dts_file-157C_EV1_SCMI = stm32mp157c-ev1-scmi.dts 12 13flavor_dts_file-135F_DK = stm32mp135f-dk.dts 14 15flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) \ 16 $(flavor_dts_file-157C_DK2_SCMI) \ 17 $(flavor_dts_file-135F_DK) 18 19flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) \ 20 $(flavor_dts_file-157A_DK1_SCMI) 21 22flavorlist-cryp-1G = $(flavor_dts_file-157C_DHCOM_PDK2) \ 23 $(flavor_dts_file-157C_ED1) \ 24 $(flavor_dts_file-157C_EV1) \ 25 $(flavor_dts_file-157C_ED1_SCMI) \ 26 $(flavor_dts_file-157C_EV1_SCMI) 27 28flavorlist-no_cryp-1G = $(flavor_dts_file-157A_DHCOR_AVENGER96) 29 30flavorlist-no_cryp = $(flavorlist-no_cryp-512M) \ 31 $(flavorlist-no_cryp-1G) 32 33flavorlist-512M = $(flavorlist-cryp-512M) \ 34 $(flavorlist-no_cryp-512M) 35 36flavorlist-1G = $(flavorlist-cryp-1G) \ 37 $(flavorlist-no_cryp-1G) 38 39flavorlist-MP15-HUK-DT = $(flavor_dts_file-157A_DK1) \ 40 $(flavor_dts_file-157C_DK2) \ 41 $(flavor_dts_file-157C_ED1) \ 42 $(flavor_dts_file-157C_EV1) \ 43 $(flavor_dts_file-157A_DK1_SCMI) \ 44 $(flavor_dts_file-157C_DK2_SCMI) \ 45 $(flavor_dts_file-157C_ED1_SCMI) \ 46 $(flavor_dts_file-157C_EV1_SCMI) 47 48flavorlist-MP15 = $(flavor_dts_file-157A_DHCOR_AVENGER96) \ 49 $(flavor_dts_file-157A_DK1) \ 50 $(flavor_dts_file-157C_DHCOM_PDK2) \ 51 $(flavor_dts_file-157C_DK2) \ 52 $(flavor_dts_file-157C_ED1) \ 53 $(flavor_dts_file-157C_EV1) \ 54 $(flavor_dts_file-157A_DK1_SCMI) \ 55 $(flavor_dts_file-157C_DK2_SCMI) \ 56 $(flavor_dts_file-157C_ED1_SCMI) \ 57 $(flavor_dts_file-157C_EV1_SCMI) 58 59flavorlist-MP13 = $(flavor_dts_file-135F_DK) 60 61flavorlist-dh-platforms = $(flavor_dts_file-157A_DHCOR_AVENGER96) \ 62 $(flavor_dts_file-157C_DHCOM_PDK2) 63 64ifneq ($(PLATFORM_FLAVOR),) 65ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 66$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 67endif 68CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 69endif 70CFG_EMBED_DTB_SOURCE_FILE ?= stm32mp157c-dk2.dts 71 72ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 73$(call force,CFG_STM32_CRYP,n) 74$(call force,CFG_STM32_SAES,n) 75endif 76 77ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_rng)),) 78$(call force,CFG_HWRNG_PTA,n) 79$(call force,CFG_WITH_SOFTWARE_PRNG,y) 80endif 81 82ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15-HUK-DT)),) 83CFG_STM32MP15_HUK ?= y 84CFG_STM32_HUK_FROM_DT ?= y 85endif 86 87ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP13)),) 88$(call force,CFG_STM32MP13,y) 89endif 90 91ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15)),) 92$(call force,CFG_STM32MP15,y) 93endif 94 95ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-dh-platforms)),) 96CFG_STM32_ALLOW_UNSAFE_PROBE ?= y 97endif 98 99# CFG_STM32MP1x switches are exclusive. 100# - CFG_STM32MP15 is enabled for STM32MP15x-* targets (default) 101# - CFG_STM32MP13 is enabled for STM32MP13x-* targets 102ifeq ($(CFG_STM32MP13),y) 103$(call force,CFG_STM32MP15,n) 104else 105$(call force,CFG_STM32MP15,y) 106$(call force,CFG_STM32MP13,n) 107endif 108ifeq ($(call cfg-one-enabled,CFG_STM32MP15 CFG_STM32MP13),n) 109$(error One of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 110endif 111ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 112$(error Only one of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 113endif 114 115include core/arch/arm/cpu/cortex-a7.mk 116 117$(call force,CFG_DRIVERS_CLK,y) 118$(call force,CFG_DRIVERS_CLK_DT,y) 119$(call force,CFG_DRIVERS_GPIO,y) 120$(call force,CFG_DRIVERS_PINCTRL,y) 121$(call force,CFG_DRIVERS_REGULATOR,y) 122$(call force,CFG_GIC,y) 123$(call force,CFG_INIT_CNTVOFF,y) 124$(call force,CFG_PSCI_ARM32,y) 125$(call force,CFG_REGULATOR_FIXED,y) 126$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 127$(call force,CFG_SM_PLATFORM_HANDLER,y) 128$(call force,CFG_STM32_SHARED_IO,y) 129 130ifeq ($(CFG_STM32MP13),y) 131$(call force,CFG_BOOT_SECONDARY_REQUEST,n) 132$(call force,CFG_CORE_ASYNC_NOTIF,y) 133$(call force,CFG_CORE_ASYNC_NOTIF_GIC_INTID,31) 134$(call force,CFG_CORE_RESERVED_SHM,n) 135$(call force,CFG_DRIVERS_CLK_FIXED,y) 136$(call force,CFG_SCMI_MSG_PERF_DOMAIN,y) 137$(call force,CFG_SECONDARY_INIT_CNTFRQ,n) 138$(call force,CFG_STM32_GPIO,y) 139$(call force,CFG_STM32_VREFBUF,y) 140$(call force,CFG_STM32MP_CLK_CORE,y) 141$(call force,CFG_STM32MP1_RSTCTRL,y) 142$(call force,CFG_STM32MP13_CLK,y) 143$(call force,CFG_STM32MP13_REGULATOR_IOD,y) 144$(call force,CFG_TEE_CORE_NB_CORE,1) 145$(call force,CFG_WITH_NSEC_GPIOS,n) 146CFG_EXTERNAL_DT ?= n 147CFG_STM32_CPU_OPP ?= y 148CFG_STM32MP_OPP_COUNT ?= 3 149# Measured latency on STM32MP13 is around 650uS so set 1mS 150CFG_STM32MP_OPP_LATENCY_US ?= 1000 151CFG_WITH_PAGER ?= n 152endif # CFG_STM32MP13 153 154ifeq ($(CFG_STM32MP15),y) 155$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 156$(call force,CFG_DRIVERS_CLK_FIXED,n) 157$(call force,CFG_HALT_CORES_SGI,15) 158$(call force,CFG_SCMI_MSG_PERF_DOMAIN,n) 159$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 160$(call force,CFG_STM32_PKA,n) 161$(call force,CFG_STM32_SAES,n) 162$(call force,CFG_STM32MP1_RSTCTRL,y) 163$(call force,CFG_STM32MP15_CLK,y) 164CFG_CORE_RESERVED_SHM ?= n 165CFG_MULTI_CORE_HALTING ?= y 166CFG_EXTERNAL_DT ?= y 167CFG_STM32_BSEC_SIP ?= y 168CFG_TEE_CORE_NB_CORE ?= 2 169CFG_WITH_PAGER ?= y 170CFG_WITH_SOFTWARE_PRNG ?= y 171endif # CFG_STM32MP15 172 173ifeq ($(CFG_WITH_PAGER),y) 174CFG_WITH_LPAE ?= n 175endif 176CFG_WITH_LPAE ?= y 177CFG_MMAP_REGIONS ?= 23 178CFG_DTB_MAX_SIZE ?= (256 * 1024) 179CFG_CORE_ASLR ?= n 180 181CFG_STM32MP_REMOTEPROC ?= n 182CFG_DRIVERS_REMOTEPROC ?= $(CFG_STM32MP_REMOTEPROC) 183CFG_REMOTEPROC_PTA ?= $(CFG_STM32MP_REMOTEPROC) 184ifeq ($(CFG_REMOTEPROC_PTA),y) 185# Remoteproc early TA for coprocessor firmware management in boot stages 186CFG_IN_TREE_EARLY_TAS += remoteproc/80a4c275-0a47-4905-8285-1486a9771a08 187# Embed public part of this key in OP-TEE OS 188RPROC_SIGN_KEY ?= keys/default.pem 189endif 190 191ifneq ($(CFG_WITH_LPAE),y) 192# Without LPAE, default TEE virtual address range is 1MB, we need at least 2MB. 193CFG_TEE_RAM_VA_SIZE ?= 0x00200000 194endif 195 196ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 197CFG_TZDRAM_START ?= 0xde000000 198CFG_DRAM_SIZE ?= 0x20000000 199endif 200 201CFG_DRAM_BASE ?= 0xc0000000 202CFG_DRAM_SIZE ?= 0x40000000 203 204# CFG_STM32MP1_SCMI_SHM_BASE and CFG_STM32MP1_SCMI_SHM_SIZE define the 205# device memory mapped SRAM used for SCMI message transfers. 206# When CFG_STM32MP1_SCMI_SHM_BASE is set to 0, the platform uses OP-TEE 207# native shared memory for SCMI communication instead of SRAM. 208# 209# When CFG_STM32MP1_SCMI_SHM_SYSRAM is enabled, OP-TEE uses the 210# last 4KB page of SYSRAM as SCMI shared memory. The switch is default 211# disabled. 212CFG_STM32MP1_SCMI_SHM_SYSRAM ?= n 213ifeq ($(CFG_STM32MP1_SCMI_SHM_SYSRAM),y) 214$(call force,CFG_STM32MP1_SCMI_SHM_BASE,0x2ffff000) 215CFG_TZSRAM_SIZE ?= 0x0003f000 216else 217CFG_STM32MP1_SCMI_SHM_BASE ?= 0 218endif 219$(call force,CFG_STM32MP1_SCMI_SHM_SIZE,0x1000) 220 221ifeq ($(CFG_STM32MP15),y) 222CFG_TZDRAM_START ?= 0xfe000000 223ifeq ($(CFG_CORE_RESERVED_SHM),y) 224CFG_TZDRAM_SIZE ?= 0x01e00000 225else 226CFG_TZDRAM_SIZE ?= 0x02000000 227endif 228CFG_TZSRAM_START ?= 0x2ffc0000 229CFG_TZSRAM_SIZE ?= 0x00040000 230ifeq ($(CFG_CORE_RESERVED_SHM),y) 231CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE)) 232CFG_SHMEM_SIZE ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_SHMEM_START)) 233endif 234else 235CFG_TZDRAM_SIZE ?= 0x02000000 236CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_TZDRAM_SIZE)) 237endif #CFG_STM32MP15 238 239CFG_STM32_BSEC ?= y 240CFG_STM32_CRYP ?= y 241CFG_STM32_ETZPC ?= y 242CFG_STM32_EXTI ?= y 243CFG_STM32_GPIO ?= y 244CFG_STM32_HASH ?= y 245CFG_STM32_I2C ?= y 246CFG_STM32_IWDG ?= y 247CFG_STM32_PKA ?= y 248CFG_STM32_RNG ?= y 249CFG_STM32_RSTCTRL ?= y 250CFG_STM32_RTC ?= y 251CFG_STM32_SAES ?= y 252CFG_STM32_TAMP ?= y 253CFG_STM32_UART ?= y 254CFG_STPMIC1 ?= y 255CFG_TZC400 ?= y 256 257# Default RTC accuracy, higher accuracy means higher power consumption 258CFG_STM32_RTC_HIGH_ACCURACY ?= n 259 260CFG_DRIVERS_I2C ?= $(CFG_STM32_I2C) 261CFG_REGULATOR_GPIO ?= $(CFG_STM32_GPIO) 262 263CFG_WITH_SOFTWARE_PRNG ?= n 264ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 265$(call force,CFG_STM32_RNG,y,Required by HW RNG when CFG_WITH_SOFTWARE_PRNG=n) 266endif 267 268ifeq ($(CFG_STPMIC1),y) 269$(call force,CFG_STM32_I2C,y) 270$(call force,CFG_STM32_GPIO,y) 271endif 272 273# If any crypto driver is enabled, enable the crypto-framework layer 274ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP \ 275 CFG_STM32_HASH \ 276 CFG_STM32_PKA \ 277 CFG_STM32_SAES),y) 278$(call force,CFG_STM32_CRYPTO_DRIVER,y) 279endif 280 281CFG_DRIVERS_RSTCTRL ?= $(CFG_STM32_RSTCTRL) 282$(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL)) 283 284CFG_WDT ?= $(CFG_STM32_IWDG) 285CFG_WDT_SM_HANDLER ?= $(CFG_WDT) 286CFG_WDT_SM_HANDLER_ID ?= 0xbc000000 287$(eval $(call cfg-depends-all,CFG_STM32_IWDG,CFG_WDT_SM_HANDLER CFG_WDT)) 288 289# Platform specific configuration 290CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 291 292# Default enable scmi-msg server if SCP-firmware SCMI server is disabled 293ifneq ($(CFG_SCMI_SCPFW),y) 294CFG_SCMI_MSG_DRIVERS ?= y 295endif 296 297# SiP/OEM service for non-secure world 298CFG_STM32_BSEC_SIP ?= n 299CFG_STM32MP1_SCMI_SIP ?= n 300ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 301$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 302$(call force,CFG_SCMI_MSG_SMT,y,Mandated by CFG_STM32MP1_SCMI_SIP) 303$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 304endif 305 306# Enable BSEC PTA for fuses access management 307CFG_STM32_BSEC_PTA ?= y 308ifeq ($(CFG_STM32_BSEC_PTA),y) 309$(call force,CFG_STM32_BSEC,y,Mandated by CFG_BSEC_PTA) 310endif 311 312CFG_STM32_DEBUG_ACCESS_PTA ?= y 313ifeq ($(CFG_STM32_DEBUG_ACCESS_PTA),y) 314$(call force,CFG_STM32_BSEC,y,Mandated by CFG_STM32_DEBUG_ACCESS_PTA) 315endif 316 317# Default disable CPU OPP support 318CFG_STM32_CPU_OPP ?= n 319 320# Default enable SCMI PTA support 321CFG_SCMI_PTA ?= y 322ifeq ($(CFG_SCMI_PTA),y) 323ifneq ($(CFG_SCMI_SCPFW),y) 324$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 325CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 326CFG_SCMI_MSG_SHM_MSG ?= y 327CFG_SCMI_MSG_SMT ?= y 328endif # !CFG_SCMI_SCPFW 329endif # CFG_SCMI_PTA 330 331CFG_SCMI_SCPFW ?= n 332ifeq ($(CFG_SCMI_SCPFW),y) 333$(call force,CFG_SCMI_SCPFW_PRODUCT,stm32mp1) 334endif 335 336CFG_SCMI_MSG_DRIVERS ?= n 337ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 338$(call force,CFG_SCMI_MSG_CLOCK,y) 339$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 340CFG_SCMI_MSG_SHM_MSG ?= y 341CFG_SCMI_MSG_SMT ?= y 342CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 343$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 344endif 345 346ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 347CFG_HWRNG_PTA ?= y 348endif 349ifeq ($(CFG_HWRNG_PTA),y) 350$(call force,CFG_STM32_RNG,y,Mandated by CFG_HWRNG_PTA) 351$(call force,CFG_WITH_SOFTWARE_PRNG,n,Mandated by CFG_HWRNG_PTA) 352$(call force,CFG_HWRNG_QUALITY,1024) 353endif 354 355# Provision enough threads to pass xtest 356ifneq (,$(filter y,$(CFG_SCMI_PTA) $(CFG_STM32MP1_SCMI_SIP))) 357ifeq ($(CFG_WITH_PAGER),y) 358CFG_NUM_THREADS ?= 3 359else 360CFG_NUM_THREADS ?= 10 361endif 362endif 363 364# Default enable some test facitilites 365CFG_ENABLE_EMBEDDED_TESTS ?= y 366CFG_WITH_STATS ?= y 367 368# Default enable software fallback on crypto drivers 369CFG_STM32_SAES_SW_FALLBACK ?= y 370 371# Enable OTP update with BSEC driver 372CFG_STM32_BSEC_WRITE ?= y 373 374# Default disable some support for pager memory size constraint 375ifeq ($(CFG_WITH_PAGER),y) 376CFG_TEE_CORE_DEBUG ?= n 377CFG_UNWIND ?= n 378CFG_LOCKDEP ?= n 379CFG_TA_BGET_TEST ?= n 380endif 381 382# Non-secure UART and GPIO/pinctrl for the output console 383CFG_WITH_NSEC_GPIOS ?= y 384CFG_WITH_NSEC_UARTS ?= y 385# UART instance used for early console (0 disables early console) 386CFG_STM32_EARLY_CONSOLE_UART ?= 4 387 388# CFG_STM32MP15_HUK enables use of a HUK read from BSEC fuses. 389# Disable the HUK by default as it requires a product specific configuration. 390# 391# Configuration must provide OTP indices where HUK is loaded. 392# When CFG_STM32_HUK_FROM_DT is enabled, HUK OTP location is found in the DT. 393# When CFG_STM32_HUK_FROM_DT is disabled, configuration sets each HUK location. 394# Either with CFG_STM32MP15_HUK_OTP_BASE, in which case the 4 words are used, 395# Or with CFG_STM32MP15_HUK_BSEC_KEY_0/1/2/3 each locating one BSEC word. 396# 397# Configuration must provide the HUK generation scheme. The following switches 398# are exclusive and at least one must be eable when CFG_STM32MP15_HUK is enable. 399# CFG_STM32MP15_HUK_BSEC_KEY makes platform HUK to be the raw fuses content. 400# CFG_STM32MP15_HUK_BSEC_DERIVE_UID makes platform HUK to be the HUK fuses 401# content derived with the device UID fuses content. See derivation scheme 402# in stm32mp15_huk.c implementation. 403CFG_STM32MP15_HUK ?= n 404CFG_STM32_HUK_FROM_DT ?= n 405 406ifeq ($(CFG_STM32MP15_HUK),y) 407ifneq ($(CFG_STM32_HUK_FROM_DT),y) 408ifneq (,$(CFG_STM32MP15_HUK_OTP_BASE)) 409$(call force,CFG_STM32MP15_HUK_BSEC_KEY_0,CFG_STM32MP15_HUK_OTP_BASE) 410$(call force,CFG_STM32MP15_HUK_BSEC_KEY_1,(CFG_STM32MP15_HUK_OTP_BASE + 1)) 411$(call force,CFG_STM32MP15_HUK_BSEC_KEY_2,(CFG_STM32MP15_HUK_OTP_BASE + 2)) 412$(call force,CFG_STM32MP15_HUK_BSEC_KEY_3,(CFG_STM32MP15_HUK_OTP_BASE + 3)) 413endif 414ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_0)) 415$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_0) 416endif 417ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_1)) 418$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_1) 419endif 420ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_2)) 421$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_2) 422endif 423ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_3)) 424$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_3) 425endif 426endif # CFG_STM32_HUK_FROM_DT 427 428CFG_STM32MP15_HUK_BSEC_KEY ?= y 429CFG_STM32MP15_HUK_BSEC_DERIVE_UID ?= n 430ifneq (y,$(call cfg-one-enabled,CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID)) 431$(error CFG_STM32MP15_HUK mandates one of CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID) 432else ifeq ($(CFG_STM32MP15_HUK_BSEC_KEY)-$(CFG_STM32MP15_HUK_BSEC_DERIVE_UID),y-y) 433$(error CFG_STM32MP15_HUK_BSEC_KEY and CFG_STM32MP15_HUK_BSEC_DERIVE_UID are exclusive) 434endif 435endif # CFG_STM32MP15_HUK 436 437CFG_TEE_CORE_DEBUG ?= y 438CFG_STM32_DEBUG_ACCESS ?= $(CFG_TEE_CORE_DEBUG) 439 440# Sanity on choice config switches 441ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 442$(error CFG_STM32MP13_CLK and CFG_STM32MP15_CLK are exclusive) 443endif 444 445CFG_DRIVERS_FIREWALL ?= y 446ifeq ($(CFG_STM32_ETZPC),y) 447$(call force,CFG_DRIVERS_FIREWALL,y) 448endif 449 450# Allow probing of unsafe peripherals. Firewall config will not be checked 451CFG_STM32_ALLOW_UNSAFE_PROBE ?= n 452 453# Enable RTC 454ifeq ($(CFG_STM32_RTC),y) 455$(call force,CFG_DRIVERS_RTC,y) 456$(call force,CFG_RTC_PTA,y) 457endif 458