1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 3flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 4flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 5flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 6 7flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) 8 9flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) 10 11flavorlist-cryp-1G = $(flavor_dts_file-157C_ED1) \ 12 $(flavor_dts_file-157C_EV1) 13 14flavorlist-no_cryp = $(flavorlist-no_cryp-512M) 15 16flavorlist-512M = $(flavorlist-cryp-512M) \ 17 $(flavorlist-no_cryp-512M) 18 19flavorlist-1G = $(flavorlist-cryp-1G) 20 21ifneq ($(PLATFORM_FLAVOR),) 22ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 23$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 24endif 25CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 26endif 27 28ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 29$(call force,CFG_STM32_CRYP,n) 30endif 31 32include core/arch/arm/cpu/cortex-a7.mk 33 34$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 35$(call force,CFG_GIC,y) 36$(call force,CFG_INIT_CNTVOFF,y) 37$(call force,CFG_PSCI_ARM32,y) 38$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 39$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 40$(call force,CFG_SM_PLATFORM_HANDLER,y) 41$(call force,CFG_WITH_SOFTWARE_PRNG,y) 42 43ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 44CFG_TZDRAM_START ?= 0xde000000 45CFG_SHMEM_START ?= 0xdfe00000 46CFG_DRAM_SIZE ?= 0x20000000 47endif 48 49CFG_TZSRAM_START ?= 0x2ffc0000 50CFG_TZSRAM_SIZE ?= 0x0003f000 51CFG_STM32MP1_SCMI_SHM_BASE ?= 0x2ffff000 52CFG_STM32MP1_SCMI_SHM_SIZE ?= 0x00001000 53CFG_TZDRAM_START ?= 0xfe000000 54CFG_TZDRAM_SIZE ?= 0x01e00000 55CFG_SHMEM_START ?= 0xffe00000 56CFG_SHMEM_SIZE ?= 0x00200000 57CFG_DRAM_SIZE ?= 0x40000000 58 59CFG_TEE_CORE_NB_CORE ?= 2 60CFG_WITH_PAGER ?= y 61CFG_WITH_LPAE ?= y 62CFG_MMAP_REGIONS ?= 23 63CFG_DTB_MAX_SIZE ?= (256 * 1024) 64 65ifeq ($(CFG_EMBED_DTB_SOURCE_FILE),) 66# Some drivers mandate DT support 67$(call force,CFG_STM32_GPIO,n) 68$(call force,CFG_STM32_I2C,n) 69$(call force,CFG_STPMIC1,n) 70$(call force,CFG_STM32MP1_SCMI_SIP,n) 71$(call force,CFG_SCMI_PTA,n) 72endif 73 74CFG_STM32_BSEC ?= y 75CFG_STM32_ETZPC ?= y 76CFG_STM32_GPIO ?= y 77CFG_STM32_I2C ?= y 78CFG_STM32_RNG ?= y 79CFG_STM32_UART ?= y 80CFG_STPMIC1 ?= y 81CFG_TZC400 ?= y 82 83ifeq ($(CFG_STPMIC1),y) 84$(call force,CFG_STM32_I2C,y) 85$(call force,CFG_STM32_GPIO,y) 86endif 87 88# Platform specific configuration 89CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 90 91# SiP/OEM service for non-secure world 92CFG_STM32_BSEC_SIP ?= y 93CFG_STM32MP1_SCMI_SIP ?= y 94ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 95$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 96$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 97endif 98 99# Default enable SCMI PTA support 100CFG_SCMI_PTA ?= y 101ifeq ($(CFG_SCMI_PTA),y) 102$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 103$(call force,CFG_SCMI_MSG_SMT_THREAD_ENTRY,y,Mandated by CFG_SCMI_PTA) 104endif 105 106CFG_SCMI_MSG_DRIVERS ?= n 107ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 108$(call force,CFG_SCMI_MSG_CLOCK,y) 109$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 110$(call force,CFG_SCMI_MSG_SMT,y) 111$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 112endif 113 114# Default enable some test facitilites 115CFG_TEE_CORE_EMBED_INTERNAL_TESTS ?= y 116CFG_WITH_STATS ?= y 117 118# Default disable some support for pager memory size constraint 119ifeq ($(CFG_WITH_PAGER),y) 120CFG_TEE_CORE_DEBUG ?= n 121CFG_UNWIND ?= n 122CFG_LOCKDEP ?= n 123CFG_CORE_ASLR ?= n 124CFG_TA_BGET_TEST ?= n 125endif 126 127# Non-secure UART and GPIO/pinctrl for the output console 128CFG_WITH_NSEC_GPIOS ?= y 129CFG_WITH_NSEC_UARTS ?= y 130# UART instance used for early console (0 disables early console) 131CFG_STM32_EARLY_CONSOLE_UART ?= 4 132