1# 1GB and 512MB DDR targets do not locate secure DDR at the same place. 2flavor_dts_file-157A_DHCOR_AVENGER96 = stm32mp157a-dhcor-avenger96.dts 3flavor_dts_file-157A_DK1 = stm32mp157a-dk1.dts 4flavor_dts_file-157C_DHCOM_PDK2 = stm32mp157c-dhcom-pdk2.dts 5flavor_dts_file-157C_DK2 = stm32mp157c-dk2.dts 6flavor_dts_file-157C_ED1 = stm32mp157c-ed1.dts 7flavor_dts_file-157C_EV1 = stm32mp157c-ev1.dts 8flavor_dts_file-157A_DK1_SCMI = stm32mp157a-dk1-scmi.dts 9flavor_dts_file-157C_DK2_SCMI = stm32mp157c-dk2-scmi.dts 10flavor_dts_file-157C_ED1_SCMI = stm32mp157c-ed1-scmi.dts 11flavor_dts_file-157C_EV1_SCMI = stm32mp157c-ev1-scmi.dts 12 13flavor_dts_file-135F_DK = stm32mp135f-dk.dts 14 15flavorlist-cryp-512M = $(flavor_dts_file-157C_DK2) \ 16 $(flavor_dts_file-157C_DK2_SCMI) \ 17 $(flavor_dts_file-135F_DK) 18 19flavorlist-no_cryp-512M = $(flavor_dts_file-157A_DK1) \ 20 $(flavor_dts_file-157A_DK1_SCMI) 21 22flavorlist-cryp-1G = $(flavor_dts_file-157C_DHCOM_PDK2) \ 23 $(flavor_dts_file-157C_ED1) \ 24 $(flavor_dts_file-157C_EV1) \ 25 $(flavor_dts_file-157C_ED1_SCMI) \ 26 $(flavor_dts_file-157C_EV1_SCMI) 27 28flavorlist-no_cryp-1G = $(flavor_dts_file-157A_DHCOR_AVENGER96) 29 30flavorlist-no_cryp = $(flavorlist-no_cryp-512M) \ 31 $(flavorlist-no_cryp-1G) 32 33flavorlist-512M = $(flavorlist-cryp-512M) \ 34 $(flavorlist-no_cryp-512M) 35 36flavorlist-1G = $(flavorlist-cryp-1G) \ 37 $(flavorlist-no_cryp-1G) 38 39flavorlist-MP15-HUK-DT = $(flavor_dts_file-157A_DK1) \ 40 $(flavor_dts_file-157C_DK2) \ 41 $(flavor_dts_file-157C_ED1) \ 42 $(flavor_dts_file-157C_EV1) \ 43 $(flavor_dts_file-157A_DK1_SCMI) \ 44 $(flavor_dts_file-157C_DK2_SCMI) \ 45 $(flavor_dts_file-157C_ED1_SCMI) \ 46 $(flavor_dts_file-157C_EV1_SCMI) 47 48flavorlist-MP15 = $(flavor_dts_file-157A_DHCOR_AVENGER96) \ 49 $(flavor_dts_file-157A_DK1) \ 50 $(flavor_dts_file-157C_DHCOM_PDK2) \ 51 $(flavor_dts_file-157C_DK2) \ 52 $(flavor_dts_file-157C_ED1) \ 53 $(flavor_dts_file-157C_EV1) \ 54 $(flavor_dts_file-157A_DK1_SCMI) \ 55 $(flavor_dts_file-157C_DK2_SCMI) \ 56 $(flavor_dts_file-157C_ED1_SCMI) \ 57 $(flavor_dts_file-157C_EV1_SCMI) 58 59flavorlist-MP13 = $(flavor_dts_file-135F_DK) 60 61flavorlist-dh-platforms = $(flavor_dts_file-157A_DHCOR_AVENGER96) \ 62 $(flavor_dts_file-157C_DHCOM_PDK2) 63 64ifneq ($(PLATFORM_FLAVOR),) 65ifeq ($(flavor_dts_file-$(PLATFORM_FLAVOR)),) 66$(error Invalid platform flavor $(PLATFORM_FLAVOR)) 67endif 68CFG_EMBED_DTB_SOURCE_FILE ?= $(flavor_dts_file-$(PLATFORM_FLAVOR)) 69endif 70CFG_EMBED_DTB_SOURCE_FILE ?= stm32mp157c-dk2.dts 71 72ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_cryp)),) 73$(call force,CFG_STM32_CRYP,n) 74$(call force,CFG_STM32_SAES,n) 75endif 76 77ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-no_rng)),) 78$(call force,CFG_HWRNG_PTA,n) 79$(call force,CFG_WITH_SOFTWARE_PRNG,y) 80endif 81 82ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15-HUK-DT)),) 83CFG_STM32MP15_HUK ?= y 84CFG_STM32_HUK_FROM_DT ?= y 85endif 86 87ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP13)),) 88$(call force,CFG_STM32MP13,y) 89endif 90 91ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-MP15)),) 92$(call force,CFG_STM32MP15,y) 93endif 94 95ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-dh-platforms)),) 96CFG_STM32_ALLOW_UNSAFE_PROBE ?= y 97endif 98 99# CFG_STM32MP1x switches are exclusive. 100# - CFG_STM32MP15 is enabled for STM32MP15x-* targets (default) 101# - CFG_STM32MP13 is enabled for STM32MP13x-* targets 102ifeq ($(CFG_STM32MP13),y) 103$(call force,CFG_STM32MP15,n) 104else 105$(call force,CFG_STM32MP15,y) 106$(call force,CFG_STM32MP13,n) 107endif 108ifeq ($(call cfg-one-enabled,CFG_STM32MP15 CFG_STM32MP13),n) 109$(error One of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 110endif 111ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 112$(error Only one of CFG_STM32MP15 CFG_STM32MP13 must be enabled) 113endif 114 115include core/arch/arm/cpu/cortex-a7.mk 116 117$(call force,CFG_DRIVERS_CLK,y) 118$(call force,CFG_DRIVERS_CLK_DT,y) 119$(call force,CFG_DRIVERS_GPIO,y) 120$(call force,CFG_DRIVERS_PINCTRL,y) 121$(call force,CFG_DRIVERS_REGULATOR,y) 122$(call force,CFG_GIC,y) 123$(call force,CFG_INIT_CNTVOFF,y) 124$(call force,CFG_PSCI_ARM32,y) 125$(call force,CFG_REGULATOR_FIXED,y) 126$(call force,CFG_SECURE_TIME_SOURCE_CNTPCT,y) 127$(call force,CFG_SM_PLATFORM_HANDLER,y) 128$(call force,CFG_STM32_SHARED_IO,y) 129 130ifeq ($(CFG_STM32MP13),y) 131$(call force,CFG_BOOT_SECONDARY_REQUEST,n) 132$(call force,CFG_CORE_ASYNC_NOTIF,y) 133$(call force,CFG_CORE_ASYNC_NOTIF_GIC_INTID,31) 134$(call force,CFG_CORE_RESERVED_SHM,n) 135$(call force,CFG_DRIVERS_CLK_FIXED,y) 136$(call force,CFG_SECONDARY_INIT_CNTFRQ,n) 137$(call force,CFG_STM32_GPIO,y) 138$(call force,CFG_STM32_VREFBUF,y) 139$(call force,CFG_STM32MP_CLK_CORE,y) 140$(call force,CFG_STM32MP1_RSTCTRL,y) 141$(call force,CFG_STM32MP13_CLK,y) 142$(call force,CFG_STM32MP13_REGULATOR_IOD,y) 143$(call force,CFG_TEE_CORE_NB_CORE,1) 144$(call force,CFG_WITH_NSEC_GPIOS,n) 145CFG_EXTERNAL_DT ?= n 146CFG_STM32MP_OPP_COUNT ?= 2 147CFG_WITH_PAGER ?= n 148endif # CFG_STM32MP13 149 150ifeq ($(CFG_STM32MP15),y) 151$(call force,CFG_BOOT_SECONDARY_REQUEST,y) 152$(call force,CFG_DRIVERS_CLK_FIXED,n) 153$(call force,CFG_HALT_CORES_ON_PANIC_SGI,15) 154$(call force,CFG_SECONDARY_INIT_CNTFRQ,y) 155$(call force,CFG_STM32_PKA,n) 156$(call force,CFG_STM32_SAES,n) 157$(call force,CFG_STM32MP1_RSTCTRL,y) 158$(call force,CFG_STM32MP15_CLK,y) 159CFG_CORE_RESERVED_SHM ?= n 160CFG_HALT_CORES_ON_PANIC ?= y 161CFG_EXTERNAL_DT ?= y 162CFG_STM32_BSEC_SIP ?= y 163CFG_TEE_CORE_NB_CORE ?= 2 164CFG_WITH_PAGER ?= y 165CFG_WITH_SOFTWARE_PRNG ?= y 166endif # CFG_STM32MP15 167 168ifeq ($(CFG_WITH_PAGER),y) 169CFG_WITH_LPAE ?= n 170endif 171CFG_WITH_LPAE ?= y 172CFG_MMAP_REGIONS ?= 23 173CFG_DTB_MAX_SIZE ?= (256 * 1024) 174CFG_CORE_ASLR ?= n 175 176CFG_STM32MP_REMOTEPROC ?= n 177CFG_DRIVERS_REMOTEPROC ?= $(CFG_STM32MP_REMOTEPROC) 178CFG_REMOTEPROC_PTA ?= $(CFG_STM32MP_REMOTEPROC) 179ifeq ($(CFG_REMOTEPROC_PTA),y) 180# Remoteproc early TA for coprocessor firmware management in boot stages 181CFG_IN_TREE_EARLY_TAS += remoteproc/80a4c275-0a47-4905-8285-1486a9771a08 182# Embed public part of this key in OP-TEE OS 183RPROC_SIGN_KEY ?= keys/default.pem 184endif 185 186ifneq ($(CFG_WITH_LPAE),y) 187# Without LPAE, default TEE virtual address range is 1MB, we need at least 2MB. 188CFG_TEE_RAM_VA_SIZE ?= 0x00200000 189endif 190 191ifneq ($(filter $(CFG_EMBED_DTB_SOURCE_FILE),$(flavorlist-512M)),) 192CFG_TZDRAM_START ?= 0xde000000 193CFG_DRAM_SIZE ?= 0x20000000 194endif 195 196CFG_DRAM_BASE ?= 0xc0000000 197CFG_DRAM_SIZE ?= 0x40000000 198 199# CFG_STM32MP1_SCMI_SHM_BASE and CFG_STM32MP1_SCMI_SHM_SIZE define the 200# device memory mapped SRAM used for SCMI message transfers. 201# When CFG_STM32MP1_SCMI_SHM_BASE is set to 0, the platform uses OP-TEE 202# native shared memory for SCMI communication instead of SRAM. 203# 204# When CFG_STM32MP1_SCMI_SHM_SYSRAM is enabled, OP-TEE uses the 205# last 4KB page of SYSRAM as SCMI shared memory. The switch is default 206# disabled. 207CFG_STM32MP1_SCMI_SHM_SYSRAM ?= n 208ifeq ($(CFG_STM32MP1_SCMI_SHM_SYSRAM),y) 209$(call force,CFG_STM32MP1_SCMI_SHM_BASE,0x2ffff000) 210CFG_TZSRAM_SIZE ?= 0x0003f000 211else 212CFG_STM32MP1_SCMI_SHM_BASE ?= 0 213endif 214$(call force,CFG_STM32MP1_SCMI_SHM_SIZE,0x1000) 215 216ifeq ($(CFG_STM32MP15),y) 217CFG_TZDRAM_START ?= 0xfe000000 218ifeq ($(CFG_CORE_RESERVED_SHM),y) 219CFG_TZDRAM_SIZE ?= 0x01e00000 220else 221CFG_TZDRAM_SIZE ?= 0x02000000 222endif 223CFG_TZSRAM_START ?= 0x2ffc0000 224CFG_TZSRAM_SIZE ?= 0x00040000 225ifeq ($(CFG_CORE_RESERVED_SHM),y) 226CFG_SHMEM_START ?= ($(CFG_TZDRAM_START) + $(CFG_TZDRAM_SIZE)) 227CFG_SHMEM_SIZE ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_SHMEM_START)) 228endif 229else 230CFG_TZDRAM_SIZE ?= 0x02000000 231CFG_TZDRAM_START ?= ($(CFG_DRAM_BASE) + $(CFG_DRAM_SIZE) - $(CFG_TZDRAM_SIZE)) 232endif #CFG_STM32MP15 233 234CFG_STM32_BSEC ?= y 235CFG_STM32_CRYP ?= y 236CFG_STM32_ETZPC ?= y 237CFG_STM32_GPIO ?= y 238CFG_STM32_HASH ?= y 239CFG_STM32_I2C ?= y 240CFG_STM32_IWDG ?= y 241CFG_STM32_PKA ?= y 242CFG_STM32_RNG ?= y 243CFG_STM32_RSTCTRL ?= y 244CFG_STM32_RTC ?= y 245CFG_STM32_SAES ?= y 246CFG_STM32_TAMP ?= y 247CFG_STM32_UART ?= y 248CFG_STPMIC1 ?= y 249CFG_TZC400 ?= y 250 251CFG_DRIVERS_I2C ?= $(CFG_STM32_I2C) 252CFG_REGULATOR_GPIO ?= $(CFG_STM32_GPIO) 253 254CFG_WITH_SOFTWARE_PRNG ?= n 255ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 256$(call force,CFG_STM32_RNG,y,Required by HW RNG when CFG_WITH_SOFTWARE_PRNG=n) 257endif 258 259ifeq ($(CFG_STPMIC1),y) 260$(call force,CFG_STM32_I2C,y) 261$(call force,CFG_STM32_GPIO,y) 262endif 263 264# If any crypto driver is enabled, enable the crypto-framework layer 265ifeq ($(call cfg-one-enabled, CFG_STM32_CRYP \ 266 CFG_STM32_HASH \ 267 CFG_STM32_PKA \ 268 CFG_STM32_SAES),y) 269$(call force,CFG_STM32_CRYPTO_DRIVER,y) 270endif 271 272CFG_DRIVERS_RSTCTRL ?= $(CFG_STM32_RSTCTRL) 273$(eval $(call cfg-depends-all,CFG_STM32_RSTCTRL,CFG_DRIVERS_RSTCTRL)) 274 275CFG_WDT ?= $(CFG_STM32_IWDG) 276CFG_WDT_SM_HANDLER ?= $(CFG_WDT) 277CFG_WDT_SM_HANDLER_ID ?= 0xbc000000 278$(eval $(call cfg-depends-all,CFG_STM32_IWDG,CFG_WDT_SM_HANDLER CFG_WDT)) 279 280# Platform specific configuration 281CFG_STM32MP_PANIC_ON_TZC_PERM_VIOLATION ?= y 282 283# Default enable scmi-msg server if SCP-firmware SCMI server is disabled 284ifneq ($(CFG_SCMI_SCPFW),y) 285CFG_SCMI_MSG_DRIVERS ?= y 286endif 287 288# SiP/OEM service for non-secure world 289CFG_STM32_BSEC_SIP ?= n 290CFG_STM32MP1_SCMI_SIP ?= n 291ifeq ($(CFG_STM32MP1_SCMI_SIP),y) 292$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_STM32MP1_SCMI_SIP) 293$(call force,CFG_SCMI_MSG_SMT,y,Mandated by CFG_STM32MP1_SCMI_SIP) 294$(call force,CFG_SCMI_MSG_SMT_FASTCALL_ENTRY,y,Mandated by CFG_STM32MP1_SCMI_SIP) 295endif 296 297# Enable BSEC PTA for fuses access management 298CFG_STM32_BSEC_PTA ?= y 299ifeq ($(CFG_STM32_BSEC_PTA),y) 300$(call force,CFG_STM32_BSEC,y,Mandated by CFG_BSEC_PTA) 301endif 302 303# Default enable SCMI PTA support 304CFG_SCMI_PTA ?= y 305ifeq ($(CFG_SCMI_PTA),y) 306ifneq ($(CFG_SCMI_SCPFW),y) 307$(call force,CFG_SCMI_MSG_DRIVERS,y,Mandated by CFG_SCMI_PTA) 308CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 309CFG_SCMI_MSG_SHM_MSG ?= y 310CFG_SCMI_MSG_SMT ?= y 311endif # !CFG_SCMI_SCPFW 312endif # CFG_SCMI_PTA 313 314CFG_SCMI_SCPFW ?= n 315ifeq ($(CFG_SCMI_SCPFW),y) 316$(call force,CFG_SCMI_SCPFW_PRODUCT,stm32mp1) 317endif 318 319CFG_SCMI_MSG_DRIVERS ?= n 320ifeq ($(CFG_SCMI_MSG_DRIVERS),y) 321$(call force,CFG_SCMI_MSG_CLOCK,y) 322$(call force,CFG_SCMI_MSG_RESET_DOMAIN,y) 323CFG_SCMI_MSG_SHM_MSG ?= y 324CFG_SCMI_MSG_SMT ?= y 325CFG_SCMI_MSG_SMT_THREAD_ENTRY ?= y 326$(call force,CFG_SCMI_MSG_VOLTAGE_DOMAIN,y) 327endif 328 329ifneq ($(CFG_WITH_SOFTWARE_PRNG),y) 330CFG_HWRNG_PTA ?= y 331endif 332ifeq ($(CFG_HWRNG_PTA),y) 333$(call force,CFG_STM32_RNG,y,Mandated by CFG_HWRNG_PTA) 334$(call force,CFG_WITH_SOFTWARE_PRNG,n,Mandated by CFG_HWRNG_PTA) 335$(call force,CFG_HWRNG_QUALITY,1024) 336endif 337 338# Provision enough threads to pass xtest 339ifneq (,$(filter y,$(CFG_SCMI_PTA) $(CFG_STM32MP1_SCMI_SIP))) 340ifeq ($(CFG_WITH_PAGER),y) 341CFG_NUM_THREADS ?= 3 342else 343CFG_NUM_THREADS ?= 10 344endif 345endif 346 347# Default enable some test facitilites 348CFG_ENABLE_EMBEDDED_TESTS ?= y 349CFG_WITH_STATS ?= y 350 351# Default enable software fallback on crypto drivers 352CFG_STM32_SAES_SW_FALLBACK ?= y 353 354# Enable OTP update with BSEC driver 355CFG_STM32_BSEC_WRITE ?= y 356 357# Default disable some support for pager memory size constraint 358ifeq ($(CFG_WITH_PAGER),y) 359CFG_TEE_CORE_DEBUG ?= n 360CFG_UNWIND ?= n 361CFG_LOCKDEP ?= n 362CFG_TA_BGET_TEST ?= n 363endif 364 365# Non-secure UART and GPIO/pinctrl for the output console 366CFG_WITH_NSEC_GPIOS ?= y 367CFG_WITH_NSEC_UARTS ?= y 368# UART instance used for early console (0 disables early console) 369CFG_STM32_EARLY_CONSOLE_UART ?= 4 370 371# CFG_STM32MP15_HUK enables use of a HUK read from BSEC fuses. 372# Disable the HUK by default as it requires a product specific configuration. 373# 374# Configuration must provide OTP indices where HUK is loaded. 375# When CFG_STM32_HUK_FROM_DT is enabled, HUK OTP location is found in the DT. 376# When CFG_STM32_HUK_FROM_DT is disabled, configuration sets each HUK location. 377# Either with CFG_STM32MP15_HUK_OTP_BASE, in which case the 4 words are used, 378# Or with CFG_STM32MP15_HUK_BSEC_KEY_0/1/2/3 each locating one BSEC word. 379# 380# Configuration must provide the HUK generation scheme. The following switches 381# are exclusive and at least one must be eable when CFG_STM32MP15_HUK is enable. 382# CFG_STM32MP15_HUK_BSEC_KEY makes platform HUK to be the raw fuses content. 383# CFG_STM32MP15_HUK_BSEC_DERIVE_UID makes platform HUK to be the HUK fuses 384# content derived with the device UID fuses content. See derivation scheme 385# in stm32mp15_huk.c implementation. 386CFG_STM32MP15_HUK ?= n 387CFG_STM32_HUK_FROM_DT ?= n 388 389ifeq ($(CFG_STM32MP15_HUK),y) 390ifneq ($(CFG_STM32_HUK_FROM_DT),y) 391ifneq (,$(CFG_STM32MP15_HUK_OTP_BASE)) 392$(call force,CFG_STM32MP15_HUK_BSEC_KEY_0,CFG_STM32MP15_HUK_OTP_BASE) 393$(call force,CFG_STM32MP15_HUK_BSEC_KEY_1,(CFG_STM32MP15_HUK_OTP_BASE + 1)) 394$(call force,CFG_STM32MP15_HUK_BSEC_KEY_2,(CFG_STM32MP15_HUK_OTP_BASE + 2)) 395$(call force,CFG_STM32MP15_HUK_BSEC_KEY_3,(CFG_STM32MP15_HUK_OTP_BASE + 3)) 396endif 397ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_0)) 398$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_0) 399endif 400ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_1)) 401$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_1) 402endif 403ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_2)) 404$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_2) 405endif 406ifeq (,$(CFG_STM32MP15_HUK_BSEC_KEY_3)) 407$(error Missing configuration switch CFG_STM32MP15_HUK_BSEC_KEY_3) 408endif 409endif # CFG_STM32_HUK_FROM_DT 410 411CFG_STM32MP15_HUK_BSEC_KEY ?= y 412CFG_STM32MP15_HUK_BSEC_DERIVE_UID ?= n 413ifneq (y,$(call cfg-one-enabled,CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID)) 414$(error CFG_STM32MP15_HUK mandates one of CFG_STM32MP15_HUK_BSEC_KEY CFG_STM32MP15_HUK_BSEC_DERIVE_UID) 415else ifeq ($(CFG_STM32MP15_HUK_BSEC_KEY)-$(CFG_STM32MP15_HUK_BSEC_DERIVE_UID),y-y) 416$(error CFG_STM32MP15_HUK_BSEC_KEY and CFG_STM32MP15_HUK_BSEC_DERIVE_UID are exclusive) 417endif 418endif # CFG_STM32MP15_HUK 419 420CFG_TEE_CORE_DEBUG ?= y 421CFG_STM32_DEBUG_ACCESS ?= $(CFG_TEE_CORE_DEBUG) 422 423# Sanity on choice config switches 424ifeq ($(call cfg-all-enabled,CFG_STM32MP15 CFG_STM32MP13),y) 425$(error CFG_STM32MP13_CLK and CFG_STM32MP15_CLK are exclusive) 426endif 427 428CFG_DRIVERS_FIREWALL ?= y 429ifeq ($(CFG_STM32_ETZPC),y) 430$(call force,CFG_DRIVERS_FIREWALL,y) 431endif 432 433# Allow probing of unsafe peripherals. Firewall config will not be checked 434CFG_STM32_ALLOW_UNSAFE_PROBE ?= n 435 436# Enable RTC 437ifeq ($(CFG_STM32_RTC),y) 438$(call force,CFG_DRIVERS_RTC,y) 439endif 440